This is version 2K10A of the Suska IP core. ------------------------------------------ ------------------------------------------ Content: 1. Introduction 2. Changelog 3. Known issues 4. What's ahead ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- Introduction: This core is an Atari compatible core for the different ST machines. It includes all custom chips like GLUE, MMU (MCU), SHIFTER, DMA, BLITTER and SHADOW (Stacy, STBook) as also cores for the LSI chips originally used in these machines like the 68000 CPU (68K00), the multi function port MFP, the WD1772 floppy controller and the Yamaha sound chip YM2149. There are several add ons like SD card interface, IDE interface, real time clock, sound with a CODEC, SCSI/ ACSI bridge and a Bootloader prepared for the Suska-III-C hardware for loading the operation system to the flash memory. There are also some hardware extensions on the Suska-III-C like USB and Ethernet. Distribution: With release 2K8B the file structure of the distribution has changed in the following way: - All required source code to build the machine is available. - We provide support for the Suska-III-C hardware platform in the Altera section. - We do not provide implementation support for other hardware platforms like Actel, Lattice or Xilinx. - There is some top level file support for the Xilinx platform in the rtl/vhdl/suska directory. Compiler notes: The core is compiled (and tested) with following integrated development environments: Altera: Quartus II version 8.1 and 9.1. Xilinx: Although this release is prepared for Xilinx we dropped since version 2K10A testing the system on Xilinx development tools or Xilinx hardware. Whats's new: The version 2K10A is a maintenance release which fixes some of the known issues. the most important changes are a modified ACSI/SCSI bridge to get more devices working, a fixed real time clock module and 14MB of memory support. See the changelog for further details. Above these details there is an experimental change of the IDE interface to achieve full compatibility of CF-Card between Suska-III-C and a PC. This means we have now CF-Cards bootable under TOS and fully read and write access under TOS or Windows / Linux etc. To get the things running it is necessary to prepare the cards with a new version of the HDDRUTIL of Uwe Seimet and have installed the HDDRIVER. Please be aware that the such installed cards are not compatible with old ST machines. Progress and known issues: The core is tested successfully on the Suska-III-C prototype, series-0 and series-1 boards. The results are as follows: Operating systems: This core is tested with the following operating systems: TOS1.00 : works with Slowdown-CPU feature (configuration switch 1 on). Reason: requires 8MHz system. TOS1.02 : fails. Reason: requires 8MHz system. TOS1.04 : works with Slowdown-CPU feature (configuration switch 1 on). Reason: requires 8MHz system. TOS1.62 : works. TOS2.05 : works. TOS2.06 : works. emuTos : works. Applications: We have tested several applications and there are a lot of reports of tests done by the community. The detailed results of such tests are beyond the scope of this document. Generally spoken, a lot of applications work fine. The most critical applications seems to be several games. We would appreciate, if someone could set up a data bench reflecting the test results. We will provide the information concerning this issue at www.experiment-s.de Configware Versions: Since the 2K9A release of the Suska IP-Core we will provide tested configuration files in the config-files directory. We store improved versions in chronological order So the latest files will result in the most improved hardware. ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- Chanelog: Revision 2K10A - Changed logic in the 25912 control section to enable the 14MB RAM. Introduced EN_RAM_14MB therefore . - Changed DTACKn logic to enable 14MB correctly in the 25912 control section. - Reduced MCU_ADR from 25 to 23 bits in this file. - Several minor changes in the 68K00 to meet better design tool compatibility. - Several changes to meet better compatibility with SCSI-II devices in the module WF_ACSI_SCSI_IF_SOC. - Fixes in this top level concerning SCSI_WR, SCSI_RD and SCSI_DPn. - Fixed VMAn for RTC access in the GLUE address register section. - Several fixes in all WF5C15_139xIP_.. files to get the RTC working properly. - odified the IDE bus access to achieve TOS/PC compatibility with bootable CF cards under TOS. WF - 20100620. Revision 2K9B - RESET_INn is now SYS_RESET_INn in the MCU top level file. - RESET_OUTn is now SYS_RESET_OUTn in the MCU top level file. - Replaced RESETn filter by new RESET_INn in the MCU top level file. - Renamed the comp sync signal SH_COLOR to SH_CSYNCn. - Removed DMAn in the module WF_IDE. - Changed the MDAT_BUFFER clock from 64MHz to 32MHz due to better stability. - Fixed 68000 bus interface: UDSn and LDSn logic not working correct with waitstates in some cases. - Changed UNLK A7 logic due to compatibility reasons with MC68000 in the module wf68k00ip_control. - Fixed a timing bug in the 68K00 bus arbitration state register. - Small improvement the process TIME_SLICES in module wf25912ip_ctrl. - Linewidth correction in wf25912ip_video_counter_sd. - Bugfix in the BANK_SWITCH concerning 14MB of memory in the MCU control file. - Numerous changes in wf25913ip_ctrl due to new wf25915ip_bus_arbiter_v2. These changes result - wf25915ip_bus_arbiter_v2. - Changed timing of SECT_CNT_ZEROn in module wf25913_registers. - Fixed a bug in the sector counter in module wf25913_registers. - Fixed bus access timing in module wf25913_registers. - Introduced CTRL_SRC_SEL in the wf25913 registers and top level. - Replaced port DMA_SRC_SEL by DRIVE_SEL in the wf25913 top level to meet better ACSI bus timing. - New modeling of FIFO_HI in the DMA FIFO control section to meet the requirements for the new DMA controller. - Adjusted FIFO_LOW in the DMA FIFO control section due to new FIFO_HI. - Fixed DMA_EN logic and replaced DMA_RDn, DMA_WRn by DMA_EN in the DMA register section. - Removed the unneccesary DMA_LOCKn in the module wf25915ip_adrdec. - Changes in the related package and top level files to meet the new wf25915ip_bus_arbiter_V1. - IACKn is now also locked by ASn in the module wf25915ip_interrupts. - Fixed a FCSn bug in the GLUE's address decoding. - Fixed a DMA_MODE_CSn bug in the GLUE's address decoding. - Fixed a bug in the GLUE bus arbiter's BRn_LOGIC process not to start the DMA operation unintendedly. - Removed DMA_LOCKn in the module wf25915ip_interrupts. - Partially rewritten the wf25915ip_bus_arbiter_V1, removed DMA_SYNC again (not necessary any longer). - these changes results in version wf25915ip_bus_arbiter_v2. - Fixed the interrupt logic in the module wf6850ip_ctrl_status. - Introduced a minor RTSn correction in the module wf6850ip_ctrl_status. - Fixed the timing for DR_LOAD in the 1772 control section. WF - 20091224. Revision 2K9A - Enhancements in the video system to drive modern TFTs or multisyncs. - The RESETn pin is not asserted by the RESET_BOOTn any more but by the FLASH_RESETn. This change was necessary because the FLASH's reset is on the series boards connected to the system reset. - New: PLL_ARESET logic for resetting the phase locked loops during system startup. - New: Clock synchronization in the MCU control file (process TIME_SLICES). This improves system startup. - New: Clock synchronization in the WF25914IP_CR_SHIFT_REG. This improves system startup. - Changed LATCHn behaviour in the MCU control file (No unnecessary bus switching). - New: process SLOW_CPU for lowering the CPU speed (compatibility reasons to TOS1.00 up to TOS1.04). - Fixed interrupt polarity for TA_I and TB_I in the MFP core. - Minor improvements in the MFP timer section. - Several fixes concerning colour corrections in the Shifter's chroma shift registers. - Fixed CPU exception processing to improve system startup. - A couple of minor bug fixes. - WF - 20090620. Version 2K8B: - CPU68K00 is fully working now. Thanks to T. Gubener for the intensive help during debugging. - There is now a fully working SD-RAM memory controller unit (MCU) replacing the legacy DRAM MCU. The SD-RAM MCU is capable to address the full portion of the 23 address lines respective 16MB. - There are some significant improvements over version 2K8A in the WD1772 compatible floppy - controller core. - The bootloader works now fine. - The IDE and ACSI hard disk access work now fine. - WF - 20081224. Version 2K8A: - Added a new MMU model to meet the requirements of the SDRAMs used on the 'Suska-Classic' hardware. - Fixed CPU core to run the operating system emutos and TOS 1.00. - Minor changes in a couple of modules. - Bugfixes in a couple of modules. - Added bootloader to the core. - Enhancements in the toplevel files to run different TOS versions. - The core's main frequency is now 16MHz. WF - 20080714. Version 2K7B: - Added a further top level file for the new Suska III series hardware. - Improved the flash boot loader unit. - Minor changes in the WD1772 compatible controller. - Bug fixes and changes in the 68K00 ip core. For more information see the readme files in the 68K00 vhdl directory (rtl). - Minor fixes and changes in several modules to meet the requirements for the new hardware. WF - 20071224. Version 2K7A: - Withdrawn the RTC interface for the I2C real time chip DS1337 (Maxim / Dallas). Introduced the DS139x real time chip bridge wich features the simple SPI interface of the DS1392 or the DS1393. - Added an interface for an audio DAC (AD5302). - Added a ACSI to SCSI interface. See the respective top level file for more information. - Added an IDE interface. See the respective top level file for more information. - Added an interface to connect SD cards via the ACSI bus. This component is based on Miroslav Nohaj's - "Jookie's" project named Satan Disk. - Added a boot loader mechanism for the operating system flash device. See the component WF_FLASHBOOT for more information. - Provided a keyboard switch to select either the original keyboard and mouse or the Eiffel system. - Several fixes improvments in several files. - The CPU is now (hopefully) working. - Code modified to fit 100% to the Suska-III hardware. - Added a module to control the serial DAC used in the SUSKA-III hardware. - For more information concerning the CPU 68K00 see the respective readme file in the rtl directory of the 68K00 core. WF - 20070601. Version 2K6B: - Modified the source files to compile with the XILINX web edition software (ISE8.2i). - Introduced the 68000 IP core in an alpha version. - Introduced the RP5C15 interface replacement for the DS1337 which is I2C also alpha state. - Added top level files for the use in a system on a programmable chip. These files all have the same extension ..._top_soc.vhd. There are now to possibilities: fistly use the top level entities ..._top.vhd for stand alone chip versions. secondly use the ..._top_soc.vhd. for an integrated system on one chip. - Added a top level file for the ST(E) compatible machine. This file is located in the WF_SUSKA directory. - Some minor bug fixes in several files. See the file histories for more information. WF - 20061224. Version 2K6A: Initial release of a set of models for the most 1040ST chips as follows: - BLITTER: Complete implementation of the famous ATARI bit block transfer processor. - SHIFTER: Video shifter with all enhancements of the STE machines (microwire interface, 4 bit per colour DA resolution, fine scrolling feature). Aditionally STBook or STACY SHADOW registers for the power management. - GLUE: 1040 GLUE logic with enhancements concerning TOS ROM configuration, real time clock decoding, interrupt logic and some minor STE machine logic. - MCU: Memory controller as in the ST or STE machines. - DMA: Direct memory access controller compatible with the ST DMA controller. - WD1772: Floppy drive controller core with enhancements concerning HD floppies. Built in digital phase locked loop (PLL) for optimal data recovery. Besides these enhance- ments, the core is highly compatible with the WD1772 of the Western Digital Cor- poration. - YM2149: Sound controller IP core with a digital DA converter approach with pulse width modulation logic. The core is compatible with Yamaha's YM2149 chip. - UART: The serial interface core behaves like the 6850 ACIA. - MFP: A solution for a multi function port identically to the MC68901 from Motorola. - SHADOW: Atari had the STACY and the STBook, which were notebooks driving a LCD panel with a screen resolution of 640x400. Since these custom LCD panels are obsolete, the new SHADOW IP (intelectual property) core drives a standard VGA display with 640x480 dots in monochrome mode. WF - 20060609. ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- Known issues 1. The IDE interface features Master/Slave operation. There was no way to operate a SD-Card configured as master and a 2.5" IDE hard drive configured as slave up to now. This seems not to be caused by the core. 2. emutos detects a 68010 CPU by the implemented MOVE_FROM_CCR operation. This leads to a wrong TRAP operation because the 68010 has a 4 word stack frame while the 68K00 stacks only three words. 3. The Joyports seems to have a wrong wiring (wrong directions when Joysticks are used). 4. eMuTos version 0.8.3 do not start with PS/2 keyboard and PS/2 mouse. An original keyboard is required. 5. Using HDDRIVER's AUTOPARK accessory version 8.23 causes the TOS2.06 system hang when selecting the Desktop info menu. Workaround: rename or delete the accessory. 6. Loading Sound.cpx causes a system hang. ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- What's ahead: Since this ip core is now developed for about 7 years and is publicly available since 2006, there are only a few things left over for further development concerning the SUSKA-III-C boards and for the upcoming Suska-III-B. We will try to provide the following things as soon as possible: - 68K30 core: this is the implementation of an ip core which will be capable running 68030 code. Thus it is possible to run things like the well known MINT operating system. We firstly will provide this core for the Suska-III-C boards. - Ethenet stack: this ip core will be made available if someone will be willing to write a driver for it. - USB interface: this ip core will be made available if someone will be willing to write a driver for it. - Enhanced sound capability (DMA sound): this is also a topic of codesigning the ip core with it's related software driver. - Operate SD-Cards on the ACSI DMA channel. - Prepare the MINT operating system on Suska-III-C. - Enhance the video capabilities providing higher resolutions meeting the requirements for the MINT operating system. - Add a memory management unit to the core to ease the use of operating systems like Linux. 20100620 Enjoy Wolfgang Foerster