This is version 2K14B of the Suska IP core. ------------------------------------------ ------------------------------------------ Content: 1. Introduction 2. Distribution 3. Compiler notes 4. Whant's new / work in progress 5. What's ahead 6. Configware versions 7. Progress 8. Known issues 9. Revision history ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- 1. Introduction: This core is an Atari compatible core for the different ST machines. It includes all custom chips like GLUE, MMU (MCU), SHIFTER, DMA, BLITTER and SHADOW (Stacy, STBook) as also cores for the LSI chips originally used in these machines like the 68000 CPU (68K00), the multi function port MFP, the WD1772 floppy controller and the Yamaha sound chip YM2149. There are several add ons like SD card interface, IDE interface, real time clock, sound with a CODEC, SCSI/ ACSI bridge and a Bootloader prepared for the Suska-III-C hardware for loading the operation system to the flash memory. There are also some hardware extensions on the Suska-III-C like USB and Ethernet. With the 2K18B version there are Atari Falcon custom chips COMBEL, VIDEL and Falcon-DMA available. See below for more information. 2. Distribution: With release 2K13B the file structure of the distribution has changed in the following manner: - For the Suska-III-C machine all required source code is available to build this machine. - For the Suska-III-B machine all required source code except the SD drives module is available to build this machine. Use an empty wrapper for the SD drives module where required. - We provide support for the Suska-III-C hardware and for the Suska-III-B platform in the backend/Altera section. - We do not provide implementation support for other hardware platforms like Microsemi (formerly Actel), Lattice or Xilinx. - There is some top level file support for the Xilinx platform in the rtl/vhdl/suska-c directory. 3. Compiler notes: The core is compiled (and tested) with following integrated development environments: Altera: All Quartus II versions up to V13.1. Xilinx: Although this release is prepared for Xilinx we dropped since version 2K10A testing the system on Xilinx development tools or Xilinx hardware. Feel free to contribute. Lattice / Microsemi / others: Testers are welcome. 4. Whats's new / work in progress: Since the Suska-III-C core is developed fore several years, there are now new features nor changes in comparision with the 2K14A configware. There is progress to provide a hardware which is Atari Falcon compatible. For this reason, there are new hardware modules for the Falcon: the Combel, the Videl and the Falcon-DMA in an untested condition up to now. Fore further work a new hardware is required. If it is available, the work on these modules will proceed. 5. What's ahead: STE compatible IP core (Suska-III-C): For the STE compatible ip core there are a few things left for further development concerning the SUSKA-III-C boards and for Suska-III-B. We have dropped some software related items listed here in the previous release notes. This is because we decided to focus on the hardware development and let the community work on the software stuff. So there are plans to enhance the Suska-III-C as follows: - Preparation for more modern TFT displays. - Getting USB Mouse and keyboard to work. - Provide some high quality case for the Suska-III-C bard. STE compatible IP core (Suska-III-B): - Completion of the Configware and the system controller's firmware to get the boards running. Provide an internal SD card hard drive like the GigaFile solution. Falcon compatible IP core (Suska-III-T2): This is the most sophisticated part of the Suska project. Beside the three Falcon custom chips listed above we need also a 68030 compatible central processing unit. There are two of those ip cores done by myself. One is a fully featured complex instruction set computer (CISC) CPU with 68030 instruction set, addressing modes, memory management unit, instruction and data cache and the coprocessor interface. It is developed in a pipelined architecture. The shifter unit is designed as a barrel shifter with one clock cycle delay. This is the 68K30 version. I will not release this CPU in the near future. Interested people can contact me concerning this IP core. The other version is a subset of the 68K30 called 68K30L. This ip core is finished since a few days but will not make it in this 2K14B release. It also features all addressing modes and instructions but does not have MMU, cache and coprocessor interface. The shifter unit is modeled as a convetional shift register with sever clock cycles delay. The 68K30L will probably come under the Cern open hardware (COHL) lisence. 6. Configware Versions: Since the 2K9A release of the Suska IP-Core we will provide tested configuration files in the config-files directory. We store improved versions in chronological order So the latest files will result in the most improved hardware. 7. Progress: The core is tested successfully on the Suska-III-C prototype, series-0 and series-1 boards. The results are as follows: Operating systems: TOS1.00 : works with Slowdown-CPU feature (configuration switch 1 on). Reason: requires 8MHz system. TOS1.02 : fails. Reason: requires 8MHz system. TOS1.04 : works with Slowdown-CPU feature (configuration switch 1 on). Reason: requires 8MHz system. TOS1.62 : works. TOS2.05 : works. TOS2.06 : works. emuTos : works. Applications: We have tested several applications and there are a lot of reports of tests done by the community. The detailed results of such tests are beyond the scope of this document. Generally spoken, a lot of applications work fine. The most critical applications seems to be several games. We would appreciate, if someone could set up a data bench reflecting the test results. We will provide the information concerning this issue at www.experiment-s.de 8. Known issues 1. The IDE interface features Master/Slave operation. There was no way to operate a SD-Card configured as master and a 2.5" IDE hard drive configured as slave up to now. This seems not to be caused by the core. 2. Using HDDRIVER's AUTOPARK accessory version 8.23 causes the TOS2.06 system hang when selecting the Desktop info menu. Workaround: rename or delete the accessory. 3. Loading Sound.cpx causes a system hang. 9. Revision history: Revision 2K14B No changes since the 2K14A release for the Suska-III-C hardware. New Falcon compatible COMBEL module. New Falcon compatible DMA module. New Falcon compatible VIDEL module. WF - 20141224 Revision 2K14A 20140628 WF 68K00 address registers: fixed the INDEX logic concerning the use of SSP and USP. 68K00 address registers: fixed the index logic concerning scaling. 68K00 address registers: fixed the exchange of registers for SSP and USP. 68K00 ALU: fixed the ABCD, NBCD and SBCD integer calculation. 68K00 ALU: fixed the wrong remainder's sign for the DIVS operation. 68K00 Interrupt controller: fixed wrong interrupt vector calculation in autovectoring mode. 68K00 top level: Small changes for the IPL_In filter. ACSI-SCSI bridge: rearranged the complete selection timeout to improve drive compatibility. WF - 20140623 Revision 2K13B 20131224 WF 68K00 ALU: Fixed the N flag for the CHK operation. 68K00 ALU: DIV_RESULT_VAR is now 64 bit wide to handle the overflow correctly. Opcode decoder: Minor optimizations. 68K00 interrupt controller: Changed the sequence for sampling the interrupt vector. It is now sampled before stacking. 68901 USART: separate Transmit and receive buffer and some minor changes. Thanks to Peter Neways (20121218). WF_ACSI_SCSI_IF_SOC: changed the selection timeout to work without TIMEOUT. WF_ACSI_SCSI_IF_SOC: some additional minor changes. GLUE address decoder: Disabled signal SCCn (emuTos crashes due to not present SCC). DMA register section: several changes due to implementation of the 5380. This top level: implementation of the 5380 SCSI controller. WF - 20131224 Revision 2K13A 20130620 WF Minor changes in WF_ACSI_SCSI_IF_SOC to improve data integrity (DATA_BUFFER). Improvements in WF_ACSI_SCSI_IF_SOC concerning compatibility to devices using the message phases. WF_ACSI_SCSI_IF_SOC: changed DATA_EN logic for ACSI and SCSI. This top level: changed the logic for the ACSI_RDn and ACSI_WRn signals. Fixed the VMAn timing in the 68K00 bus controller. Thanks to Igor Majstorovic for the information. Top level: changes concerning the ACSI and SCSI bus logic. The both interfaces can now be used in parallel. Top level: removed the RESET_Sn temporary fix. It is not used any more due to a correction in the system microcontroller firmware. Top level: minor change for the BERR_I signal. WF - 20130620 Revision 2K12B 20121224 WF WF_ACSI_SCSI_IF_SOC: Introduced the SLOW_MODE to achieve boot capability with TOS. 25913 controller: removed some old stuff (package counter). WF - 20121224 Revision 2K12A Improvements and work in progress are described above. Detailed changes listed in the top level file of the Suska project are as follows: - GLUE: Introduced GL_STE_A4299_CS for the audio codec. - WF_RTC5C15 registers: changed TIMER_EN to EOSCn with inverted functionality. - New feature: Release of the CS4299 audio codec AC97 controller (WF_SND4299). - Removed DTACKn for the RTC_CS in ST section (validated via VPAn) in the GLUE top level. - Glue address register section: minor change concerning CMPCSn (UDSn locked now). - MCU dma control: readback of the DMA base and counter register is now 24 bit wide. - MCU dma sound module: a minor change concerning SINTn. - Changed the SDATA_L and SDATA_R from linear to 2's complement. - Changes in WF_AUDIO_DAC due to audiodata is now 2's complement. - GPIP_IN(7) is now: SINT_IO7 or INT_4299. - WF_ACSI_SCSI_IF_SOC: implementation of selection timeout. - WF_ACSI_SCSI_IF_SOC: provided LINK97 compatibility (see SCSI_MODE). - RTC5C15-139x control: minor changes to improve data integrity. - Fixed some compatibility issues to the RP5C15 in WF5C15_139xIP_REGISTERS. WF - 20120620 Revision 2K11B - This version is improved by some effort to achieve better core timing using timing driven synthesis - techniques. This results in a highly robust implementation for the Suska-III-C board file. All other - changes are listed in the top level file of the Suska project. WF - 20111226 Revision 2K11A - A minor change in the data readback logic of the 68901 timers (RWn is now taken into consideration). - Cleaned up the condition code logic in the 68K00 shifter section. WF - 20110620 Revision 2K10B - Introduced screen resolution switch SEL_640x400 in the shadow unit. - Shadow control section: several optimizations to meet the operation of the LCD with 640x400 resolution. - Shadow FIFO unit: changed the data output from pipelined to unpipelined. - Changed entity name WF_SD_CARD to WF_ACSI_SDC. - A bunch of changes in the Shifter's microwire interface. - Changes concerning the monochrome monitor detection in the 25912 top level file. - A bunch of changes in the MMU DMA sound control logic. - Completely rewritten the DMA sound control logic in the SHIFTER module. - There is now a FIFO with a depth of 4 and a width of 16 bits in the SHIFTER's DMA sound control. - Minor changes in the MMU control logic concerning the DMA sound. - Changes in this top level concerning DMA sound control respective the monochrome detection. - 25912 top level: minor modification concerning the changes of the DMA sound module. - 25912 address decoder: Removed the colour monitor processor access for the addressx "8901" because - the DMA sound control register resides in the 25912 MCU dma sound control logic. - Several behavioural changes in the audio DAC module. - Modified the audio DAC module by introduction of FCLK (this fixes distorted sound). WF - 20101227. Revision 2K10A - Changed logic in the 25912 control section to enable the 14MB RAM. Introduced EN_RAM_14MB therefore . - Changed DTACKn logic to enable 14MB correctly in the 25912 control section. - Reduced MCU_ADR from 25 to 23 bits in this file. - Several minor changes in the 68K00 to meet better design tool compatibility. - Several changes to meet better compatibility with SCSI-II devices in the module WF_ACSI_SCSI_IF_SOC. - Fixes in this top level concerning SCSI_WR, SCSI_RD and SCSI_DPn. - Fixed VMAn for RTC access in the GLUE address register section. - Several fixes in all WF5C15_139xIP_.. files to get the RTC working properly. - odified the IDE bus access to achieve TOS/PC compatibility with bootable CF cards under TOS. WF - 20100620. Revision 2K9B - RESET_INn is now SYS_RESET_INn in the MCU top level file. - RESET_OUTn is now SYS_RESET_OUTn in the MCU top level file. - Replaced RESETn filter by new RESET_INn in the MCU top level file. - Renamed the comp sync signal SH_COLOR to SH_CSYNCn. - Removed DMAn in the module WF_IDE. - Changed the MDAT_BUFFER clock from 64MHz to 32MHz due to better stability. - Fixed 68000 bus interface: UDSn and LDSn logic not working correct with waitstates in some cases. - Changed UNLK A7 logic due to compatibility reasons with MC68000 in the module wf68k00ip_control. - Fixed a timing bug in the 68K00 bus arbitration state register. - Small improvement the process TIME_SLICES in module wf25912ip_ctrl. - Linewidth correction in wf25912ip_video_counter_sd. - Bugfix in the BANK_SWITCH concerning 14MB of memory in the MCU control file. - Numerous changes in wf25913ip_ctrl due to new wf25915ip_bus_arbiter_v2. These changes result - wf25915ip_bus_arbiter_v2. - Changed timing of SECT_CNT_ZEROn in module wf25913_registers. - Fixed a bug in the sector counter in module wf25913_registers. - Fixed bus access timing in module wf25913_registers. - Introduced CTRL_SRC_SEL in the wf25913 registers and top level. - Replaced port DMA_SRC_SEL by DRIVE_SEL in the wf25913 top level to meet better ACSI bus timing. - New modeling of FIFO_HI in the DMA FIFO control section to meet the requirements for the new DMA controller. - Adjusted FIFO_LOW in the DMA FIFO control section due to new FIFO_HI. - Fixed DMA_EN logic and replaced DMA_RDn, DMA_WRn by DMA_EN in the DMA register section. - Removed the unneccesary DMA_LOCKn in the module wf25915ip_adrdec. - Changes in the related package and top level files to meet the new wf25915ip_bus_arbiter_V1. - IACKn is now also locked by ASn in the module wf25915ip_interrupts. - Fixed a FCSn bug in the GLUE's address decoding. - Fixed a DMA_MODE_CSn bug in the GLUE's address decoding. - Fixed a bug in the GLUE bus arbiter's BRn_LOGIC process not to start the DMA operation unintendedly. - Removed DMA_LOCKn in the module wf25915ip_interrupts. - Partially rewritten the wf25915ip_bus_arbiter_V1, removed DMA_SYNC again (not necessary any longer). - these changes results in version wf25915ip_bus_arbiter_v2. - Fixed the interrupt logic in the module wf6850ip_ctrl_status. - Introduced a minor RTSn correction in the module wf6850ip_ctrl_status. - Fixed the timing for DR_LOAD in the 1772 control section. WF - 20091224. Revision 2K9A - Enhancements in the video system to drive modern TFTs or multisyncs. - The RESETn pin is not asserted by the RESET_BOOTn any more but by the FLASH_RESETn. This change was necessary because the FLASH's reset is on the series boards connected to the system reset. - New: PLL_ARESET logic for resetting the phase locked loops during system startup. - New: Clock synchronization in the MCU control file (process TIME_SLICES). This improves system startup. - New: Clock synchronization in the WF25914IP_CR_SHIFT_REG. This improves system startup. - Changed LATCHn behaviour in the MCU control file (No unnecessary bus switching). - New: process SLOW_CPU for lowering the CPU speed (compatibility reasons to TOS1.00 up to TOS1.04). - Fixed interrupt polarity for TA_I and TB_I in the MFP core. - Minor improvements in the MFP timer section. - Several fixes concerning colour corrections in the Shifter's chroma shift registers. - Fixed CPU exception processing to improve system startup. - A couple of minor bug fixes. WF - 20090620. Version 2K8B: - CPU68K00 is fully working now. Thanks to T. Gubener for the intensive help during debugging. - There is now a fully working SD-RAM memory controller unit (MCU) replacing the legacy DRAM MCU. The SD-RAM MCU is capable to address the full portion of the 23 address lines respective 16MB. - There are some significant improvements over version 2K8A in the WD1772 compatible floppy - controller core. - The bootloader works now fine. - The IDE and ACSI hard disk access work now fine. - WF - 20081224. Version 2K8A: - Added a new MMU model to meet the requirements of the SDRAMs used on the 'Suska-Classic' hardware. - Fixed CPU core to run the operating system emutos and TOS 1.00. - Minor changes in a couple of modules. - Bugfixes in a couple of modules. - Added bootloader to the core. - Enhancements in the toplevel files to run different TOS versions. - The core's main frequency is now 16MHz. WF - 20080714. Version 2K7B: - Added a further top level file for the new Suska III series hardware. - Improved the flash boot loader unit. - Minor changes in the WD1772 compatible controller. - Bug fixes and changes in the 68K00 ip core. For more information see the readme files in the 68K00 vhdl directory (rtl). - Minor fixes and changes in several modules to meet the requirements for the new hardware. WF - 20071224. Version 2K7A: - Withdrawn the RTC interface for the I2C real time chip DS1337 (Maxim / Dallas). Introduced the DS139x real time chip bridge wich features the simple SPI interface of the DS1392 or the DS1393. - Added an interface for an audio DAC (AD5302). - Added a ACSI to SCSI interface. See the respective top level file for more information. - Added an IDE interface. See the respective top level file for more information. - Added an interface to connect SD cards via the ACSI bus. This component is based on Miroslav Nohaj's - "Jookie's" project named Satan Disk. - Added a boot loader mechanism for the operating system flash device. See the component WF_FLASHBOOT for more information. - Provided a keyboard switch to select either the original keyboard and mouse or the Eiffel system. - Several fixes improvments in several files. - The CPU is now (hopefully) working. - Code modified to fit 100% to the Suska-III hardware. - Added a module to control the serial DAC used in the SUSKA-III hardware. - For more information concerning the CPU 68K00 see the respective readme file in the rtl directory of the 68K00 core. WF - 20070601. Version 2K6B: - Modified the source files to compile with the XILINX web edition software (ISE8.2i). - Introduced the 68000 IP core in an alpha version. - Introduced the RP5C15 interface replacement for the DS1337 which is I2C also alpha state. - Added top level files for the use in a system on a programmable chip. These files all have the same extension ..._top_soc.vhd. There are now to possibilities: fistly use the top level entities ..._top.vhd for stand alone chip versions. secondly use the ..._top_soc.vhd. for an integrated system on one chip. - Added a top level file for the ST(E) compatible machine. This file is located in the WF_SUSKA directory. - Some minor bug fixes in several files. See the file histories for more information. WF - 20061224. Version 2K6A: Initial release of a set of models for the most 1040ST chips as follows: - BLITTER: Complete implementation of the famous ATARI bit block transfer processor. - SHIFTER: Video shifter with all enhancements of the STE machines (microwire interface, 4 bit per colour DA resolution, fine scrolling feature). Aditionally STBook or STACY SHADOW registers for the power management. - GLUE: 1040 GLUE logic with enhancements concerning TOS ROM configuration, real time clock decoding, interrupt logic and some minor STE machine logic. - MCU: Memory controller as in the ST or STE machines. - DMA: Direct memory access controller compatible with the ST DMA controller. - WD1772: Floppy drive controller core with enhancements concerning HD floppies. Built in digital phase locked loop (PLL) for optimal data recovery. Besides these enhance- ments, the core is highly compatible with the WD1772 of the Western Digital Cor- poration. - YM2149: Sound controller IP core with a digital DA converter approach with pulse width modulation logic. The core is compatible with Yamaha's YM2149 chip. - UART: The serial interface core behaves like the 6850 ACIA. - MFP: A solution for a multi function port identically to the MC68901 from Motorola. - SHADOW: Atari had the STACY and the STBook, which were notebooks driving a LCD panel with a screen resolution of 640x400. Since these custom LCD panels are obsolete, the new SHADOW IP (intelectual property) core drives a standard VGA display with 640x480 dots in monochrome mode. WF - 20060609. ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- 20140623 Enjoy Wolfgang Foerster