This is version 2K15B of the Suska IP core. ------------------------------------------ ------------------------------------------ Content: 1. Introduction 2. Distribution 3. Compiler notes 4. Whant's new / work in progress 5. What's ahead 6. Configware versions 7. Progress 8. Known issues 9. Revision history -------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------- 1. Introduction: Suska is a collection of configware modules for the implementation of digital logic in FPGAs or CPLDs, which features the functionality of Atari Falcon-, ST-, STE-, Stacy-, STBook- and TT- computers. There is also Firmware for the microcontrollers on the different Suska hardware. And Suska includes Software Tools for Developers. The configware includes many custom chips like GLUE, MMU (MCU), SHIFTER, DMA, BLITTER, Stacy- and STBook-Shadow, and also cores for the LSI chips originally used in these machines like the 68000 CPU (68K00), the multi function port MFP, the WD1772 floppy controller and the Yamaha sound chip YM2149. There are several add ons like SD card interface, IDE interface, real time clock, sound with a CODEC, SCSI/ ACSI bridge and a Bootloader prepared for the Suska-III-C and SUska-III-B hardware for loading the operating system into the flash memory. There are also some hardware exten- sions on the Suska-III-C like USB and Ethernet. With the 2K14B version there are Atari Falcon custom chips COMBEL, VIDEL and Falcon-DMA available. See below for more information. With the 2K15A version there are cores for the MC68030 in a light version and for the MC68010 and the MC68012. For a detailed description refer to the top level files headers of the respective processor. The 68K10 features the full bus width of the MC68012 and it has a downward compatibility mode for the MC68000. It can be clocked about five times higher than the 68K00. The 68K30L is instruction compatible to the MC68030 but has noc MMU, Caches and coprocessor interface. 2. Distribution: With release 2K13B the file structure of the distribution has changed in the following manner: - For the Suska-III-C machine all required source code is available to build this machine. - For the Suska-III-B machine all required source code except the SD drives module is available to build this machine. Use an empty wrapper for the SD drives module where required. - We provide support for the Suska-III-C hardware and for the Suska-III-B platform in the backend/Altera section. - We do not provide implementation support for other hardware platforms like Lattice, Microsemi (formerly Actel) or Xilinx. - There is some top level file support for the Xilinx platform in the rtl/vhdl/suska-c directory. 3. Compiler notes: The core is compiled (and tested) with following integrated development environments: Altera: All Quartus II versions up to V13.1. Be aware, that the Suska hardware is equipped with different FPGAs. Altera has dropped support for older FPGAs in newer versions of Quartus. Refer to the respective documentation on Altera's website. Xilinx: Although this release is prepared for Xilinx we dropped since version 2K10A testing the system on Xilinx development tools or Xilinx hardware. Feel free to contribute. Lattice / Microsemi / others: Testers are welcome. 4. Whats's new / work in progress: First of all there has been done some effort to switch the complete core to the data type std_logic. All modules are affected and the data type bit is exchanged by std_logic. The reason for this is to improve the IP core concerning interchangeability with other cores. Furthermore the new processors 68K10, 68K12, 68K30L, 68K30, 68K30F and perhaps the 68K40 will be built on the data type std_logic. This core also focuses on the Suska-III-B IP core. In this release you find the sources except for the functionality featuring the SD card as a hard drive. Suska-III-B is now finished in a way, that the board boots from a appropriate SD card (for example with installed HDDRIVER). There is a configuration image for Suska-III-B featuring the STE core inclusive the SD card support. There have be done several small fixes and changes in the Suska-III-C ip core. Refer to the top level header for more information. The intended Atari Falcon compatible core featuring all chips like the Combel, the Videl and the Falcon-DMA are partially tested. There is are betweern two prototypes of the required Falcon capable hardware. These are the Suska-III-T2 boards. 5. What's ahead: STE compatible IP core (Suska-III-C): For the STE compatible ip core there are a few things left for further development concerning the SUSKA-III-C boards and for Suska-III-B. We have dropped some software related items listed here in the previous release notes. This is because we decided to focus on the hardware development and let the community work on the software stuff. So there are plans to enhance the Suska-III-C as follows: - Preparation for more modern TFT displays. - Getting USB Mouse and keyboard to work. - Provide some high quality case for the Suska-III-C bard. Falcon compatible IP core (Suska-III-T2) is in intense development. Information from the last release: ... There are two of those ip cores... One is a fully featured complex instruction set computer (CISC) CPU with 68030 instruction set, addressing modes, memory management unit, instruction and data cache and the coprocessor interface. It is developed in a pipelined architecture. The shifter unit is designed as a barrel shifter with one clock cycle delay. This is the 68K30 version. I will not release this CPU in the near future. Interested people can contact me concerning this IP core. The other version is a subset of the 68K30 called 68K30L. This ip core features all addressing modes and instructions but does not have MMU, cache and coprocessor interface. The shifter unit is modeled as a convetional shift register with several clock cycles delay. The 68K30F IP core which will implement the 68882 floating point unit seamlessly to the 68K30. This work is in progress. The 68K40 IP core featuring a MC68040 compatible machine. 6. Configware Versions: Since the 2K9A release of the Suska IP-Core we will provide tested configuration files in the config-files directory. We store improved versions in chronological order So the latest files will result in the most improved hardware. 7. Progress: Suska-III-B: Information currently not available. Suska-III-C: The core is tested successfully on the Suska-III-C prototype, series-0 and series-1 boards. The results are as follows: Operating systems: TOS1.00 : works with Slowdown-CPU feature (configuration switch 1 on). Reason: requires 8MHz system. TOS1.02 : fails. Reason: requires 8MHz system. TOS1.04 : works with Slowdown-CPU feature (configuration switch 1 on). Reason: requires 8MHz system. TOS1.62 : works. TOS2.05 : works. TOS2.06 : works. emuTos : works. Applications: We have tested several applications and there are a lot of reports of tests done by the community. The detailed results of such tests are beyond the scope of this document. Generally spoken, a lot of applications work fine. The most critical applications seems to be several games. We would appreciate, if someone could set up a data bench reflecting the test results. We will provide the information concerning this issue at www.experiment-s.de Suska-III-T2: Information currently not available. 8. Known issues Suska-III-B: Information currently not available. Suska-III-C: 1. The IDE interface features Master/Slave operation. There was no way to operate a SD-Card configured as master and a 2.5" IDE hard drive configured as slave up to now. This seems not to be caused by the core. 2. Using HDDRIVER's AUTOPARK accessory version 8.23 causes the TOS2.06 system hang when selecting the Desktop info menu. Workaround: rename or delete the accessory. 3. Loading Sound.cpx causes a system hang. Suska-III-T2: Information currently not available. 9. Revision history (all cores): With the release 2K15A of the Suska configware there is no listing of the revisions here. The reason for this change is the availability of the Suska-III-B IP core and the Suska-III-T2 IP core beside Suska-III-C. Every development trajectory has it's own revision history which can be found in the headers of the top level files. ----------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------- 20151224 Enjoy Wolfgang Foerster