Atari ST series compatible IP core release notes:
This archieve contains the stuff for building a complete Atari ST, STE or Mega STE compatible IP core. Currently the core is in a beta state. The core is developed as near as possible to the original hardware. The name convention of the VHDL stuff
is self explaining (similar to the original chips). Where it made sense, the core is improved over the original hardware. One example is the floppy controller which is done without gated clocks and for use of DD or HD floppy disks in FM or MFM mode.

This is version 2K6B of the IP core. 
It is compiled (and tested) with following integrated development environments:
- Quartus II version 6.0 SP1.
- Xilinx ISE8.2i (Currently i have no hardware for Xilinx tests available).


Currently untested or not well tested features:

MFP:
- The USART is not tested yet. The asynchronous mode is verified in a simulation.
- The synchronous USART mode is completely untested.
- Break character logic not tested.
- Asynchronous non div by 16 clock mode is not tested.

WF - 20061224.