Revision 2K9B - RESET_INn is now SYS_RESET_INn in the MCU top level file. - RESET_OUTn is now SYS_RESET_OUTn in the MCU top level file. - Replaced RESETn filter by new RESET_INn in the MCU top level file. - Renamed the comp sync signal SH_COLOR to SH_CSYNCn. - Removed DMAn in the module WF_IDE. - Changed the MDAT_BUFFER clock from 64MHz to 32MHz due to better stability. - Fixed 68000 bus interface: UDSn and LDSn logic not working correct with waitstates in some cases. - Changed UNLK A7 logic due to compatibility reasons with MC68000 in the module wf68k00ip_control. - Fixed a timing bug in the 68K00 bus arbitration state register. - Small improvement the process TIME_SLICES in module wf25912ip_ctrl. - Linewidth correction in wf25912ip_video_counter_sd. - Bugfix in the BANK_SWITCH concerning 14MB of memory in the MCU control file. - Numerous changes in wf25913ip_ctrl due to new wf25915ip_bus_arbiter_v2. These changes result - wf25915ip_bus_arbiter_v2. - Changed timing of SECT_CNT_ZEROn in module wf25913_registers. - Fixed a bug in the sector counter in module wf25913_registers. - Fixed bus access timing in module wf25913_registers. - Introduced CTRL_SRC_SEL in the wf25913 registers and top level. - Replaced port DMA_SRC_SEL by DRIVE_SEL in the wf25913 top level to meet better ACSI bus timing. - New modeling of FIFO_HI in the DMA FIFO control section to meet the requirements for the new DMA controller. - Adjusted FIFO_LOW in the DMA FIFO control section due to new FIFO_HI. - Fixed DMA_EN logic and replaced DMA_RDn, DMA_WRn by DMA_EN in the DMA register section. - Removed the unneccesary DMA_LOCKn in the module wf25915ip_adrdec. - Changes in the related package and top level files to meet the new wf25915ip_bus_arbiter_V1. - IACKn is now also locked by ASn in the module wf25915ip_interrupts. - Fixed a FCSn bug in the GLUE's address decoding. - Fixed a DMA_MODE_CSn bug in the GLUE's address decoding. - Fixed a bug in the GLUE bus arbiter's BRn_LOGIC process not to start the DMA operation unintendedly. - Removed DMA_LOCKn in the module wf25915ip_interrupts. - Partially rewritten the wf25915ip_bus_arbiter_V1, removed DMA_SYNC again (not necessary any longer). - these changes results in version wf25915ip_bus_arbiter_v2. - Fixed the interrupt logic in the module wf6850ip_ctrl_status. - Introduced a minor RTSn correction in the module wf6850ip_ctrl_status. - Fixed the timing for DR_LOAD in the 1772 control section. WF - 20091224. Revision 2K9A - Enhancements in the video system to drive modern TFTs or multisyncs. - The RESETn pin is not asserted by the RESET_BOOTn any more but by the FLASH_RESETn. This change was necessary because the FLASH's reset is on the series boards connected to the system reset. - New: PLL_ARESET logic for resetting the phase locked loops during system startup. - New: Clock synchronization in the MCU control file (process TIME_SLICES). This improves system startup. - New: Clock synchronization in the WF25914IP_CR_SHIFT_REG. This improves system startup. - Changed LATCHn behaviour in the MCU control file (No unnecessary bus switching). - New: process SLOW_CPU for lowering the CPU speed (compatibility reasons to TOS1.00 up to TOS1.04). - Fixed interrupt polarity for TA_I and TB_I in the MFP core. - Minor improvements in the MFP timer section. - Several fixes concerning colour corrections in the Shifter's chroma shift registers. - Fixed CPU exception processing to improve system startup. - A couple of minor bug fixes. - WF - 20090620. Version 2K8B: - CPU68K00 is fully working now. Thanks to T. Gubener for the intensive help during debugging. - There is now a fully working SD-RAM memory controller unit (MCU) replacing the legacy DRAM MCU. The SD-RAM MCU is capable to address the full portion of the 23 address lines respective 16MB. - There are some significant improvements over version 2K8A in the WD1772 compatible floppy - controller core. - The bootloader works now fine. - The IDE and ACSI hard disk access work now fine. - WF - 20081224. Version 2K8A: - Added a new MMU model to meet the requirements of the SDRAMs used on the 'Suska-Classic' hardware. - Fixed CPU core to run the operating system emutos and TOS 1.00. - Minor changes in a couple of modules. - Bugfixes in a couple of modules. - Added bootloader to the core. - Enhancements in the toplevel files to run different TOS versions. - The core's main frequency is now 16MHz. WF - 20080714. Version 2K7B: - Added a further top level file for the new Suska III series hardware. - Improved the flash boot loader unit. - Minor changes in the WD1772 compatible controller. - Bug fixes and changes in the 68K00 ip core. For more information see the readme files in the 68K00 vhdl directory (rtl). - Minor fixes and changes in several modules to meet the requirements for the new hardware. WF - 20071224. Version 2K7A: - Withdrawn the RTC interface for the I2C real time chip DS1337 (Maxim / Dallas). Introduced the DS139x real time chip bridge wich features the simple SPI interface of the DS1392 or the DS1393. - Added an interface for an audio DAC (AD5302). - Added a ACSI to SCSI interface. See the respective top level file for more information. - Added an IDE interface. See the respective top level file for more information. - Added an interface to connect SD cards via the ACSI bus. This component is based on Miroslav Nohaj's - "Jookie's" project named Satan Disk. - Added a boot loader mechanism for the operating system flash device. See the component WF_FLASHBOOT for more information. - Provided a keyboard switch to select either the original keyboard and mouse or the Eiffel system. - Several fixes improvments in several files. - The CPU is now (hopefully) working. - Code modified to fit 100% to the Suska-III hardware. - Added a module to control the serial DAC used in the SUSKA-III hardware. - For more information concerning the CPU 68K00 see the respective readme file in the rtl directory of the 68K00 core. WF - 20070601. Version 2K6B: - Modified the source files to compile with the XILINX web edition software (ISE8.2i). - Introduced the 68000 IP core in an alpha version. - Introduced the RP5C15 interface replacement for the DS1337 which is I2C also alpha state. - Added top level files for the use in a system on a programmable chip. These files all have the same extension ..._top_soc.vhd. There are now to possibilities: fistly use the top level entities ..._top.vhd for stand alone chip versions. secondly use the ..._top_soc.vhd. for an integrated system on one chip. - Added a top level file for the ST(E) compatible machine. This file is located in the WF_SUSKA directory. - Some minor bug fixes in several files. See the file histories for more information. WF - 20061224. Version 2K6A: Initial release of a set of models for the most 1040ST chips as follows: - BLITTER: Complete implementation of the famous ATARI bit block transfer processor. - SHIFTER: Video shifter with all enhancements of the STE machines (microwire interface, 4 bit per colour DA resolution, fine scrolling feature). Aditionally STBook or STACY SHADOW registers for the power management. - GLUE: 1040 GLUE logic with enhancements concerning TOS ROM configuration, real time clock decoding, interrupt logic and some minor STE machine logic. - MCU: Memory controller as in the ST or STE machines. - DMA: Direct memory access controller compatible with the ST DMA controller. - WD1772: Floppy drive controller core with enhancements concerning HD floppies. Built in digital phase locked loop (PLL) for optimal data recovery. Besides these enhance- ments, the core is highly compatible with the WD1772 of the Western Digital Cor- poration. - YM2149: Sound controller IP core with a digital DA converter approach with pulse width modulation logic. The core is compatible with Yamaha's YM2149 chip. - UART: The serial interface core behaves like the 6850 ACIA. - MFP: A solution for a multi function port identically to the MC68901 from Motorola. - SHADOW: Atari had the STACY and the STBook, which were notebooks driving a LCD panel with a screen resolution of 640x400. Since these custom LCD panels are obsolete, the new SHADOW IP (intelectual property) core drives a standard VGA display with 640x480 dots in monochrome mode. WF - 20060609.