Atari ST series compatible IP core release notes: This archieve contains the stuff for building a complete Atari ST, STE or Mega STE compatible IP core. Currently the core is in a beta state. The core is developed as near as possible to the original hardware. The name convention of the VHDL stuff is self explaining (similar to the original chips). Where it made sense, the core is improved over the original hardware. One example is the floppy controller which is done without gated clocks and for use of DD or HD floppy disks in FM or MFM mode. This is version 2K7A of the IP core. It is compiled (and tested) with following integrated development environments: - Quartus II version 6.0 SP1. - Xilinx ISE8.2i (Currently i have no hardware for Xilinx tests available). This version 2K7A will bring above all other things a running 68000, a running real time clock interface and a cleaned up code with bugfixes. So the version 2K7A is called the bugfix version. It is intended as a proof of concept how to realize the complete system in one chip. Other topics could be the following: Implemented ST, STE features: - CPU 68K00 , done in version 2K6B - Blitter , done in version 2K6A - GLUE , done in version 2K6A - MCU , done in version 2K6A - SHIFTER , done in version 2K6A - SHADOW , done in version 2K6A - DMA , done in version 2K6A - FDC , done in version 2K6A Atari STE enhancements against the ST, all done in version 2K6A. W. Foerster 20050202 -------------------------------------------------------------------------- Topic Implemented Where Tested Joyport 0 yes GLUE - Joyport 1 yes GLUE - Buttons yes GLUE - Lightpen yes GLUE - Paddle 0 yes GLUE - Paddle 1 yes GLUE - Paddle 2 yes GLUE - Paddle 3 yes GLUE - DMA sound yes GLUE; SHIFTER - Microwire interface yes SHIFTER - Vertical finescrolling yes MMU - Horizontal finescrolling yes SHIFTER; MMU, 1) - Palette register yes SHIFTER - Real time clock (RTC) yes GLUE - Remarks: -------------------------------------------------------------------------- 1) : Implemnted the Hscroll register in the SHIFTER and the LINEWIDTH register in the MCU. Implemented Core features additionally to the given above: - Real time clock interface to a modern SPI device. - Boot loader: The Suska core is equipped with a boot loader mechanism since version 2K7A. It provides the programming of a flash device via an SPI interface controlled by request / acknowldege. For more information see the respective component WF_FLASHBOOT. - Keyboard switch for the Eiffel keyboard and mouse. - SD card interface. - ACSI to SCSI bridge providing parity and initiator identification. - AUDIO_DAC: module to control the serial DAC used in the SUSKA-III hardware. Implementations planned: - Audio codec module to operate the Suska-III audio codec. - TCP/IP interface via SPI connection to a TCP/IP microcontroller. - USB20 interface via SPI connection to a USB20 microcontroller. - Floating point co processor unit compatible with the 68882. Implementation not provided by this core: - Digital Signal processor (56001) because this core is 16 bit and the DSP requires 32 bit. - Special purpose chips: The following chips of the TT will not be provided by this core until they will be provided:) - Funnel, TT video, TTSCU, DCU, DMAC, 8516. - SCSI: - The Implementation of a DP5380 compatible IP core is withdrawn. The reason is the more and more upcoming legacy of this interface. Instead of this, an SD-Card via the ACSI interface will be provided. Additionally a ACSI to SCSI bridge allows the operation of SCSI devices on the ACSI interface. - Cache Logic: - The implementation of the cache logic of the MEGA STE is also withdrawn because the efficiency of this feature was very poor and the compatibility to older machines was not given in any case. Additionally the old Cache Tag RAMs (e.g. P4C174) are not available any more and the new SD-RAMs intended for use are as fast as old Cache RAMs. And last but not least: Todays FPGAs do not provide as much internal RAM as needed for an efficient cache. There will be attempts later to introduce a level I cache in the processor core. - RTCs: - All the different real time clocks of the machines (RP5C15 for the ST series, 148818 for the TT, C1287 for the Falcon) will be replaced by an actual DS1392 or DS1393 chip wich is connected via SPI interface. The chip is RP5C15 register compatible (as far as possible) provided by the RTC core. For more details see the respective top level file. - SCCs: - The serial communication controllers SCC (85C30) are not provided by the core until the will be a severe need of it. Planned Improvements: - SHADOW: Resynchronisation of the FIFO with the Video base address. This improves stability concerning lateral shift errors on the LCD panel. - BLITTER:Enlarge the sorce address register and the destination address register to 32bit. This makes the BLITTER compatible with the Falcon BLITTER C302183 / MM9200C0C. - Processor: - Upgrading the current 68K00 to a 68030 compatible 68K30 CPU. - Upgrading even to a 68K40. - MCU: Extend the memory address lines to 11 bit. This allows the addressing of 16MB. Currently untested or not well tested features: - MFP: - The USART is not tested yet. The asynchronous mode is verified in a simulation. - The synchronous USART mode is completely untested. - Break character logic not tested. - Asynchronous non div by 16 clock mode is not tested. The next release 2K7B will be a bugfix release and the proof of concept for the upcoming SUSKA-III hardware platform. WF - 20070121.