TimeQuest Timing Analyzer report for SUSKA-III-B
Wed Dec 15 10:42:25 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 14. Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 15. Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 16. Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
 17. Slow 1200mV 85C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
 18. Slow 1200mV 85C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
 19. Slow 1200mV 85C Model Setup: 'CLK_PLL1'
 20. Slow 1200mV 85C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
 21. Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 22. Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 23. Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 24. Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
 25. Slow 1200mV 85C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
 26. Slow 1200mV 85C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
 27. Slow 1200mV 85C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
 28. Slow 1200mV 85C Model Hold: 'CLK_PLL1'
 29. Slow 1200mV 85C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 30. Slow 1200mV 85C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 31. Slow 1200mV 85C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 32. Slow 1200mV 85C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 33. Slow 1200mV 85C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 34. Slow 1200mV 85C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 40. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
 42. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_PLL1'
 43. Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_PLL2'
 44. Setup Times
 45. Hold Times
 46. Clock to Output Times
 47. Minimum Clock to Output Times
 48. Propagation Delay
 49. Minimum Propagation Delay
 50. Output Enable Times
 51. Minimum Output Enable Times
 52. Output Disable Times
 53. Minimum Output Disable Times
 54. Slow 1200mV 85C Model Metastability Report
 55. Slow 1200mV 0C Model Fmax Summary
 56. Slow 1200mV 0C Model Setup Summary
 57. Slow 1200mV 0C Model Hold Summary
 58. Slow 1200mV 0C Model Recovery Summary
 59. Slow 1200mV 0C Model Removal Summary
 60. Slow 1200mV 0C Model Minimum Pulse Width Summary
 61. Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 62. Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 63. Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
 64. Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 65. Slow 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
 66. Slow 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
 67. Slow 1200mV 0C Model Setup: 'CLK_PLL1'
 68. Slow 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
 69. Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 70. Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 71. Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
 72. Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 73. Slow 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
 74. Slow 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
 75. Slow 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
 76. Slow 1200mV 0C Model Hold: 'CLK_PLL1'
 77. Slow 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 78. Slow 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 79. Slow 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 80. Slow 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 81. Slow 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 82. Slow 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
 86. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
 87. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
 88. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
 89. Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
 90. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL1'
 91. Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL2'
 92. Setup Times
 93. Hold Times
 94. Clock to Output Times
 95. Minimum Clock to Output Times
 96. Propagation Delay
 97. Minimum Propagation Delay
 98. Output Enable Times
 99. Minimum Output Enable Times
100. Output Disable Times
101. Minimum Output Disable Times
102. Slow 1200mV 0C Model Metastability Report
103. Fast 1200mV 0C Model Setup Summary
104. Fast 1200mV 0C Model Hold Summary
105. Fast 1200mV 0C Model Recovery Summary
106. Fast 1200mV 0C Model Removal Summary
107. Fast 1200mV 0C Model Minimum Pulse Width Summary
108. Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
109. Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
110. Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
111. Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
112. Fast 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
113. Fast 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
114. Fast 1200mV 0C Model Setup: 'CLK_PLL1'
115. Fast 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
116. Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
117. Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
118. Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
119. Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
120. Fast 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
121. Fast 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
122. Fast 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
123. Fast 1200mV 0C Model Hold: 'CLK_PLL1'
124. Fast 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
125. Fast 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
126. Fast 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
127. Fast 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
128. Fast 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
129. Fast 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
130. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'
131. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'
132. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'
133. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'
134. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL1'
135. Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL2'
136. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'
137. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'
138. Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'
139. Setup Times
140. Hold Times
141. Clock to Output Times
142. Minimum Clock to Output Times
143. Propagation Delay
144. Minimum Propagation Delay
145. Output Enable Times
146. Minimum Output Enable Times
147. Output Disable Times
148. Minimum Output Disable Times
149. Fast 1200mV 0C Model Metastability Report
150. Multicorner Timing Analysis Summary
151. Setup Times
152. Hold Times
153. Clock to Output Times
154. Minimum Clock to Output Times
155. Propagation Delay
156. Minimum Propagation Delay
157. Board Trace Model Assignments
158. Input Transition Times
159. Slow Corner Signal Integrity Metrics
160. Fast Corner Signal Integrity Metrics
161. Setup Transfers
162. Hold Transfers
163. Recovery Transfers
164. Removal Transfers
165. Report TCCS
166. Report RSKM
167. Unconstrained Paths
168. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                       ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name      ; SUSKA-III-B                                        ;
; Device Family      ; Cyclone III                                        ;
; Device Name        ; EP3C25Q240C8                                       ;
; Timing Models      ; Final                                              ;
; Delay Model        ; Combined                                           ;
; Rise/Fall Delays   ; Enabled                                            ;
+--------------------+----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.35        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  15.0%      ;
;     Processors 3-4         ;  10.0%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+-----------------------------------------------------------------------------------------------+
; SDC File List                                                                                 ;
+-----------------------------------------------------------+--------+--------------------------+
; SDC File Path                                             ; Status ; Read at                  ;
+-----------------------------------------------------------+--------+--------------------------+
; ../../../rtl/vhdl/SUSKA-III-B/suska_cycloneIII_core_b.sdc ; OK     ; Wed Dec 15 10:42:06 2021 ;
+-----------------------------------------------------------+--------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------------------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-----------------------------------------------------------+-------------------------------------------------------------+
; Clock Name                                                                                             ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                    ; Targets                                                     ;
+--------------------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-----------------------------------------------------------+-------------------------------------------------------------+
; CLK_PLL1                                                                                               ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                           ; { CLK_PLL1 }                                                ;
; CLK_PLL2                                                                                               ; Base      ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                           ; { CLK_PLL2 }                                                ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL1 ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0] } ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Generated ; 31.250 ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CLK_PLL1 ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1] } ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL1 ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2] } ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Generated ; 41.666 ; 24.0 MHz  ; 0.000 ; 20.833 ; 50.00      ; 2         ; 3           ;       ;        ;           ;            ; false    ; CLK_PLL1 ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3] } ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Generated ; 39.062 ; 25.6 MHz  ; 0.000 ; 19.531 ; 50.00      ; 5         ; 8           ;       ;        ;           ;            ; false    ; CLK_PLL2 ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0] } ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Generated ; 25.390 ; 39.39 MHz ; 0.000 ; 12.695 ; 50.00      ; 13        ; 32          ;       ;        ;           ;            ; false    ; CLK_PLL2 ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1] } ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Generated ; 62.500 ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL2 ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0] ; { I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2] } ;
+--------------------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-----------------------------------------------------------+-------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                                                     ;
+-------------+-----------------+--------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name                                                                                             ; Note                                                          ;
+-------------+-----------------+--------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+
; 15.73 MHz   ; 15.73 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;                                                               ;
; 22.06 MHz   ; 22.06 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;                                                               ;
; 44.24 MHz   ; 44.24 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;                                                               ;
; 69.66 MHz   ; 69.66 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;                                                               ;
; 377.64 MHz  ; 250.0 MHz       ; CLK_PLL1                                                                                               ; limit due to minimum period restriction (max I/O toggle rate) ;
; 380.66 MHz  ; 380.66 MHz      ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ;                                                               ;
; 452.08 MHz  ; 402.09 MHz      ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; limit due to minimum period restriction (tmin)                ;
; 1027.75 MHz ; 402.09 MHz      ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; limit due to minimum period restriction (tmin)                ;
+-------------+-----------------+--------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                                             ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; -4.791 ; -9.171        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -0.538 ; -2.526        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.245  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.593  ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 22.763 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 38.089 ; 0.000         ;
; CLK_PLL1                                                                                               ; 59.852 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 60.288 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                                             ;
+--------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                  ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+-------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.079 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.433 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.434 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.434 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.435 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.455 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.467 ; 0.000         ;
; CLK_PLL1                                                                                               ; 0.485 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                                          ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 21.548 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 21.593 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 27.749 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                                           ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1.701  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 4.065  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 33.361 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                                               ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 12.384 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.295 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 19.218 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 20.498 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 30.806 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 30.920 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 30.932 ; 0.000         ;
; CLK_PLL1                                                                                               ; 31.009 ; 0.000         ;
; CLK_PLL2                                                                                               ; 31.107 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                        ;
+--------+--------------------------------------------------------------------------------+---------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                      ; To Node                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------+---------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -4.791 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 20.572     ;
; -4.587 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 20.368     ;
; -4.560 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 20.342     ;
; -4.457 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 20.239     ;
; -4.446 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 20.227     ;
; -4.380 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 20.161     ;
; -4.298 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 20.079     ;
; -4.267 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 20.049     ;
; -4.176 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.957     ;
; -4.149 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.931     ;
; -4.145 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.926     ;
; -4.111 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.893     ;
; -4.046 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.828     ;
; -4.035 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.816     ;
; -3.933 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.714     ;
; -3.887 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.668     ;
; -3.856 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.638     ;
; -3.848 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.629     ;
; -3.806 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.588     ;
; -3.734 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.515     ;
; -3.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.500     ;
; -3.700 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.482     ;
; -3.648 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.429     ;
; -3.572 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 19.341     ;
; -3.568 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[16]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.350     ;
; -3.522 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.303     ;
; -3.482 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[21]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 19.251     ;
; -3.437 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.218     ;
; -3.430 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[18]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 19.201     ;
; -3.419 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[19]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 19.188     ;
; -3.395 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.177     ;
; -3.358 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[11] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.693     ;
; -3.308 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[13] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.643     ;
; -3.307 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 19.089     ;
; -3.260 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[12] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.595     ;
; -3.249 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[20]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 19.020     ;
; -3.237 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.155      ; 19.018     ;
; -3.161 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.930     ;
; -3.157 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[16]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.156      ; 18.939     ;
; -3.129 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[10] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.464     ;
; -3.124 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[23]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.893     ;
; -3.071 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[21]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.840     ;
; -3.019 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[18]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.790     ;
; -3.008 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[19]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.777     ;
; -2.958 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[22]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.729     ;
; -2.947 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[11] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.282     ;
; -2.897 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[13] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.232     ;
; -2.886 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[24]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.655     ;
; -2.866 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[15] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.201     ;
; -2.849 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[12] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.184     ;
; -2.838 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[20]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.609     ;
; -2.831 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[8]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.166     ;
; -2.829 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[18] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 18.157     ;
; -2.779 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[14] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.114     ;
; -2.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[10] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.053     ;
; -2.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[7]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.053     ;
; -2.717 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[9]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 18.052     ;
; -2.713 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[23]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.482     ;
; -2.679 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[16] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 18.007     ;
; -2.649 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[17] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.977     ;
; -2.632 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.960     ;
; -2.612 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[6]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.947     ;
; -2.591 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[25] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.919     ;
; -2.578 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[26] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.906     ;
; -2.551 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.322     ;
; -2.547 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[22]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.318     ;
; -2.546 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.874     ;
; -2.541 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[3]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.876     ;
; -2.535 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[28]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.306     ;
; -2.525 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.296     ;
; -2.509 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[29]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.278     ;
; -2.497 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[4]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.832     ;
; -2.475 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[24]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.244     ;
; -2.455 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[15] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.790     ;
; -2.451 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[27]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 18.222     ;
; -2.443 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[5]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.778     ;
; -2.420 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[8]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.755     ;
; -2.418 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[18] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.746     ;
; -2.374 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[19] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 18.143     ;
; -2.368 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[14] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.703     ;
; -2.307 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[7]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.642     ;
; -2.306 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[9]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.641     ;
; -2.289 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[2]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.153      ; 18.068     ;
; -2.268 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[16] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.596     ;
; -2.238 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[17] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.566     ;
; -2.221 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.549     ;
; -2.201 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[6]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.536     ;
; -2.180 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[25] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.508     ;
; -2.167 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[26] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.495     ;
; -2.140 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 17.911     ;
; -2.135 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.463     ;
; -2.130 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[3]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.465     ;
; -2.124 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[28]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 17.895     ;
; -2.114 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 17.885     ;
; -2.113 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[24] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.298     ; 17.441     ;
; -2.098 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[29]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 17.867     ;
; -2.086 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[4]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.421     ;
; -2.040 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[27]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.145      ; 17.811     ;
; -2.032 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[5]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.291     ; 17.367     ;
; -1.992 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[22] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.143      ; 17.761     ;
+--------+--------------------------------------------------------------------------------+---------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                               ;
+--------+-----------------------------------------------------------------------------+-------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+-------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.538 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 31.644     ;
; -0.427 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.531     ;
; -0.334 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 31.440     ;
; -0.330 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 31.423     ;
; -0.307 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.411     ;
; -0.307 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 31.414     ;
; -0.282 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.255      ; 31.788     ;
; -0.265 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 31.787     ;
; -0.223 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.327     ;
; -0.216 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 31.309     ;
; -0.204 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 31.311     ;
; -0.196 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 31.301     ;
; -0.193 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 31.299     ;
; -0.126 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 31.219     ;
; -0.103 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.207     ;
; -0.099 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 31.193     ;
; -0.093 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 31.198     ;
; -0.088 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 31.196     ;
; -0.082 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.186     ;
; -0.078 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.255      ; 31.584     ;
; -0.076 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 31.181     ;
; -0.073 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.252      ; 31.576     ;
; -0.061 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 31.583     ;
; -0.051 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.256      ; 31.558     ;
; -0.045 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 31.151     ;
; -0.034 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.272      ; 31.557     ;
; -0.014 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 31.121     ;
; -0.012 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 31.105     ;
; 0.004  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 31.090     ;
; 0.015  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 31.078     ;
; 0.022  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 31.072     ;
; 0.027  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 31.078     ;
; 0.032  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 31.061     ;
; 0.038  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.066     ;
; 0.049  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.252      ; 31.454     ;
; 0.052  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.256      ; 31.455     ;
; 0.063  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.255      ; 31.443     ;
; 0.066  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 31.038     ;
; 0.069  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.272      ; 31.454     ;
; 0.080  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.344      ; 31.515     ;
; 0.080  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 31.442     ;
; 0.097  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 31.008     ;
; 0.108  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 30.998     ;
; 0.116  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.328      ; 31.463     ;
; 0.116  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 30.992     ;
; 0.125  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 30.969     ;
; 0.129  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.964     ;
; 0.131  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.252      ; 31.372     ;
; 0.142  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 30.965     ;
; 0.145  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[8]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.344      ; 31.450     ;
; 0.150  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.142     ; 30.959     ;
; 0.158  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.253      ; 31.346     ;
; 0.163  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.930     ;
; 0.186  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 30.918     ;
; 0.194  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 30.900     ;
; 0.211  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.255      ; 31.295     ;
; 0.217  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 30.888     ;
; 0.219  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 30.885     ;
; 0.228  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 31.294     ;
; 0.236  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.857     ;
; 0.242  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.256      ; 31.265     ;
; 0.253  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 30.852     ;
; 0.253  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.252      ; 31.250     ;
; 0.253  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.142     ; 30.856     ;
; 0.257  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 30.851     ;
; 0.259  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.272      ; 31.264     ;
; 0.261  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.253      ; 31.243     ;
; 0.263  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 30.831     ;
; 0.272  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.252      ; 31.231     ;
; 0.277  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.816     ;
; 0.280  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.253      ; 31.224     ;
; 0.284  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.344      ; 31.311     ;
; 0.307  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.270      ; 31.214     ;
; 0.311  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.345      ; 31.285     ;
; 0.315  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 30.779     ;
; 0.316  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.777     ;
; 0.320  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 30.786     ;
; 0.320  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.328      ; 31.259     ;
; 0.335  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 30.769     ;
; 0.339  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.147     ; 30.765     ;
; 0.342  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.327      ; 31.236     ;
; 0.347  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.329      ; 31.233     ;
; 0.349  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[27] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 30.756     ;
; 0.349  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[8]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.344      ; 31.246     ;
; 0.350  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 30.744     ;
; 0.360  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.318      ; 31.209     ;
; 0.364  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.255      ; 31.142     ;
; 0.366  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.157     ; 30.728     ;
; 0.373  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.146     ; 30.732     ;
; 0.377  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.716     ;
; 0.381  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 31.141     ;
; 0.383  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[8]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.345      ; 31.213     ;
; 0.383  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.253      ; 31.121     ;
; 0.388  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[12] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.344      ; 31.207     ;
; 0.389  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.280      ; 31.142     ;
; 0.394  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.252      ; 31.109     ;
; 0.398  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.256      ; 31.109     ;
; 0.402  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[28] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.158     ; 30.691     ;
; 0.405  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.145     ; 30.701     ;
; 0.405  ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 30.703     ;
+--------+-----------------------------------------------------------------------------+-------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                             ;
+-------+-----------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                          ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.245 ; CLK_24576                                                                   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL1_S        ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1.970        ; -0.480     ; 1.106      ;
; 1.058 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 30.370     ;
; 1.165 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 30.245     ;
; 1.173 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 30.299     ;
; 1.173 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 30.299     ;
; 1.262 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 30.166     ;
; 1.277 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 30.111     ;
; 1.281 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 30.107     ;
; 1.296 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 30.133     ;
; 1.369 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 30.041     ;
; 1.377 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 30.095     ;
; 1.377 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 30.095     ;
; 1.396 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.160      ; 30.015     ;
; 1.399 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 30.030     ;
; 1.403 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 30.025     ;
; 1.404 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 30.069     ;
; 1.404 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 30.069     ;
; 1.481 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.907     ;
; 1.485 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.903     ;
; 1.499 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.160      ; 29.912     ;
; 1.507 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.966     ;
; 1.507 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.966     ;
; 1.510 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 29.900     ;
; 1.515 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.874     ;
; 1.518 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.954     ;
; 1.518 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.954     ;
; 1.519 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.870     ;
; 1.531 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.867     ;
; 1.531 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.867     ;
; 1.551 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 29.877     ;
; 1.589 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 29.840     ;
; 1.618 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.771     ;
; 1.622 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.766     ;
; 1.622 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.767     ;
; 1.626 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.762     ;
; 1.658 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 29.752     ;
; 1.666 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.806     ;
; 1.666 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.806     ;
; 1.689 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.160      ; 29.722     ;
; 1.697 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.776     ;
; 1.697 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.776     ;
; 1.704 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 29.724     ;
; 1.735 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.663     ;
; 1.735 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.663     ;
; 1.745 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 29.684     ;
; 1.762 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.148      ; 29.637     ;
; 1.762 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.148      ; 29.637     ;
; 1.770 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.618     ;
; 1.774 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.614     ;
; 1.800 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.189      ; 29.640     ;
; 1.803 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.189      ; 29.637     ;
; 1.808 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.581     ;
; 1.811 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 29.599     ;
; 1.812 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.577     ;
; 1.819 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.653     ;
; 1.819 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.653     ;
; 1.845 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.160      ; 29.566     ;
; 1.853 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.620     ;
; 1.853 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.620     ;
; 1.854 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.202      ; 29.599     ;
; 1.865 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.148      ; 29.534     ;
; 1.865 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.148      ; 29.534     ;
; 1.876 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.522     ;
; 1.876 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.522     ;
; 1.916 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 29.512     ;
; 1.923 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.465     ;
; 1.927 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.461     ;
; 1.948 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.525     ;
; 1.948 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.525     ;
; 1.964 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.425     ;
; 1.968 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 29.421     ;
; 2.001 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 29.427     ;
; 2.004 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.189      ; 29.436     ;
; 2.007 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.189      ; 29.433     ;
; 2.023 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 29.387     ;
; 2.024 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.374     ;
; 2.024 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.147      ; 29.374     ;
; 2.031 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.441     ;
; 2.031 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.441     ;
; 2.038 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.190      ; 29.403     ;
; 2.041 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.190      ; 29.400     ;
; 2.043 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 29.386     ;
; 2.055 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.148      ; 29.344     ;
; 2.055 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.148      ; 29.344     ;
; 2.058 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.202      ; 29.395     ;
; 2.085 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.203      ; 29.369     ;
; 2.108 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.159      ; 29.302     ;
; 2.116 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.356     ;
; 2.116 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.221      ; 29.356     ;
; 2.131 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 29.298     ;
; 2.135 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.253     ;
; 2.136 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.177      ; 29.292     ;
; 2.139 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.137      ; 29.249     ;
; 2.141 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.190      ; 29.300     ;
; 2.144 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.190      ; 29.297     ;
; 2.145 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.189      ; 29.295     ;
; 2.148 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.189      ; 29.292     ;
; 2.150 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.160      ; 29.261     ;
; 2.152 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.321     ;
; 2.152 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.222      ; 29.321     ;
+-------+-----------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                                                                                                                                                    ;
+-------+-------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                             ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.593 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 10.137     ;
; 0.643 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 10.087     ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.667 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.583      ;
; 0.693 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 10.037     ;
; 0.708 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 10.022     ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.763 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.487      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.767 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.483      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[21]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[19]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[18]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[20]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[23]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.836 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[22]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.414      ;
; 0.857 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.873      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.863 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.387      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.868 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.384      ;
; 0.869 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.381      ;
; 0.907 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.823      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.931 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.319      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[21]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[19]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[18]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[20]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[23]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.936 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[22]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.314      ;
; 0.957 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.773      ;
; 0.961 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.769      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.968 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.284      ;
; 0.969 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.281      ;
; 0.975 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.755      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[89]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[88]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[93]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[91]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[90]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[92]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[95]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 0.995 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[94]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.165     ; 9.257      ;
; 1.007 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.723      ;
; 1.011 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.719      ;
; 1.025 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.313      ; 9.705      ;
; 1.027 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.223      ;
; 1.027 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.223      ;
; 1.027 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.223      ;
; 1.027 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.223      ;
; 1.027 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.223      ;
; 1.027 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.167     ; 9.223      ;
+-------+-------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                             ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 22.763 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 2.549      ;
; 22.853 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 2.459      ;
; 22.862 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 2.450      ;
; 23.427 ; CLK_24576             ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 1.885      ;
; 23.484 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 1.828      ;
; 23.487 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 1.825      ;
; 24.042 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 1.270      ;
; 24.052 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 1.260      ;
; 24.067 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 1.245      ;
; 24.454 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.079     ; 0.858      ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                     ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 38.089 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.079     ; 0.895      ;
; 38.126 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.079     ; 0.858      ;
; 38.126 ; SCLK_6M4          ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.079     ; 0.858      ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLK_PLL1'                                                                                    ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 59.852 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.569      ;
; 59.852 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.569      ;
; 59.852 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.569      ;
; 59.852 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.569      ;
; 59.852 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.569      ;
; 59.860 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.561      ;
; 59.860 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.561      ;
; 59.860 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.561      ;
; 59.860 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.561      ;
; 59.860 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.561      ;
; 60.062 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.359      ;
; 60.062 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.359      ;
; 60.062 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.359      ;
; 60.062 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.359      ;
; 60.062 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.359      ;
; 60.196 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.225      ;
; 60.196 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.225      ;
; 60.196 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.225      ;
; 60.196 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.225      ;
; 60.196 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 2.225      ;
; 60.477 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.944      ;
; 60.477 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.944      ;
; 60.477 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.944      ;
; 60.477 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.944      ;
; 60.477 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.944      ;
; 60.752 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.669      ;
; 60.760 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.661      ;
; 60.962 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.459      ;
; 61.096 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.325      ;
; 61.377 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.080     ; 1.044      ;
; 61.528 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.079     ; 0.894      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                           ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 60.288 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.646      ;
; 60.321 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.613      ;
; 60.434 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.500      ;
; 60.526 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.408      ;
; 60.672 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.262      ;
; 60.673 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.261      ;
; 60.832 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 1.102      ;
; 61.024 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.567     ; 0.910      ;
; 61.079 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.099     ; 1.323      ;
; 61.130 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.079     ; 1.292      ;
; 61.138 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.099     ; 1.264      ;
; 61.299 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.099     ; 1.103      ;
; 61.544 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.099     ; 0.858      ;
; 61.544 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.099     ; 0.858      ;
; 61.544 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.099     ; 0.858      ;
; 61.564 ; CLK_0M5              ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.079     ; 0.858      ;
; 61.564 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.079     ; 0.858      ;
; 61.564 ; CLK_2M0              ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.079     ; 0.858      ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                                                                                         ;
+-------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                   ; To Node                                                                                                     ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.079 ; CLK_24576                                                                                                   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL1_S                                                   ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.020        ; 0.529      ; 1.000      ;
; 0.433 ; VMA_68K30Ln                                                                                                 ; VMA_68K30Ln                                                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.101      ; 0.746      ;
; 0.435 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.099      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I                                 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.SHIFT_R                                                              ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.SHIFT_R                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.LOAD_R                                                               ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.LOAD_R                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|FE                                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|FE                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|\IPL1n_CONTROL:SECOND                             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|\IPL1n_CONTROL:SECOND                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.TEST_PENDING                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.TEST_PENDING                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_SCLK                                              ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_SCLK                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[2]                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[2]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[1]                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[1]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                                  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.START                           ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.START                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_LOCK                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_LOCK                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP2                            ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP2                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP1                            ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP1                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[2]                                  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[2]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1]                                  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[0]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[0]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[8]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[8]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[9]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[9]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[11]                                     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[11]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[10]                                     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[10]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[7]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[7]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[4]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[4]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[6]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[6]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[5]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[5]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[1]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[1]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[2]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[2]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[3]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[3]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[4]                                           ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[0]                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[0]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[6]                                           ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[2]                                           ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[2]                                           ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                                           ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST                                 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\BUFFER_EMPTY:LOCK  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\BUFFER_EMPTY:LOCK  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|HSYNC_INTn                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|HSYNC_INTn                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\PARITY_TEST:P_ERR   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\PARITY_TEST:P_ERR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                        ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                             ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                  ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[6]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[6]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[5]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[5]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[4]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[4]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[3]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[3]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[1]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[1]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|FLOPPY_DPLL:DIGITAL_PLL|PLL_D                                      ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|FLOPPY_DPLL:DIGITAL_PLL|PLL_D                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[0]                                                ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[0]                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[1]                                                ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[1]                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[2]                                                ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[2]                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.NONE                                                         ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.NONE                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|RD_MBLOCK_I                                                        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|RD_MBLOCK_I                                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1]                                        ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2]                                        ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3]                                        ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0]                                        ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[10]                                ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[10]                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[1]  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:NEW_SDATA  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:NEW_SDATA  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:CLK_LOCK   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:CLK_LOCK   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.PARITY     ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.PARITY     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.WAIT_START ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.WAIT_START ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|PARITY_I            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|PARITY_I            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[7]        ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                                        ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[0]                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[0]                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[2]                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[2]                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[1]                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[1]                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[3]                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_DELAY:TMP[3]                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_TIMEOUT:TMP[26]                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_TIMEOUT:TMP[26]                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[11]                                   ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[11]                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[12]                                   ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[12]                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|HBLANKn                                             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|HBLANKn                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[7]                              ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[7]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_B_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_B_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_A_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_A_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_C_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_C_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[2]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[1]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[1]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\ENVELOPE:ENV_UP_DNn                        ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\ENVELOPE:ENV_UP_DNn                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_AUDIO_DAC:I_AUDIODAC|\TX_SHIFT:LOCK                                                                      ; WF_AUDIO_DAC:I_AUDIODAC|\TX_SHIFT:LOCK                                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[0]                                             ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[0]                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[15]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[15]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\TX_SHIFT:LOCK                                        ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\TX_SHIFT:LOCK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; SYNCn                                                                                                       ; SYNCn                                                                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ADJUST                                      ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ADJUST                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.080      ; 0.746      ;
+-------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                  ; To Node                                                                                    ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.433 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]                ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.101      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1]               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2]               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0]               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                           ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                  ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                             ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                                   ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|EW_RDY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|EW_RDY                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                   ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_BYTES[0]                                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_BYTES[0]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|\ADDRESS_MODES:BD_SIZE[0] ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|\ADDRESS_MODES:BD_SIZE[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_HILOn                                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_HILOn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TAS~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SBCD~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSL~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSL~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ASR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ASR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EXG~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.UNLK~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.Scc~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.Scc~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SWAP~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.SWAP~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPA~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.EOR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.AND_B~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.AND_B~reg0                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.OR_B~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.OR_B~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMP~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NBCD~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ADDQ~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ADDQ~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CMPM~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ABCD~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TRAPV~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TRAPV~reg0                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[9]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[9]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[11]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[11]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[26]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[26]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[10]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[10]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[18]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[18]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                            ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.SLEEP                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                         ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.BYTE~reg0                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[29]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[29]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[14]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[14]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[31]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[31]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[5]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[5]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[25]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[25]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[11]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[11]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[27]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[27]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[28]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[28]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[9]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[9]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[8]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[8]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[1]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[1]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[0]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[0]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.LONG~reg0                         ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OP_SIZE_WB.LONG~reg0                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[31]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[31]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[15]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[15]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[14]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[14]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[13]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[13]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[12]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[12]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[11]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[11]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[30]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[30]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[29]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[29]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[27]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[27]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[26]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[26]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[25]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[25]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[24]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[24]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[23]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[23]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[22]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[22]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[21]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[21]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[20]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[20]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[17]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[17]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[17]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[17]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[29]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[29]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[27]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[27]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[28]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[28]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[26]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[26]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[22]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[22]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[25]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[25]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[23]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[23]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[18]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[18]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[19]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[19]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[20]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[20]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[21]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[21]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[15]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[15]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[31]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[31]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[4]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[4]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[0]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[0]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[2]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[2]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[1]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[1]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[13]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[13]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[14]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[14]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[10]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[10]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[9]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[9]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[11]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[11]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[12]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[12]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[28]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[28]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[4]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[4]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.080      ; 0.746      ;
+-------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                                                                   ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.434 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                           ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.436 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.098      ; 0.746      ;
; 0.440 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                              ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.094      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IO                             ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IO                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_SBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_SBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_MBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_MBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\SPEED_DETECTION:LOCK                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\SPEED_DETECTION:LOCK                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RW_ERROR                                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RW_ERROR                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|MBLOCK                                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|MBLOCK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\COMMAND_DESCRIPTOR:LOCK                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\COMMAND_DESCRIPTOR:LOCK                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IDLE                           ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IDLE                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:LOCK                     ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:LOCK                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:FIRST_ACCESS             ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:FIRST_ACCESS             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:REJECTED                 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:REJECTED                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STAT_RDY                                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STAT_RDY                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[0]                                           ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[2]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[2]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[1]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[1]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[3]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[3]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[1]             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK           ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK           ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In               ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK           ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.456 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[1]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[2]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.078      ; 0.746      ;
; 0.466 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[0]             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.758      ;
; 0.468 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[0]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.078      ; 0.758      ;
; 0.487 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_RD                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.778      ;
; 0.493 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9]          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.784      ;
; 0.495 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.786      ;
; 0.501 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:ADR_PNTR[8]              ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:ADR_PNTR[8]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[23]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[12]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[5]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.793      ;
; 0.502 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[6]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.793      ;
; 0.502 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[52]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[45]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[2]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[29]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[16]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[17]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.795      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[4]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[3]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[41]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[38]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.796      ;
; 0.505 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[58]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.080      ; 0.797      ;
; 0.505 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[11]                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[10]                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[11]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.796      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                      ; To Node                                                                        ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.434 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.100      ; 0.746      ;
; 0.434 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.100      ; 0.746      ;
; 0.435 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.099      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_WR                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_WR                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[0]                                          ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[0]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[1]                                          ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_RD                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_RD                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[6]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[0]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[7]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|OP_RDY                              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|OP_RDY                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[1]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:TOKEN              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:TOKEN              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_MBLOCK                           ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_MBLOCK                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[2]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[0]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[1]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[3]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[19]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[19]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[7]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[6]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[5]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[3]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[1]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[2]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[8]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[8]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_RESPONSE_RDY                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_RESPONSE_RDY                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_DATA_RESPONSE      ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_DATA_RESPONSE      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_OUT                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_OUT                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR                     ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[12]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[12]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[11]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[11]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[10]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[10]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[7]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[5]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[4]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[3]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[2]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[2]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:BITCNT[0]              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:BITCNT[0]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_0                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_0                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.SWITCH_SPI                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.SWITCH_SPI                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.POR                        ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.POR                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CARD_RELEASE:LOCK                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CARD_RELEASE:LOCK                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_RELEASE            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_RELEASE            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[0]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.758      ;
; 0.467 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.758      ;
; 0.493 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:BITCNT[5] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:BITCNT[5] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.784      ;
; 0.520 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_CMD_RESPONSE       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.811      ;
; 0.521 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.812      ;
; 0.526 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.818      ;
; 0.535 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.826      ;
; 0.538 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.830      ;
; 0.546 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.837      ;
; 0.546 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.837      ;
; 0.546 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[4]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.837      ;
; 0.548 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.839      ;
; 0.548 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.079      ; 0.839      ;
; 0.550 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.842      ;
; 0.561 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.080      ; 0.853      ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                           ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.435 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.099      ; 0.746      ;
; 0.447 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.099      ; 0.758      ;
; 0.455 ; CLK_2M0              ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; CLK_0M5              ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.079      ; 0.746      ;
; 0.718 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.099      ; 1.029      ;
; 0.756 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.099      ; 1.067      ;
; 0.757 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.099      ; 1.068      ;
; 0.886 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.079      ; 1.177      ;
; 0.962 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 0.785      ;
; 1.205 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.028      ;
; 1.243 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.066      ;
; 1.243 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.066      ;
; 1.463 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.286      ;
; 1.517 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.340      ;
; 1.602 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.425      ;
; 1.629 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.389     ; 1.452      ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                     ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; SCLK_6M4          ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.488 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 0.779      ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                             ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.467 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 0.758      ;
; 0.741 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.032      ;
; 0.760 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.051      ;
; 0.761 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.052      ;
; 1.102 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.393      ;
; 1.104 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.395      ;
; 1.352 ; CLK_24576             ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.643      ;
; 1.693 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 1.984      ;
; 1.709 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 2.000      ;
; 1.711 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.079      ; 2.002      ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLK_PLL1'                                                                                    ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.485 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.079      ; 0.776      ;
; 0.638 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 0.930      ;
; 0.748 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.040      ;
; 0.748 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.040      ;
; 0.749 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.042      ;
; 0.771 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.063      ;
; 0.874 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.166      ;
; 1.014 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.306      ;
; 1.101 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.393      ;
; 1.109 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.401      ;
; 1.111 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.403      ;
; 1.118 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.410      ;
; 1.120 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.412      ;
; 1.231 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.523      ;
; 1.232 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.524      ;
; 1.233 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.525      ;
; 1.241 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.533      ;
; 1.249 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.541      ;
; 1.258 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.550      ;
; 1.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.941      ;
; 1.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.941      ;
; 1.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.941      ;
; 1.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 1.941      ;
; 1.885 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 2.177      ;
; 2.025 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 2.317      ;
; 2.025 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 2.317      ;
; 2.242 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 2.534      ;
; 2.242 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 2.534      ;
; 2.242 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.080      ; 2.534      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                 ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                            ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[38] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[41] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[42] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.548 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.215     ; 9.488      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[3]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[0]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[1]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[2]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[4]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[15]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[14]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[13]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[12]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[11]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[8]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[7]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[6]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[5]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[4]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[3]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_MASK[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[3][2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][0]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][2]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][12]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][9]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][10]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[2][2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][9]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][10]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][11]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.212     ; 9.485      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.214     ; 9.483      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[32] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[33] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[57] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[58] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[59] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[60] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[61] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[62] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[63] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.206     ; 9.491      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_STATUS              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|DATA_I[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[3]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[4]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[5]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[6]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.480      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[8]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[11]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[12]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[13]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[14]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.554 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_D[15]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.216     ; 9.481      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.479      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.479      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.479      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.479      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[7]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.218     ; 9.478      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[2]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.218     ; 9.478      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[4]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.218     ; 9.478      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[5]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.218     ; 9.478      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|SOUND_MODE_CTRL[6]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.218     ; 9.478      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.479      ;
; 21.555 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.217     ; 9.479      ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                             ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                            ; To Node                                                                                                   ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 21.593 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.179     ; 9.479      ;
; 21.594 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.176     ; 9.481      ;
; 21.594 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.176     ; 9.481      ;
; 21.594 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.176     ; 9.481      ;
; 21.610 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.477      ;
; 21.610 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 9.478      ;
; 21.610 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 9.478      ;
; 21.617 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.470      ;
; 21.617 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.470      ;
; 21.617 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.470      ;
; 21.619 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.480      ;
; 21.619 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.480      ;
; 21.619 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.480      ;
; 21.619 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.480      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.481      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.481      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.481      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.481      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.481      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.146     ; 9.476      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.146     ; 9.476      ;
; 21.629 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.146     ; 9.476      ;
; 21.635 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 9.486      ;
; 21.635 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 9.486      ;
; 21.635 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 9.486      ;
; 21.638 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.179     ; 9.434      ;
; 21.639 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.176     ; 9.436      ;
; 21.639 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.176     ; 9.436      ;
; 21.639 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.176     ; 9.436      ;
; 21.654 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.113     ; 9.484      ;
; 21.654 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.113     ; 9.484      ;
; 21.655 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.113     ; 9.483      ;
; 21.655 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.432      ;
; 21.655 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 9.433      ;
; 21.655 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 9.433      ;
; 21.662 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.425      ;
; 21.662 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.425      ;
; 21.662 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.164     ; 9.425      ;
; 21.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.435      ;
; 21.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.435      ;
; 21.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.435      ;
; 21.664 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.152     ; 9.435      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.436      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.436      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.436      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.436      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.141     ; 9.436      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.146     ; 9.431      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.146     ; 9.431      ;
; 21.674 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.146     ; 9.431      ;
; 21.680 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 9.441      ;
; 21.680 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 9.441      ;
; 21.680 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 9.441      ;
; 21.699 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.113     ; 9.439      ;
; 21.699 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.113     ; 9.439      ;
; 21.700 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.113     ; 9.438      ;
; 21.785 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.170     ; 9.296      ;
; 21.787 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.167     ; 9.297      ;
; 21.787 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.167     ; 9.297      ;
; 21.787 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.167     ; 9.297      ;
; 21.804 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.155     ; 9.292      ;
; 21.804 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.154     ; 9.293      ;
; 21.804 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.154     ; 9.293      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.143     ; 9.297      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.143     ; 9.297      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.155     ; 9.285      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.155     ; 9.285      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.155     ; 9.285      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.143     ; 9.297      ;
; 21.811 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.143     ; 9.297      ;
; 21.820 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.132     ; 9.299      ;
; 21.820 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.132     ; 9.299      ;
; 21.820 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.132     ; 9.299      ;
; 21.820 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.132     ; 9.299      ;
; 21.820 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.132     ; 9.299      ;
; 21.821 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 9.293      ;
; 21.821 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 9.293      ;
; 21.821 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 9.293      ;
; 21.827 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.121     ; 9.303      ;
; 21.827 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.121     ; 9.303      ;
; 21.827 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.121     ; 9.303      ;
; 21.847 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.104     ; 9.300      ;
; 21.847 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.104     ; 9.300      ;
; 21.847 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.104     ; 9.300      ;
; 21.992 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.214      ; 9.473      ;
; 21.992 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.214      ; 9.473      ;
; 21.992 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.214      ; 9.473      ;
; 21.992 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.214      ; 9.473      ;
; 21.994 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.224      ; 9.481      ;
; 21.994 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.224      ; 9.481      ;
; 22.004 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.229      ; 9.476      ;
; 22.005 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.233      ; 9.479      ;
; 22.006 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.232      ; 9.477      ;
; 22.006 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.236      ; 9.481      ;
; 22.011 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.238      ; 9.478      ;
; 22.019 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.251      ; 9.483      ;
; 22.019 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.251      ; 9.483      ;
; 22.029 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.254      ; 9.476      ;
; 22.029 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.254      ; 9.476      ;
; 22.037 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.264      ; 9.478      ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                        ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                         ; To Node                                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 27.749 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.037     ; 3.465      ;
; 28.156 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.037     ; 3.058      ;
; 28.167 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.037     ; 3.047      ;
; 28.200 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_RD     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.074     ; 2.977      ;
; 28.523 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_WR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.073     ; 2.655      ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                                        ;
+-------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                ; To Node                                                                                                          ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.701 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 2.003      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 1.792 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 2.082      ;
; 2.085 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.385      ;
; 2.085 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.385      ;
; 2.085 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.385      ;
; 2.085 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.385      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.088      ; 2.404      ;
; 2.330 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE                                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 2.631      ;
; 2.330 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 2.631      ;
; 2.330 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 2.631      ;
; 2.358 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.073      ; 2.643      ;
; 2.435 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.070      ; 2.717      ;
; 2.435 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.070      ; 2.717      ;
; 2.435 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.070      ; 2.717      ;
; 2.686 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 2.977      ;
; 2.686 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 2.977      ;
; 2.686 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 2.977      ;
; 2.686 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 2.977      ;
; 2.686 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 2.977      ;
; 2.686 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 2.977      ;
; 2.702 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 2.986      ;
; 2.702 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 2.986      ;
; 2.754 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.035      ;
; 2.754 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.035      ;
; 2.754 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.035      ;
; 2.754 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.035      ;
; 2.754 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.035      ;
; 2.754 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.035      ;
; 2.793 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.074      ;
; 2.793 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.074      ;
; 2.793 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.074      ;
; 2.793 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 3.074      ;
; 3.305 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.068      ; 3.585      ;
; 3.305 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.068      ; 3.585      ;
; 3.305 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.068      ; 3.585      ;
; 3.305 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.068      ; 3.585      ;
; 3.305 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.068      ; 3.585      ;
; 3.426 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[22]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.709      ;
; 3.426 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.709      ;
; 3.426 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.709      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[23]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[21]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[20]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.444 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 3.727      ;
; 3.470 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 3.742      ;
; 3.470 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 3.742      ;
; 3.470 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 3.742      ;
; 3.470 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 3.742      ;
; 3.470 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 3.742      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:13:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:14:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[4]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:11:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[4] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:12:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[4] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:11:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:12:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:12:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:11:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 4.262      ;
; 3.965 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[3]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.089      ; 4.266      ;
+-------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                     ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                                                  ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.065 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.168      ; 4.465      ;
; 4.454 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.293      ; 4.979      ;
; 4.454 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.293      ; 4.979      ;
; 4.454 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.293      ; 4.979      ;
; 4.454 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.293      ; 4.979      ;
; 4.465 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.286      ; 4.983      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.256      ; 4.978      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[3]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.974      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.974      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.256      ; 4.978      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.974      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.256      ; 4.978      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[5]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.974      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.974      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[0]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.974      ;
; 4.490 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[16]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.256      ; 4.978      ;
; 4.491 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.255      ; 4.978      ;
; 4.493 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.256      ; 4.981      ;
; 4.493 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[14]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.249      ; 4.974      ;
; 4.493 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.256      ; 4.981      ;
; 4.493 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[8]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.249      ; 4.974      ;
; 4.496 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.979      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.982      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.982      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.249      ; 4.980      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.982      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.249      ; 4.980      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.982      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.982      ;
; 4.499 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.251      ; 4.982      ;
; 4.500 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.252      ; 4.984      ;
; 4.501 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[19] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.247      ; 4.980      ;
; 4.501 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.247      ; 4.980      ;
; 4.501 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.247      ; 4.980      ;
; 4.503 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.240      ; 4.975      ;
; 4.504 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.249      ; 4.985      ;
; 4.504 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.249      ; 4.985      ;
; 4.505 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.953      ;
; 4.505 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.953      ;
; 4.505 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.953      ;
; 4.505 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.953      ;
; 4.505 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.953      ;
; 4.505 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.953      ;
; 4.506 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.241      ; 4.979      ;
; 4.507 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.244      ; 4.983      ;
; 4.507 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.244      ; 4.983      ;
; 4.507 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.244      ; 4.983      ;
; 4.507 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.244      ; 4.983      ;
; 4.507 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.244      ; 4.983      ;
; 4.512 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.240      ; 4.984      ;
; 4.512 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.238      ; 4.982      ;
; 4.512 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.240      ; 4.984      ;
; 4.512 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.240      ; 4.984      ;
; 4.514 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.231      ; 4.977      ;
; 4.514 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.238      ; 4.984      ;
; 4.514 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.235      ; 4.981      ;
; 4.514 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.233      ; 4.979      ;
; 4.514 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.231      ; 4.977      ;
; 4.514 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.237      ; 4.983      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[19]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.230      ; 4.977      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.230      ; 4.977      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[18]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.230      ; 4.977      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.236      ; 4.983      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.230      ; 4.977      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.236      ; 4.983      ;
; 4.515 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.236      ; 4.983      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[11]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[10]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[12]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.208      ; 4.956      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[14]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[15]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.516 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[8]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.224      ; 4.972      ;
; 4.517 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.232      ; 4.981      ;
; 4.525 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.982      ;
; 4.525 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.982      ;
; 4.525 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.982      ;
; 4.527 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.984      ;
; 4.527 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.984      ;
; 4.527 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.984      ;
; 4.527 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.984      ;
; 4.527 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.984      ;
; 4.528 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.213      ; 4.973      ;
; 4.530 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.212      ; 4.974      ;
; 4.530 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.216      ; 4.978      ;
; 4.534 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.215      ; 4.981      ;
; 4.534 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.215      ; 4.981      ;
; 4.534 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.215      ; 4.981      ;
; 4.536 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.210      ; 4.978      ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                         ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                         ; To Node                                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 33.361 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_WR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.125      ; 2.468      ;
; 33.637 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_RD     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.124      ; 2.743      ;
; 33.640 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.123      ; 2.745      ;
; 33.721 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.123      ; 2.826      ;
; 33.990 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.123      ; 3.095      ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 12.384 ; 12.604       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 12.384 ; 12.604       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 12.384 ; 12.604       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 12.384 ; 12.604       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
; 12.596 ; 12.784       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 12.596 ; 12.784       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 12.596 ; 12.784       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 12.596 ; 12.784       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
; 12.653 ; 12.653       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576|clk                                                                 ;
; 12.653 ; 12.653       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                                                     ;
; 12.653 ; 12.653       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                                                     ;
; 12.653 ; 12.653       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                                                     ;
; 12.658 ; 12.658       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] ;
; 12.658 ; 12.658       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk   ;
; 12.731 ; 12.731       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] ;
; 12.731 ; 12.731       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk   ;
; 12.736 ; 12.736       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576|clk                                                                 ;
; 12.736 ; 12.736       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                                                     ;
; 12.736 ; 12.736       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                                                     ;
; 12.736 ; 12.736       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                                                     ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                           ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                                      ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------+
; 15.295 ; 15.515       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11]    ;
; 15.295 ; 15.515       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12]    ;
; 15.295 ; 15.515       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[14]    ;
; 15.296 ; 15.516       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[0]       ;
; 15.296 ; 15.516       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4]       ;
; 15.296 ; 15.516       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]       ;
; 15.296 ; 15.516       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]       ;
; 15.297 ; 15.517       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]       ;
; 15.297 ; 15.517       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[2]       ;
; 15.297 ; 15.517       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[3]       ;
; 15.297 ; 15.517       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[6]       ;
; 15.299 ; 15.519       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[7]         ;
; 15.299 ; 15.519       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[10]      ;
; 15.299 ; 15.519       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[15]      ;
; 15.299 ; 15.519       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[8]       ;
; 15.299 ; 15.519       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                                  ;
; 15.299 ; 15.519       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                                  ;
; 15.300 ; 15.520       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[8]     ;
; 15.300 ; 15.520       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]        ;
; 15.300 ; 15.520       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                                 ;
; 15.300 ; 15.520       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                                 ;
; 15.301 ; 15.521       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                     ;
; 15.301 ; 15.521       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                     ;
; 15.301 ; 15.521       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                      ;
; 15.304 ; 15.524       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                   ;
; 15.304 ; 15.524       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[4]                   ;
; 15.304 ; 15.524       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[5]                   ;
; 15.304 ; 15.524       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[2]       ;
; 15.304 ; 15.524       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]       ;
; 15.305 ; 15.525       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[7]                   ;
; 15.305 ; 15.525       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[20]                     ;
; 15.306 ; 15.526       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[11]      ;
; 15.306 ; 15.526       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[12]      ;
; 15.306 ; 15.526       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[14]      ;
; 15.307 ; 15.527       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[2]                   ;
; 15.307 ; 15.527       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]     ;
; 15.307 ; 15.527       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]        ;
; 15.308 ; 15.528       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[18]                ;
; 15.308 ; 15.528       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]                ;
; 15.308 ; 15.528       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]                ;
; 15.308 ; 15.528       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]       ;
; 15.308 ; 15.528       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]       ;
; 15.308 ; 15.528       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]       ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                     ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]        ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]       ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]       ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]       ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]       ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]       ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                                  ;
; 15.310 ; 15.530       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                                  ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                      ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[22]                     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[2]                      ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[3]                      ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                      ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                      ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[7]                      ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[0]     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[23]    ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[2]     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]     ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.CHK_CMD                           ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                                  ;
; 15.311 ; 15.531       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                              ;
; 15.312 ; 15.532       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]      ;
; 15.312 ; 15.532       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[0]        ;
; 15.312 ; 15.532       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]        ;
; 15.312 ; 15.532       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[2]        ;
; 15.312 ; 15.532       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[3]        ;
; 15.312 ; 15.532       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[7]        ;
; 15.313 ; 15.533       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]       ;
; 15.314 ; 15.534       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18]    ;
; 15.314 ; 15.534       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20]    ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[0]                   ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[4]                      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]      ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[16]    ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]                 ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]                 ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]                 ;
; 15.315 ; 15.535       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]                 ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10]    ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13]    ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15]    ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17]    ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]                ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK         ;
; 15.316 ; 15.536       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|address_reg_a[2] ;
; 15.317 ; 15.537       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|LINE80_RELOAD                  ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 19.218 ; 19.438       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 19.218 ; 19.438       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
; 19.433 ; 19.621       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 19.433 ; 19.621       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
; 19.487 ; 19.487       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4|clk                                                                  ;
; 19.487 ; 19.487       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]|clk                                                         ;
; 19.494 ; 19.494       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.494 ; 19.494       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.567 ; 19.567       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.567 ; 19.567       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.573 ; 19.573       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4|clk                                                                  ;
; 19.573 ; 19.573       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]|clk                                                         ;
; 36.575 ; 39.062       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 36.575 ; 39.062       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                      ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                 ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------------------+
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[72]                     ;
; 20.498 ; 20.718       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[73]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[56]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[57]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[58]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[59]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[60]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[61]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[62]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[63]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[48]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[49]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[50]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[51]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[52]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[53]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[54]                     ;
; 20.506 ; 20.726       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[55]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[64]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[65]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[66]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[67]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[68]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[69]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[70]                     ;
; 20.507 ; 20.727       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[71]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[32]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[33]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[34]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[35]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[36]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[37]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[38]                     ;
; 20.508 ; 20.728       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[39]                     ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[112]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[113]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[114]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[115]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[116]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[117]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[118]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[119]                    ;
; 20.512 ; 20.732       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]          ;
; 20.513 ; 20.733       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.CMD_12             ;
; 20.513 ; 20.733       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]           ;
; 20.513 ; 20.733       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]           ;
; 20.514 ; 20.734       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[31]              ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[100]                    ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[101]                    ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[102]                    ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[103]                    ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[96]                     ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[97]                     ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[98]                     ;
; 20.515 ; 20.735       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[99]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[48]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[49]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[50]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[51]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[52]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[53]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[54]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[55]                     ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[126]                    ;
; 20.516 ; 20.736       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[127]                    ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[0]                      ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[5]                      ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[7]                      ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]               ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[7]               ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                     ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                    ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]          ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]          ;
; 20.518 ; 20.738       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]           ;
; 20.524 ; 20.744       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:CMD_SHIFT[40]  ;
; 20.524 ; 20.744       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:CMD_SHIFT[43]  ;
; 20.524 ; 20.744       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:CMD_SHIFT[45]  ;
; 20.524 ; 20.744       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:CMD_SHIFT[8]   ;
; 20.524 ; 20.744       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:SHIFTER[1] ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|LED_1                                            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|LED_2                                            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC           ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[21]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[22]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[23]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[24]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[25]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[26]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[27]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[28]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[29]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[30]            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY            ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                    ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                      ;
; 20.525 ; 20.745       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                         ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                                                  ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------+
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[29]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[29]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[30]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[30]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[31]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[31]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[0]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[10]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[11]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[12]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[13]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[14]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[15]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[16]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[17]              ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[18]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[19]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[1]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[20]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[21]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[22]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[23]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[24]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[25]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[26]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[27]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[28]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[29]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[2]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[30]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[31]~_Duplicate_1 ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[3]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[4]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[5]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[6]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[7]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[8]               ;
; 30.806 ; 31.207       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[9]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[2]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[3]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[4]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[5]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[6]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[7]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[8]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[9]               ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[18]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[19]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[20]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[21]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[22]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[23]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[24]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[25]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[26]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[27]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[28]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[29]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[30]              ;
; 30.807 ; 31.208       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[31]              ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 30.808 ; 31.209       ; 0.401          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                            ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                                       ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------+
; 30.920 ; 31.140       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[0]               ;
; 30.920 ; 31.140       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[5]               ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[12]                           ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[1]                            ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[2]                            ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[3]                            ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[8]                            ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[9]                            ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[6]               ;
; 30.921 ; 31.141       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[7]               ;
; 30.923 ; 31.143       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[13]                           ;
; 30.923 ; 31.143       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[14]                           ;
; 30.923 ; 31.143       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[15]                           ;
; 30.924 ; 31.144       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[2]               ;
; 30.924 ; 31.144       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[4]               ;
; 30.924 ; 31.144       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]                            ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[12]                          ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[3]                           ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[6]                           ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[7]                           ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][11]                      ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][13]                      ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][14]                      ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][3]                       ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][12]                      ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][4]                       ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[7][12]                      ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[7][4]                       ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[7][5]                       ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[8][12]                      ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[8][3]                       ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[8][8]                       ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[10]              ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[11]              ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[2]               ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[3]               ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[4]               ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[8]               ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_A[9]               ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]                                    ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[1]                                    ;
; 30.925 ; 31.145       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[4]                                    ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[13]                          ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][1]                      ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][2]                      ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][3]                      ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][8]                      ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][9]                      ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[7][13]                      ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_X_INCR[4]                            ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[3]               ;
; 30.926 ; 31.146       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[4]               ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|ENV_FREQ[13]                 ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[4]                                    ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[3] ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[4] ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[5] ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[7] ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0] ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[2] ;
; 30.928 ; 31.148       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[5] ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[3]                              ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[7]                              ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[8]                              ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[9]                              ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_X_INCR[13]                           ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_X_INCR[14]                           ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[5]               ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[6]               ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[7]               ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|HDREG[0]                       ;
; 30.929 ; 31.149       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|HDREG[1]                       ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[12]                          ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[1]                           ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[2]                           ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[3]                           ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[4]                           ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|OP_I[1]                                  ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|OP_I[3]                                  ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|ENV_FREQ[14]                 ;
; 30.930 ; 31.150       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|ENV_FREQ[15]                 ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[10]                          ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[11]                          ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[4]                           ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[5]                           ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[8]                           ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[9]                           ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[10]                           ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[11]                           ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[5]                            ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[6]                            ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[7]                            ;
; 30.931 ; 31.151       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[6] ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[0]                              ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[10]                             ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[11]                             ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[12]                             ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[2]                              ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[4]                              ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[5]                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 30.932 ; 31.152       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 30.939 ; 31.159       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 30.939 ; 31.159       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 30.939 ; 31.159       ; 0.220          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
; 31.150 ; 31.338       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 31.150 ; 31.338       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 31.150 ; 31.338       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
; 31.156 ; 31.344       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 31.156 ; 31.344       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 31.156 ; 31.344       ; 0.188          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 31.201 ; 31.201       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                                                      ;
; 31.201 ; 31.201       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                                                      ;
; 31.201 ; 31.201       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                                                      ;
; 31.208 ; 31.208       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5|clk                                                                   ;
; 31.208 ; 31.208       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0|clk                                                                   ;
; 31.208 ; 31.208       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                                                      ;
; 31.213 ; 31.213       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ;
; 31.213 ; 31.213       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk   ;
; 31.285 ; 31.285       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ;
; 31.285 ; 31.285       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk   ;
; 31.290 ; 31.290       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5|clk                                                                   ;
; 31.290 ; 31.290       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0|clk                                                                   ;
; 31.290 ; 31.290       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                                                      ;
; 31.296 ; 31.296       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                                                      ;
; 31.296 ; 31.296       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                                                      ;
; 31.296 ; 31.296       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                                                      ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_PLL1'                                                                                                 ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                            ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; 31.009 ; 31.197       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 31.009 ; 31.197       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 31.009 ; 31.197       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 31.009 ; 31.197       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 31.009 ; 31.197       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 31.009 ; 31.197       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 31.010 ; 31.198       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 31.010 ; 31.198       ; 0.188          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 31.080 ; 31.300       ; 0.220          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
; 31.104 ; 31.104       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.104 ; 31.104       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.104 ; 31.104       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.104 ; 31.104       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]           ;
; 31.104 ; 31.104       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 31.135 ; 31.135       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|o                                                  ;
; 31.145 ; 31.145       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|inclk[0]                                    ;
; 31.145 ; 31.145       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|outclk                                      ;
; 31.149 ; 31.149       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT|clk                                                     ;
; 31.149 ; 31.149       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                                          ;
; 31.149 ; 31.149       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                                          ;
; 31.149 ; 31.149       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                                          ;
; 31.149 ; 31.149       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                                          ;
; 31.149 ; 31.149       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                                          ;
; 31.150 ; 31.150       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                                                    ;
; 31.150 ; 31.150       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                                               ;
; 31.167 ; 31.167       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|i                                                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|i                                                  ;
; 31.332 ; 31.332       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                                                    ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT|clk                                                     ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                                          ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                                          ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                                          ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                                          ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                                          ;
; 31.349 ; 31.349       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                                               ;
; 31.354 ; 31.354       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|inclk[0]                                    ;
; 31.354 ; 31.354       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|outclk                                      ;
; 31.365 ; 31.365       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|o                                                  ;
; 31.394 ; 31.394       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.394 ; 31.394       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.394 ; 31.394       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.394 ; 31.394       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]           ;
; 31.394 ; 31.394       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 58.500 ; 62.500       ; 4.000          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLK_PLL2'                                                                                                 ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                            ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; 31.107 ; 31.107       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.107 ; 31.107       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.107 ; 31.107       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.107 ; 31.107       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 31.131 ; 31.131       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|o                                                  ;
; 31.170 ; 31.170       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|i                                                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|i                                                  ;
; 31.329 ; 31.329       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.369 ; 31.369       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|o                                                  ;
; 31.391 ; 31.391       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.391 ; 31.391       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.391 ; 31.391       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.391 ; 31.391       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 58.500 ; 62.500       ; 4.000          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                                          ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; -0.224 ; 0.002  ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; 10.240 ; 9.948  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 28.366 ; 27.967 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 19.905 ; 20.273 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 19.546 ; 19.903 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 28.227 ; 27.967 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 28.105 ; 27.660 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 28.366 ; 27.910 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 17.046 ; 16.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 14.594 ; 14.611 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 14.673 ; 14.568 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 15.116 ; 14.793 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 15.301 ; 15.105 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 13.579 ; 13.419 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 13.169 ; 13.101 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 15.102 ; 14.847 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 15.375 ; 15.201 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 14.205 ; 14.237 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 16.550 ; 16.078 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 15.869 ; 15.882 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 16.213 ; 15.927 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 17.046 ; 16.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 14.199 ; 14.212 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 12.154 ; 12.293 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 11.907 ; 12.387 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 6.220  ; 6.520  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; 4.473  ; 4.555  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 7.377  ; 7.857  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; 7.966  ; 8.379  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; 4.686  ; 5.006  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 5.334  ; 5.653  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 19.162 ; 19.096 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 17.222 ; 16.956 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 16.998 ; 16.559 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 18.545 ; 17.673 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 17.435 ; 16.814 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 15.135 ; 14.671 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 15.187 ; 14.765 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 16.115 ; 15.640 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 16.153 ; 15.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 16.160 ; 15.845 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 18.682 ; 17.896 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 16.677 ; 16.335 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 16.044 ; 15.675 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 14.588 ; 14.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 14.933 ; 15.129 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 15.162 ; 15.374 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 19.162 ; 19.096 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; 2.414  ; 2.709  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 6.717  ; 6.988  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; 17.076 ; 16.899 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 8.312  ; 8.696  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; 8.312  ; 8.696  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; 7.702  ; 8.082  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 6.109  ; 6.425  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; 6.433  ; 6.819  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 8.207  ; 8.492  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 24.334 ; 23.898 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 16.632 ; 17.000 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 16.273 ; 16.630 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 24.195 ; 23.898 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 24.073 ; 23.591 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 24.334 ; 23.841 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 12.653 ; 12.523 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 10.728 ; 10.998 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 10.819 ; 10.891 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 11.006 ; 11.104 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 11.807 ; 11.885 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 10.409 ; 10.556 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 9.848  ; 9.970  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 11.586 ; 11.601 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 12.102 ; 12.121 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 10.597 ; 10.836 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 12.653 ; 12.523 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 10.813 ; 10.984 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 11.686 ; 11.553 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 12.184 ; 12.090 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 9.003  ; 9.252  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 8.295  ; 8.386  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 7.434  ; 7.749  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 14.785 ; 14.341 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.356 ; 13.343 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.144 ; 12.882 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 14.435 ; 13.984 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.941 ; 13.594 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.965 ; 11.808 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.866 ; 11.634 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.599 ; 12.394 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.880 ; 12.644 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.552 ; 12.444 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 14.785 ; 14.341 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 11.621 ; 11.437 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 11.517 ; 11.301 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.726  ; 9.850  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.737  ; 9.933  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 11.300 ; 11.512 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 14.378 ; 14.312 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 24.985 ; 24.549 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; 17.201 ; 17.569 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; 16.842 ; 17.199 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 24.846 ; 24.549 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 24.724 ; 24.242 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 24.985 ; 24.492 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; 12.695 ; 12.739 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; 11.379 ; 11.583 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; 11.269 ; 11.383 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; 12.248 ; 12.289 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; 12.695 ; 12.739 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; 10.886 ; 10.972 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; 11.021 ; 11.033 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; 12.337 ; 12.244 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; 12.671 ; 12.617 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; 10.781 ; 10.983 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 15.677 ; 15.169 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 14.007 ; 13.928 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.594 ; 13.374 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 15.677 ; 15.169 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 14.829 ; 14.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.442 ; 12.224 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.039 ; 12.697 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.350 ; 13.037 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 13.449 ; 13.140 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.736 ; 12.591 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.675  ; 10.016 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 10.546 ; 10.818 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.703  ; 10.069 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.816 ; 11.155 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.738 ; 11.059 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.901 ; 11.192 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.604 ; 10.945 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; 12.418 ; 12.498 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 14.384 ; 14.184 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 14.245 ; 14.184 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 14.123 ; 13.877 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 14.384 ; 14.127 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 25.953 ; 25.843 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 25.814 ; 25.843 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 25.692 ; 25.536 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 25.953 ; 25.786 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; 25.740 ; 25.615 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; 18.390 ; 18.758 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; 18.031 ; 18.388 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 25.601 ; 25.615 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 25.479 ; 25.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 25.740 ; 25.558 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; 15.076 ; 14.833 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; 11.870 ; 12.179 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; 12.615 ; 12.674 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; 13.542 ; 13.460 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; 13.026 ; 13.132 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; 11.437 ; 11.572 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; 11.894 ; 12.028 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; 13.172 ; 13.143 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; 13.860 ; 13.882 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; 13.025 ; 13.150 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; 15.076 ; 14.833 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; 13.531 ; 13.582 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; 13.969 ; 13.749 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; 14.282 ; 14.085 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; 11.382 ; 11.516 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; 9.442  ; 9.602  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; 9.621  ; 9.810  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 17.208 ; 16.683 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 14.498 ; 14.524 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 14.940 ; 14.665 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 16.971 ; 16.340 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 15.160 ; 14.841 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.993 ; 12.824 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.912 ; 13.692 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 14.185 ; 13.936 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 14.638 ; 14.405 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 14.980 ; 14.758 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 17.208 ; 16.651 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 14.339 ; 14.035 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 13.800 ; 13.497 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 11.824 ; 11.845 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.116 ; 12.312 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.450 ; 12.662 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 16.749 ; 16.683 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 8.890  ; 9.141  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; 10.858 ; 11.031 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                           ;
+---------------+------------+---------+---------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+---------+---------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; 0.995   ; 0.761   ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; -5.674  ; -5.830  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -5.069  ; -5.341  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -5.418  ; -5.699  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -5.069  ; -5.341  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -8.602  ; -8.659  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -8.635  ; -8.604  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -10.763 ; -10.662 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -5.340  ; -5.631  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -7.062  ; -7.223  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -6.888  ; -7.106  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -7.692  ; -7.871  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -7.379  ; -7.464  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -5.340  ; -5.631  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -6.642  ; -6.881  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -8.005  ; -8.181  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -6.698  ; -6.995  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -6.467  ; -6.766  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -7.396  ; -7.695  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -7.134  ; -7.372  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -6.644  ; -6.858  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -9.084  ; -9.124  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -7.883  ; -8.125  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -7.355  ; -7.389  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -7.418  ; -7.628  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; -5.300  ; -5.591  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; -2.740  ; -2.851  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; -5.210  ; -5.494  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; -5.808  ; -6.142  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; -3.826  ; -4.136  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; -4.353  ; -4.628  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -8.826  ; -8.836  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -11.959 ; -11.885 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -12.197 ; -11.895 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -13.639 ; -13.103 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -13.075 ; -12.673 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -9.658  ; -9.559  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -11.170 ; -10.896 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -11.874 ; -11.547 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -11.405 ; -11.170 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -12.031 ; -11.832 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -14.046 ; -13.522 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -11.283 ; -10.962 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -10.964 ; -10.676 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -8.826  ; -8.836  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -9.227  ; -9.405  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -9.863  ; -10.055 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -13.853 ; -13.745 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; -1.655  ; -1.942  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; -5.745  ; -6.005  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; -6.441  ; -6.630  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; -5.737  ; -6.074  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; -5.870  ; -6.244  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; -5.737  ; -6.074  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; -4.840  ; -5.102  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; -5.421  ; -5.784  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; -4.868  ; -5.186  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -7.681  ; -7.683  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -14.076 ; -14.332 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -13.735 ; -13.974 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -7.681  ; -7.738  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -7.714  ; -7.683  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -9.417  ; -9.247  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -4.928  ; -5.326  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -6.456  ; -6.676  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -5.419  ; -5.679  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -6.557  ; -6.848  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -4.928  ; -5.326  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -6.219  ; -6.466  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -6.028  ; -6.360  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -6.700  ; -7.028  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -6.315  ; -6.642  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -5.374  ; -5.744  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -5.975  ; -6.353  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -6.209  ; -6.551  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -5.627  ; -5.922  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -8.399  ; -8.525  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -6.347  ; -6.668  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -5.940  ; -6.158  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -5.880  ; -6.171  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -7.770  ; -7.948  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -11.350 ; -11.334 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -11.516 ; -11.286 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -12.504 ; -12.080 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -12.316 ; -12.002 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -10.537 ; -10.394 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -10.556 ; -10.375 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -10.709 ; -10.548 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -11.022 ; -10.817 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -10.938 ; -10.810 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -12.625 ; -12.180 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -10.356 ; -10.140 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -9.947  ; -9.740  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -8.141  ; -8.237  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -7.770  ; -7.948  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -8.632  ; -8.824  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -12.396 ; -12.288 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -4.573  ; -4.846  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; -4.992  ; -5.249  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; -4.573  ; -4.846  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -7.284  ; -7.351  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -7.317  ; -7.296  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -9.159  ; -9.054  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; -4.616  ; -4.912  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; -5.225  ; -5.564  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; -5.076  ; -5.429  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; -4.616  ; -4.912  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; -5.164  ; -5.450  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; -5.388  ; -5.698  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; -5.217  ; -5.625  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; -5.546  ; -5.981  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; -5.680  ; -6.086  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; -5.903  ; -6.224  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.538  ; -3.861  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -3.538  ; -3.861  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -4.193  ; -4.458  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -3.893  ; -4.181  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -4.254  ; -4.524  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.238  ; -4.445  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.188  ; -4.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -4.104  ; -4.363  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.192  ; -4.441  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -4.509  ; -4.761  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -4.232  ; -4.457  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.277  ; -4.481  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.192  ; -4.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -4.238  ; -4.505  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -4.212  ; -4.485  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -4.324  ; -4.583  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -4.507  ; -4.781  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; -5.613  ; -5.788  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -9.003  ; -9.047  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -9.097  ; -9.287  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -9.003  ; -9.047  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -9.253  ; -9.289  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -11.190 ; -11.032 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -11.190 ; -11.087 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -11.223 ; -11.032 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -13.026 ; -12.923 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; -8.543  ; -8.567  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; -14.373 ; -14.629 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; -14.032 ; -14.271 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -8.543  ; -8.622  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -8.576  ; -8.567  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -10.379 ; -10.458 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; -5.576  ; -5.899  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; -6.857  ; -7.066  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; -7.220  ; -7.526  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; -5.577  ; -5.945  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; -5.576  ; -5.899  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; -6.298  ; -6.575  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; -6.368  ; -6.635  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; -6.776  ; -7.125  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; -5.866  ; -6.115  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; -7.122  ; -7.405  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; -7.617  ; -7.952  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; -7.517  ; -7.811  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; -7.411  ; -7.562  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; -9.448  ; -9.504  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; -7.934  ; -8.189  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; -7.082  ; -7.294  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; -7.182  ; -7.397  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -9.190  ; -9.216  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -11.755 ; -11.727 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -12.293 ; -12.163 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -13.100 ; -12.801 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -12.243 ; -12.010 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -10.370 ; -10.237 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -10.875 ; -10.650 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -11.246 ; -11.042 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -11.350 ; -11.114 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -12.686 ; -12.471 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -14.267 ; -13.779 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -11.666 ; -11.401 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -11.731 ; -11.380 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -9.190  ; -9.216  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -9.291  ; -9.469  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -9.768  ; -9.960  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -13.622 ; -13.514 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; -3.830  ; -4.110  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; -5.302  ; -5.464  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+---------+---------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                              ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 11.857 ; 11.166 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 24.633 ; 23.629 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 23.311 ; 22.350 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 22.659 ; 21.878 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 23.434 ; 22.535 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 24.215 ; 23.350 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 23.921 ; 23.096 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 24.633 ; 23.488 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 23.401 ; 22.676 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 23.521 ; 22.649 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 20.791 ; 19.825 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 20.659 ; 19.716 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 19.354 ; 18.547 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 19.732 ; 19.054 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 19.194 ; 18.443 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 20.939 ; 20.623 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 24.180 ; 23.629 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 22.014 ; 21.550 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 15.528 ; 15.226 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 20.910 ; 20.765 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 13.727 ; 12.842 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 13.376 ; 12.803 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 11.476 ; 10.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 12.177 ; 11.486 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 12.267 ; 11.637 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 13.306 ; 12.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 12.331 ; 11.713 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 11.688 ; 11.234 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 11.193 ; 10.888 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 13.217 ; 12.793 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 12.887 ; 12.255 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 15.283 ; 14.225 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 12.244 ; 11.406 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 12.462 ; 11.629 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 12.960 ; 12.234 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 19.320 ; 18.908 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 19.137 ; 18.719 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 20.910 ; 20.765 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 11.390 ; 10.868 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 10.992 ; 10.556 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 12.677 ; 12.184 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 12.325 ; 11.946 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 7.429  ; 7.147  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 4.464  ; 4.697  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 5.284  ; 5.020  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 5.982  ; 5.708  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 6.925  ; 7.419  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 12.317 ; 11.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 9.797  ; 9.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 10.248 ; 10.124 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 9.234  ; 9.013  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 9.843  ; 9.792  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 11.744 ; 11.419 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 12.317 ; 11.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 10.379 ; 10.065 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 10.459 ; 10.091 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 8.806  ; 8.542  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 8.934  ; 8.593  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 9.267  ; 8.922  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 10.107 ; 9.669  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 9.378  ; 9.007  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 9.718  ; 9.300  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 9.585  ; 9.283  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 10.294 ; 9.786  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 7.504  ; 7.856  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 7.162  ; 6.804  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 5.092  ; 4.873  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 6.760  ; 6.482  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 21.028 ; 20.952 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 23.168 ; 22.798 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 7.675  ; 8.072  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.664  ; 5.407  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 9.598  ; 9.437  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 11.784 ; 11.057 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 8.353  ; 7.736  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 6.680  ; 6.330  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 16.370 ; 15.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 14.537 ; 14.194 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 15.016 ; 14.686 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 13.676 ; 13.360 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 15.313 ; 15.063 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 15.707 ; 15.417 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 15.180 ; 15.005 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 15.452 ; 15.174 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 15.379 ; 14.992 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 16.370 ; 15.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 14.163 ; 13.819 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 15.205 ; 14.892 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 13.970 ; 13.674 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 16.180 ; 15.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 17.288 ; 16.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 12.971 ; 12.317 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 17.288 ; 16.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 21.169 ; 20.181 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 31.119 ; 30.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 28.045 ; 27.558 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 26.078 ; 25.532 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 27.360 ; 26.978 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 27.529 ; 27.015 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 26.857 ; 25.853 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 29.529 ; 28.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 27.152 ; 26.695 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 26.840 ; 26.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 27.059 ; 26.376 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 28.320 ; 27.869 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 27.185 ; 26.875 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 28.914 ; 28.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 28.082 ; 27.397 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 28.918 ; 28.566 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 28.545 ; 27.994 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 31.119 ; 30.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 13.804 ; 13.344 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 14.929 ; 14.278 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 14.241 ; 13.973 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 8.947  ; 8.650  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 7.454  ; 6.997  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 17.870 ; 18.023 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;        ; 9.720  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;        ; 8.662  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;        ; 7.989  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;        ; 8.349  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;        ; 8.819  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;        ; 9.342  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;        ; 8.971  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;        ; 8.412  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;        ; 7.952  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;        ; 8.987  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;        ; 9.513  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;        ; 11.483 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;        ; 8.589  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;        ; 8.809  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;        ; 9.067  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 16.578 ; 16.166 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 16.395 ; 15.069 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 17.870 ; 18.023 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 18.286 ; 17.826 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 20.426 ; 19.672 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 13.226 ; 12.595 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 11.176 ; 10.826 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 11.335 ; 11.149 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 10.050 ; 9.770  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 11.550 ; 11.285 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 11.470 ; 11.173 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 11.882 ; 11.614 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 12.686 ; 12.432 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 12.397 ; 11.992 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 13.226 ; 12.595 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 10.180 ; 9.988  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.965 ; 11.738 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.903 ; 10.693 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 12.459 ; 12.176 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 13.791 ; 13.796 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;        ; 9.575  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 13.791 ; 13.796 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 17.672 ; 17.439 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.193 ; 25.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 23.128 ; 22.631 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 23.196 ; 22.397 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 23.285 ; 22.360 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 24.073 ; 23.320 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 23.516 ; 22.603 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 25.834 ; 25.047 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 23.457 ; 23.000 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 23.145 ; 22.616 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 24.317 ; 22.425 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 24.090 ; 23.639 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 23.490 ; 23.180 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 23.987 ; 23.538 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 23.176 ; 22.470 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 23.992 ; 23.640 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 24.522 ; 23.971 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 26.193 ; 25.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 10.854 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 11.979 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 18.367 ; 18.078 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 16.719 ; 16.350 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 16.573 ; 16.348 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 18.367 ; 18.078 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 8.843  ; 8.821  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 8.640  ; 8.465  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 8.820  ; 8.624  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 8.711  ; 8.821  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 8.843  ; 8.779  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 11.046 ; 10.494 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 11.046 ; 10.494 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 10.122 ; 10.026 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 8.615  ; 8.610  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 7.275  ; 7.057  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 9.662  ; 9.647  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 9.662  ; 9.647  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 8.630  ; 8.641  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 9.186  ; 9.335  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 9.513  ; 9.309  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 8.638  ; 9.220  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 18.176 ; 18.248 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 20.316 ; 20.094 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 7.434  ; 7.025  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 13.460 ; 12.937 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 11.474 ; 11.099 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.432  ; 9.326  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 10.788 ; 10.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 11.005 ; 10.740 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 11.563 ; 11.273 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 12.017 ; 11.143 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 11.046 ; 10.747 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 12.376 ; 11.932 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 13.460 ; 12.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 13.215 ; 12.245 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 12.498 ; 12.937 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.443 ; 10.233 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 12.102 ; 11.734 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 17.778 ; 16.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 8.590  ; 8.048  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 17.778 ; 16.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 21.659 ; 20.548 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 2.642  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 27.909 ; 27.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 26.206 ; 25.238 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 26.568 ; 25.658 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 27.260 ; 26.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 27.595 ; 27.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 27.347 ; 26.343 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 27.909 ; 26.778 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 26.429 ; 25.744 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 26.663 ; 25.962 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 27.545 ; 26.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 25.531 ; 24.913 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 24.169 ; 23.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 25.225 ; 24.776 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 25.404 ; 24.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 25.229 ; 24.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 26.704 ; 26.153 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 27.430 ; 26.886 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 11.807 ; 11.233 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 12.932 ; 12.167 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 10.166 ; 9.854  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 10.552 ; 10.414 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 13.009 ; 12.517 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 2.608  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;        ; 2.436  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;        ; 2.402  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 30.013 ; 29.632 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 21.338 ; 20.571 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 20.426 ; 19.967 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 19.683 ; 19.067 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 19.823 ; 19.245 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 20.420 ; 19.752 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 21.191 ; 20.390 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 20.800 ; 20.170 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 20.066 ; 19.529 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 19.763 ; 19.218 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 20.980 ; 20.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 21.519 ; 20.850 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 23.797 ; 22.695 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 20.914 ; 20.186 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 21.115 ; 20.434 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 21.692 ; 21.037 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 28.365 ; 27.996 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 28.004 ; 27.822 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 30.013 ; 29.632 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 29.895 ; 30.055 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 32.035 ; 31.901 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 25.009 ; 24.482 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 23.190 ; 22.847 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 23.748 ; 23.418 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 21.787 ; 21.471 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 23.275 ; 23.025 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 24.021 ; 23.731 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 24.345 ; 24.084 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 23.208 ; 22.810 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 24.279 ; 23.892 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 25.009 ; 24.355 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 21.965 ; 21.621 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 23.837 ; 23.524 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 22.484 ; 22.188 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 24.850 ; 24.482 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 26.233 ; 25.641 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 22.544 ; 21.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 26.233 ; 25.641 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 30.114 ; 29.284 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 37.490 ; 36.946 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 34.737 ; 34.049 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 35.088 ; 34.289 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 35.025 ; 34.179 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 35.435 ; 34.902 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 35.140 ; 34.616 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 35.931 ; 35.224 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 34.557 ; 33.992 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 34.428 ; 33.727 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 35.875 ; 35.001 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 34.873 ; 34.441 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 33.556 ; 33.246 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 35.285 ; 34.836 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 35.141 ; 34.391 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 35.289 ; 34.937 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 36.203 ; 35.652 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 37.490 ; 36.946 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 20.691 ; 20.084 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 20.548 ; 20.081 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 14.269 ; 14.471 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 9.942  ; 9.560  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 16.327 ; 16.091 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 14.679 ; 14.310 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 14.586 ; 14.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 16.327 ; 16.091 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 16.189 ; 16.208 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 18.329 ; 18.054 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 15.738 ; 14.918 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 15.738 ; 14.918 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 19.619 ; 18.561 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.694 ; 25.922 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 25.510 ; 24.364 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 25.353 ; 24.443 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 26.045 ; 25.127 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 26.380 ; 25.922 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 26.132 ; 25.128 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 26.694 ; 25.563 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 25.214 ; 24.529 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 25.448 ; 24.747 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 26.347 ; 25.375 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 24.434 ; 23.698 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 22.954 ; 22.143 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 23.956 ; 23.165 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 24.211 ; 23.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 23.868 ; 23.204 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 25.781 ; 25.230 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 25.056 ; 24.592 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 14.662 ; 14.336 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 14.638 ; 14.198 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 4.790  ; 4.615  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 8.980  ; 8.200  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 8.393  ; 7.942  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 5.788  ; 5.562  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 11.137 ; 10.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 11.137 ; 10.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 7.910  ; 7.354  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.874  ; 4.593  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 11.554 ; 10.846 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 15.345 ; 15.054 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 16.933 ; 16.326 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 17.173 ; 16.454 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 18.561 ; 17.734 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 20.019 ; 19.312 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 17.789 ; 17.050 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 19.745 ; 18.726 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 16.676 ; 16.200 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 16.882 ; 16.571 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 17.575 ; 17.053 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 16.944 ; 16.565 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 15.345 ; 15.082 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 15.783 ; 15.528 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 16.495 ; 16.143 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 15.522 ; 15.054 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 17.654 ; 17.133 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 16.189 ; 15.752 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 15.030 ; 14.724 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 5.084  ; 4.750  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 6.840  ; 6.490  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 7.217  ; 6.910  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 5.783  ; 5.433  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 6.977  ; 6.586  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 5.963  ; 5.608  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 6.477  ; 6.095  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 5.974  ; 5.691  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 6.286  ; 6.035  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 5.912  ; 5.631  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 6.542  ; 6.169  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 5.404  ; 5.161  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 7.792  ; 7.098  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 5.475  ; 5.127  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 5.587  ; 5.236  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 5.084  ; 4.750  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 5.095  ; 4.813  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 5.448  ; 5.196  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 6.289  ; 5.846  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 6.756  ; 6.334  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 6.312  ; 6.001  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 7.971  ; 7.580  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 7.482  ; 7.191  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 5.760  ; 5.552  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 3.901  ; 4.129  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 4.699  ; 4.441  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 5.370  ; 5.101  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 5.047  ; 5.298  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 5.519  ; 5.362  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 6.933  ; 6.496  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 6.544  ; 6.170  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 6.479  ; 6.189  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 6.383  ; 6.139  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 7.391  ; 7.155  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 9.298  ; 8.761  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 7.283  ; 6.907  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 6.627  ; 6.303  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 5.519  ; 5.362  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 5.763  ; 5.484  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 5.960  ; 5.727  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 6.692  ; 6.373  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 6.124  ; 5.804  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 6.298  ; 6.001  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 6.268  ; 6.073  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 6.904  ; 6.505  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 6.189  ; 6.656  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 5.917  ; 5.587  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 4.509  ; 4.294  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 5.546  ; 5.280  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 6.977  ; 6.690  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 9.289  ; 8.701  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 6.288  ; 6.652  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.062  ; 4.812  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 7.497  ; 7.191  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 6.727  ; 6.051  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 7.727  ; 7.117  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 6.032  ; 5.692  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 9.094  ; 8.785  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 9.732  ; 9.408  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.663  ; 9.383  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 9.094  ; 8.785  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 9.652  ; 9.454  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 10.222 ; 9.908  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.584 ; 10.277 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.579 ; 10.198 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 9.966  ; 9.620  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 12.261 ; 11.602 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.518  ; 9.265  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.167 ; 10.836 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.046 ; 9.816  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.933 ; 11.639 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 9.193  ; 9.310  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 9.193  ; 9.310  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 10.462 ; 9.951  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 11.813 ; 11.136 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.056  ; 7.458  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.464  ; 7.857  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.141  ; 7.458  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 9.887  ; 9.164  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.301 ; 9.882  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 9.909  ; 9.543  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.177 ; 10.262 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.839  ; 8.406  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.904  ; 8.371  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 9.910  ; 9.395  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.637  ; 9.017  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.550  ; 8.041  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.688  ; 8.054  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.435  ; 9.001  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.365  ; 7.873  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 9.840  ; 9.325  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.056  ; 7.552  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 9.310  ; 8.967  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 10.366 ; 9.799  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 11.540 ; 11.434 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 7.455  ; 7.064  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 6.775  ; 6.332  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 10.448 ; 7.254  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;        ; 8.957  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;        ; 7.893  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;        ; 7.261  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;        ; 7.523  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;        ; 8.093  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;        ; 8.522  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;        ; 8.166  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;        ; 7.578  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;        ; 7.254  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;        ; 8.128  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;        ; 8.714  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;        ; 10.652 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;        ; 7.799  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;        ; 8.010  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;        ; 8.253  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 10.970 ; 9.136  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 10.448 ; 9.726  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 11.907 ; 9.832  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 12.699 ; 12.229 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 14.842 ; 14.076 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 9.005  ; 8.688  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 9.789  ; 9.396  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.527  ; 9.164  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 9.005  ; 8.688  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 9.756  ; 9.356  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 10.142 ; 9.820  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.660 ; 10.337 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.410 ; 10.021 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 10.045 ; 9.509  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 12.261 ; 11.640 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.308  ; 9.041  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.073 ; 10.742 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.026 ; 9.713  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.472 ; 11.109 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 11.941 ; 8.797  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;        ; 8.797  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 11.941 ; 11.359 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 12.196 ; 13.992 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 9.638  ; 9.264  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 10.242 ; 9.908  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 9.854  ; 9.566  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 10.250 ; 10.028 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.884 ; 10.418 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 9.638  ; 9.264  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.939 ; 11.155 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 9.962  ; 9.534  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 10.180 ; 9.713  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 10.036 ; 9.693  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.965  ; 9.625  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.844  ; 10.049 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.345 ; 9.966  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 11.138 ; 10.602 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.711 ; 10.202 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.393 ; 10.055 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 11.187 ; 10.876 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 9.693  ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 10.749 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 11.317 ; 11.099 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 12.026 ; 11.644 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 11.317 ; 11.099 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 12.946 ; 12.377 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 5.987  ; 5.659  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 6.058  ; 5.699  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 6.872  ; 6.479  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 5.987  ; 5.659  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 6.235  ; 5.841  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 5.872  ; 5.682  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 9.180  ; 8.431  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 7.609  ; 7.296  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 5.872  ; 5.682  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 6.570  ; 6.218  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 6.118  ; 5.899  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 7.207  ; 6.828  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 6.781  ; 6.502  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 6.118  ; 5.899  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 6.905  ; 6.517  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 7.827  ; 8.389  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 13.510 ; 14.022 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 15.653 ; 15.869 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 5.862  ; 5.589  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 5.316  ; 5.112  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 6.903  ; 6.411  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 5.890  ; 5.550  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 6.083  ; 5.719  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 6.300  ; 5.955  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 6.588  ; 6.230  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 6.077  ; 5.622  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 6.560  ; 6.184  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 7.178  ; 6.699  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 8.020  ; 7.309  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 6.452  ; 6.200  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 6.496  ; 6.205  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 5.316  ; 5.112  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.645  ; 5.378  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 5.946  ; 5.539  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 5.946  ; 5.539  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 6.154  ; 5.726  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 6.965  ; 6.780  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 2.169  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 5.164  ; 4.797  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 5.354  ; 5.104  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 5.610  ; 5.454  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.600  ; 5.402  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.170  ; 5.831  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 5.164  ; 4.797  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.467  ; 6.690  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.490  ; 5.069  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.703  ; 5.243  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.229  ; 5.851  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.018  ; 5.737  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 5.700  ; 5.488  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 5.907  ; 5.611  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.295  ; 6.046  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.105  ; 5.763  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.102  ; 5.805  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 6.802  ; 6.406  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 5.512  ; 5.258  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 6.001  ; 5.633  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 5.963  ; 5.880  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 5.358  ; 5.769  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 10.365 ; 9.987  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 2.135  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;        ; 1.967  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;        ; 1.934  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 8.024  ; 7.553  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 9.900  ; 9.253  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 9.141  ; 8.676  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 8.215  ; 7.728  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 8.395  ; 7.911  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 8.900  ; 8.261  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 9.488  ; 8.805  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 8.954  ; 8.445  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 8.295  ; 7.861  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 8.024  ; 7.553  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 9.061  ; 8.537  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 9.381  ; 8.894  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 11.882 ; 10.889 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 8.690  ; 8.081  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 8.871  ; 8.295  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 9.993  ; 9.398  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 10.802 ; 10.277 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 9.887  ; 9.322  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 11.690 ; 10.975 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 12.199 ; 12.355 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 14.342 ; 14.202 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 9.634  ; 9.267  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 10.085 ; 9.692  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 10.310 ; 9.947  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 9.634  ; 9.267  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 10.079 ; 9.744  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 10.310 ; 9.988  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.943 ; 10.620 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.689 ; 10.300 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 10.328 ; 9.792  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 12.331 ; 11.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.717  ; 9.450  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.253 ; 10.922 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.263 ; 9.950  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.754 ; 11.391 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 9.869  ; 9.266  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 9.869  ; 9.266  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 11.202 ; 10.360 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 12.071 ; 11.191 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 9.247  ; 8.720  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 10.052 ; 9.464  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 10.213 ; 9.421  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 10.768 ; 10.582 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.868 ; 10.529 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 10.421 ; 10.047 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.622 ; 11.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 10.689 ; 10.317 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 10.607 ; 10.009 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 10.784 ; 10.408 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 10.713 ; 10.340 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.949  ; 9.335  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.103 ; 9.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.981 ; 10.373 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.247  ; 8.720  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.783 ; 10.047 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.374 ; 9.833  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 9.572  ; 9.012  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 9.534  ; 8.872  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 10.352 ; 10.658 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 9.171  ; 8.798  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 10.761 ; 10.178 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 11.658 ; 11.250 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 10.761 ; 10.178 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 12.389 ; 12.153 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 13.055 ; 13.229 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 15.198 ; 15.076 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 13.140 ; 12.338 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 13.140 ; 12.338 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 13.826 ; 12.885 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 11.135 ; 10.537 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.612 ; 11.749 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 11.518 ; 10.739 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.945 ; 12.087 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.458 ; 11.781 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 14.280 ; 13.468 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 15.269 ; 14.490 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.051 ; 12.354 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.973 ; 12.261 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 14.794 ; 13.704 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 14.012 ; 13.110 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 13.635 ; 12.736 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 11.711 ; 11.034 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 13.526 ; 12.666 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 11.135 ; 10.537 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 13.200 ; 12.459 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 12.935 ; 12.337 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 11.327 ; 10.706 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 11.258 ; 10.557 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 4.217  ; 4.044  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 8.326  ; 7.560  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 7.681  ; 7.243  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 4.162  ; 3.953  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 6.390  ; 6.026  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 6.390  ; 6.026  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 7.218  ; 6.680  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.305  ; 4.030  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------+
; Propagation Delay                                               ;
+--------------+--------------+--------+--------+--------+--------+
; Input Port   ; Output Port  ; RR     ; RF     ; FR     ; FF     ;
+--------------+--------------+--------+--------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 21.372 ; 20.452 ; 21.740 ; 20.701 ;
; CONFIG[1]    ; RAM_DATA[12] ; 11.883 ; 11.850 ; 12.521 ; 11.694 ;
; CONFIG[1]    ; RAM_DATA[13] ; 11.542 ; 11.543 ; 12.070 ; 11.500 ;
; CONFIG[1]    ; RAM_DATA[14] ; 11.083 ; 10.865 ; 11.408 ; 11.046 ;
; CONFIG[1]    ; RAM_DATA[15] ; 11.257 ; 12.448 ; 13.041 ; 11.155 ;
; CONFIG[2]    ; RAM_DATA[7]  ; 21.013 ; 20.097 ; 21.370 ; 20.330 ;
; CONFIG[2]    ; RAM_DATA[12] ; 11.530 ; 11.497 ; 12.222 ; 11.395 ;
; CONFIG[2]    ; RAM_DATA[13] ; 11.189 ; 11.190 ; 11.771 ; 11.201 ;
; CONFIG[2]    ; RAM_DATA[14] ; 10.730 ; 10.512 ; 11.109 ; 10.747 ;
; CONFIG[2]    ; RAM_DATA[15] ; 10.904 ; 12.095 ; 12.742 ; 10.856 ;
; CONFIG[3]    ; ADR[16]      ; 21.898 ; 21.486 ; 21.807 ; 21.438 ;
; CONFIG[3]    ; ADR[17]      ; 21.715 ; 21.235 ; 21.418 ; 21.264 ;
; CONFIG[3]    ; ADR[18]      ; 23.426 ; 23.343 ; 23.455 ; 23.046 ;
; CONFIG[3]    ; ADR[22]      ; 11.136 ;        ;        ; 11.170 ;
; CONFIG[3]    ; FLASH_CEn    ; 23.606 ; 23.468 ; 23.309 ; 23.497 ;
; CONFIG[3]    ; FLASH_OEn    ; 25.746 ; 25.314 ; 25.449 ; 25.343 ;
; CONFIG[3]    ; RAM_BA[1]    ; 19.690 ; 19.252 ; 19.790 ; 18.993 ;
; CONFIG[3]    ; RAM_CASn     ; 23.571 ; 22.895 ; 23.671 ; 22.636 ;
; CONFIG[3]    ; RAM_DATA[0]  ; 28.448 ; 27.462 ; 28.151 ; 27.491 ;
; CONFIG[3]    ; RAM_DATA[1]  ; 28.516 ; 27.717 ; 28.530 ; 27.731 ;
; CONFIG[3]    ; RAM_DATA[2]  ; 28.490 ; 27.592 ; 28.467 ; 27.621 ;
; CONFIG[3]    ; RAM_DATA[3]  ; 29.146 ; 28.315 ; 28.849 ; 28.344 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 28.836 ; 28.029 ; 28.582 ; 28.058 ;
; CONFIG[3]    ; RAM_DATA[5]  ; 29.642 ; 28.637 ; 29.345 ; 28.666 ;
; CONFIG[3]    ; RAM_DATA[6]  ; 28.201 ; 27.405 ; 27.999 ; 27.434 ;
; CONFIG[3]    ; RAM_DATA[7]  ; 27.841 ; 27.140 ; 27.870 ; 27.169 ;
; CONFIG[3]    ; RAM_DATA[8]  ; 29.586 ; 28.414 ; 29.289 ; 28.443 ;
; CONFIG[3]    ; RAM_DATA[9]  ; 28.541 ; 27.854 ; 28.315 ; 27.883 ;
; CONFIG[3]    ; RAM_DATA[10] ; 26.852 ; 26.494 ; 26.636 ; 26.523 ;
; CONFIG[3]    ; RAM_DATA[11] ; 27.929 ; 27.428 ; 27.958 ; 27.457 ;
; CONFIG[3]    ; RAM_DATA[12] ; 28.554 ; 27.804 ; 28.583 ; 27.833 ;
; CONFIG[3]    ; RAM_DATA[13] ; 27.878 ; 27.214 ; 27.618 ; 26.976 ;
; CONFIG[3]    ; RAM_DATA[14] ; 29.791 ; 29.240 ; 29.645 ; 29.094 ;
; CONFIG[3]    ; RAM_DATA[15] ; 29.066 ; 28.602 ; 28.927 ; 28.463 ;
; CONFIG[4]    ; ADR[16]      ; 21.776 ; 21.364 ; 21.500 ; 21.131 ;
; CONFIG[4]    ; ADR[17]      ; 21.593 ; 21.113 ; 21.111 ; 20.957 ;
; CONFIG[4]    ; ADR[18]      ; 23.304 ; 23.221 ; 23.148 ; 22.739 ;
; CONFIG[4]    ; ADR[21]      ; 11.655 ;        ;        ; 11.583 ;
; CONFIG[4]    ; FLASH_CEn    ; 23.484 ; 23.346 ; 23.002 ; 23.190 ;
; CONFIG[4]    ; FLASH_OEn    ; 25.624 ; 25.192 ; 25.142 ; 25.036 ;
; CONFIG[4]    ; RAM_BA[1]    ; 19.568 ; 19.130 ; 19.483 ; 18.686 ;
; CONFIG[4]    ; RAM_CASn     ; 23.449 ; 22.773 ; 23.364 ; 22.329 ;
; CONFIG[4]    ; RAM_DATA[0]  ; 28.326 ; 27.340 ; 27.844 ; 27.184 ;
; CONFIG[4]    ; RAM_DATA[1]  ; 28.394 ; 27.595 ; 28.223 ; 27.424 ;
; CONFIG[4]    ; RAM_DATA[2]  ; 28.368 ; 27.470 ; 28.160 ; 27.314 ;
; CONFIG[4]    ; RAM_DATA[3]  ; 29.024 ; 28.193 ; 28.542 ; 28.037 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 28.714 ; 27.907 ; 28.275 ; 27.751 ;
; CONFIG[4]    ; RAM_DATA[5]  ; 29.520 ; 28.515 ; 29.038 ; 28.359 ;
; CONFIG[4]    ; RAM_DATA[6]  ; 28.079 ; 27.283 ; 27.692 ; 27.127 ;
; CONFIG[4]    ; RAM_DATA[7]  ; 27.719 ; 27.018 ; 27.563 ; 26.862 ;
; CONFIG[4]    ; RAM_DATA[8]  ; 29.464 ; 28.292 ; 28.982 ; 28.136 ;
; CONFIG[4]    ; RAM_DATA[9]  ; 28.419 ; 27.732 ; 28.008 ; 27.576 ;
; CONFIG[4]    ; RAM_DATA[10] ; 26.730 ; 26.372 ; 26.329 ; 26.216 ;
; CONFIG[4]    ; RAM_DATA[11] ; 27.807 ; 27.306 ; 27.651 ; 27.150 ;
; CONFIG[4]    ; RAM_DATA[12] ; 28.432 ; 27.682 ; 28.276 ; 27.526 ;
; CONFIG[4]    ; RAM_DATA[13] ; 27.756 ; 27.092 ; 27.311 ; 26.669 ;
; CONFIG[4]    ; RAM_DATA[14] ; 29.669 ; 29.118 ; 29.338 ; 28.787 ;
; CONFIG[4]    ; RAM_DATA[15] ; 28.944 ; 28.480 ; 28.620 ; 28.156 ;
; CONFIG[5]    ; ADR[16]      ; 22.037 ; 21.625 ; 21.750 ; 21.381 ;
; CONFIG[5]    ; ADR[17]      ; 21.854 ; 21.374 ; 21.361 ; 21.207 ;
; CONFIG[5]    ; ADR[18]      ; 23.565 ; 23.482 ; 23.398 ; 22.989 ;
; CONFIG[5]    ; ADR[20]      ; 10.065 ;        ;        ; 10.069 ;
; CONFIG[5]    ; FLASH_CEn    ; 23.745 ; 23.607 ; 23.252 ; 23.440 ;
; CONFIG[5]    ; FLASH_OEn    ; 25.885 ; 25.453 ; 25.392 ; 25.286 ;
; CONFIG[5]    ; RAM_BA[1]    ; 19.829 ; 19.391 ; 19.733 ; 18.936 ;
; CONFIG[5]    ; RAM_CASn     ; 23.710 ; 23.034 ; 23.614 ; 22.579 ;
; CONFIG[5]    ; RAM_DATA[0]  ; 28.587 ; 27.601 ; 28.094 ; 27.434 ;
; CONFIG[5]    ; RAM_DATA[1]  ; 28.655 ; 27.856 ; 28.473 ; 27.674 ;
; CONFIG[5]    ; RAM_DATA[2]  ; 28.629 ; 27.731 ; 28.410 ; 27.564 ;
; CONFIG[5]    ; RAM_DATA[3]  ; 29.285 ; 28.454 ; 28.792 ; 28.287 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 28.975 ; 28.168 ; 28.525 ; 28.001 ;
; CONFIG[5]    ; RAM_DATA[5]  ; 29.781 ; 28.776 ; 29.288 ; 28.609 ;
; CONFIG[5]    ; RAM_DATA[6]  ; 28.340 ; 27.544 ; 27.942 ; 27.377 ;
; CONFIG[5]    ; RAM_DATA[7]  ; 27.980 ; 27.279 ; 27.813 ; 27.112 ;
; CONFIG[5]    ; RAM_DATA[8]  ; 29.725 ; 28.553 ; 29.232 ; 28.386 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 28.680 ; 27.993 ; 28.258 ; 27.826 ;
; CONFIG[5]    ; RAM_DATA[10] ; 26.991 ; 26.633 ; 26.579 ; 26.466 ;
; CONFIG[5]    ; RAM_DATA[11] ; 28.068 ; 27.567 ; 27.901 ; 27.400 ;
; CONFIG[5]    ; RAM_DATA[12] ; 28.693 ; 27.943 ; 28.526 ; 27.776 ;
; CONFIG[5]    ; RAM_DATA[13] ; 28.017 ; 27.353 ; 27.561 ; 26.919 ;
; CONFIG[5]    ; RAM_DATA[14] ; 29.930 ; 29.379 ; 29.588 ; 29.037 ;
; CONFIG[5]    ; RAM_DATA[15] ; 29.205 ; 28.741 ; 28.870 ; 28.406 ;
; CONFIG[6]    ; ADR[19]      ; 10.474 ;        ;        ; 10.370 ;
; DATA[0]      ; RAM_DATA[0]  ; 14.981 ;        ;        ; 14.908 ;
; DATA[1]      ; RAM_DATA[1]  ; 15.530 ;        ;        ; 15.205 ;
; DATA[2]      ; RAM_DATA[2]  ; 16.625 ;        ;        ; 16.218 ;
; DATA[3]      ; RAM_DATA[3]  ; 17.985 ;        ;        ; 17.746 ;
; DATA[4]      ; RAM_DATA[4]  ; 16.174 ;        ;        ; 15.865 ;
; DATA[5]      ; RAM_DATA[5]  ; 16.513 ;        ;        ; 15.980 ;
; DATA[6]      ; RAM_DATA[6]  ; 16.337 ;        ;        ; 16.119 ;
; DATA[7]      ; RAM_DATA[7]  ; 16.842 ;        ;        ; 16.558 ;
; DATA[8]      ; RAM_DATA[8]  ; 17.177 ;        ;        ; 16.879 ;
; DATA[9]      ; RAM_DATA[9]  ; 18.819 ;        ;        ; 18.212 ;
; DATA[10]     ; RAM_DATA[10] ; 15.877 ;        ;        ; 15.657 ;
; DATA[11]     ; RAM_DATA[11] ; 17.199 ;        ;        ; 16.655 ;
; DATA[12]     ; RAM_DATA[12] ; 18.176 ;        ;        ; 17.589 ;
; DATA[13]     ; RAM_DATA[13] ; 13.850 ;        ;        ; 13.620 ;
; DATA[14]     ; RAM_DATA[14] ; 14.126 ;        ;        ; 13.859 ;
; DATA[15]     ; RAM_DATA[15] ; 13.141 ;        ;        ; 13.030 ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 17.609 ;        ;        ; 17.253 ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 17.855 ;        ;        ; 17.196 ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 20.054 ;        ;        ; 19.098 ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 20.119 ;        ;        ; 19.455 ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 17.730 ;        ;        ; 17.117 ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 18.531 ;        ;        ; 17.644 ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 17.350 ;        ;        ; 16.912 ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 17.620 ;        ;        ; 17.081 ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 19.132 ;        ;        ; 18.487 ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 20.951 ;        ;        ; 20.030 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 16.685 ;        ;        ; 16.110 ;
; RAM_DATA[11] ; RAM_DATA[11] ; 17.030 ;        ;        ; 16.403 ;
; RAM_DATA[12] ; RAM_DATA[12] ; 15.718 ;        ;        ; 15.349 ;
; RAM_DATA[13] ; RAM_DATA[13] ; 14.584 ; 13.920 ; 14.780 ; 14.109 ;
; RAM_DATA[14] ; RAM_DATA[14] ; 17.134 ; 16.583 ; 17.346 ; 16.795 ;
; RAM_DATA[15] ; RAM_DATA[15] ; 20.269 ; 19.805 ; 20.203 ; 19.739 ;
; RESET_COREn  ; RAM_CKE      ; 4.787  ;        ;        ; 4.983  ;
; RESETn       ; KEYB_TxD     ; 10.422 ; 10.422 ; 10.638 ; 10.378 ;
+--------------+--------------+--------+--------+--------+--------+


+-----------------------------------------------------------------+
; Minimum Propagation Delay                                       ;
+--------------+--------------+--------+--------+--------+--------+
; Input Port   ; Output Port  ; RR     ; RF     ; FR     ; FF     ;
+--------------+--------------+--------+--------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 20.634 ; 19.725 ; 20.953 ; 19.981 ;
; CONFIG[1]    ; RAM_DATA[12] ; 11.535 ; 11.477 ; 12.103 ; 11.343 ;
; CONFIG[1]    ; RAM_DATA[13] ; 11.142 ; 11.121 ; 11.640 ; 11.076 ;
; CONFIG[1]    ; RAM_DATA[14] ; 10.766 ; 10.550 ; 11.072 ; 10.720 ;
; CONFIG[1]    ; RAM_DATA[15] ; 10.933 ; 11.970 ; 12.554 ; 10.825 ;
; CONFIG[2]    ; RAM_DATA[7]  ; 20.285 ; 19.384 ; 20.597 ; 19.623 ;
; CONFIG[2]    ; RAM_DATA[12] ; 11.197 ; 11.139 ; 11.821 ; 11.061 ;
; CONFIG[2]    ; RAM_DATA[13] ; 10.804 ; 10.783 ; 11.358 ; 10.794 ;
; CONFIG[2]    ; RAM_DATA[14] ; 10.428 ; 10.212 ; 10.790 ; 10.438 ;
; CONFIG[2]    ; RAM_DATA[15] ; 10.595 ; 11.632 ; 12.272 ; 10.543 ;
; CONFIG[3]    ; ADR[16]      ; 17.343 ; 16.912 ; 17.412 ; 17.026 ;
; CONFIG[3]    ; ADR[17]      ; 16.686 ; 16.089 ; 16.657 ; 16.416 ;
; CONFIG[3]    ; ADR[18]      ; 13.498 ; 20.285 ; 20.424 ; 13.077 ;
; CONFIG[3]    ; ADR[22]      ; 10.815 ;        ;        ; 10.842 ;
; CONFIG[3]    ; FLASH_CEn    ; 16.107 ; 17.680 ; 17.773 ; 16.196 ;
; CONFIG[3]    ; FLASH_OEn    ; 18.250 ; 19.527 ; 19.916 ; 18.043 ;
; CONFIG[3]    ; RAM_BA[1]    ; 16.742 ; 14.691 ; 15.197 ; 16.127 ;
; CONFIG[3]    ; RAM_CASn     ; 17.606 ; 17.504 ; 17.805 ; 17.248 ;
; CONFIG[3]    ; RAM_DATA[0]  ; 18.531 ; 17.347 ; 18.051 ; 18.129 ;
; CONFIG[3]    ; RAM_DATA[1]  ; 18.400 ; 17.624 ; 18.551 ; 17.992 ;
; CONFIG[3]    ; RAM_DATA[2]  ; 19.641 ; 18.404 ; 19.315 ; 19.081 ;
; CONFIG[3]    ; RAM_DATA[3]  ; 20.461 ; 18.711 ; 19.454 ; 20.038 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 19.108 ; 17.905 ; 18.706 ; 18.700 ;
; CONFIG[3]    ; RAM_DATA[5]  ; 19.445 ; 18.317 ; 19.347 ; 18.842 ;
; CONFIG[3]    ; RAM_DATA[6]  ; 19.228 ; 18.399 ; 19.134 ; 19.037 ;
; CONFIG[3]    ; RAM_DATA[7]  ; 18.606 ; 17.740 ; 18.465 ; 18.373 ;
; CONFIG[3]    ; RAM_DATA[8]  ; 19.762 ; 18.533 ; 19.471 ; 19.318 ;
; CONFIG[3]    ; RAM_DATA[9]  ; 19.527 ; 18.595 ; 19.366 ; 18.791 ;
; CONFIG[3]    ; RAM_DATA[10] ; 18.283 ; 17.307 ; 18.076 ; 17.914 ;
; CONFIG[3]    ; RAM_DATA[11] ; 18.413 ; 17.427 ; 18.169 ; 18.100 ;
; CONFIG[3]    ; RAM_DATA[12] ; 18.770 ; 17.414 ; 18.208 ; 18.306 ;
; CONFIG[3]    ; RAM_DATA[13] ; 16.187 ; 15.841 ; 16.483 ; 16.015 ;
; CONFIG[3]    ; RAM_DATA[14] ; 18.181 ; 17.701 ; 18.615 ; 18.094 ;
; CONFIG[3]    ; RAM_DATA[15] ; 16.869 ; 16.475 ; 17.150 ; 16.713 ;
; CONFIG[4]    ; ADR[16]      ; 17.249 ; 16.818 ; 17.172 ; 16.786 ;
; CONFIG[4]    ; ADR[17]      ; 16.592 ; 15.995 ; 16.417 ; 16.176 ;
; CONFIG[4]    ; ADR[18]      ; 13.531 ; 20.210 ; 20.188 ; 13.022 ;
; CONFIG[4]    ; ADR[21]      ; 11.292 ;        ;        ; 11.209 ;
; CONFIG[4]    ; FLASH_CEn    ; 16.140 ; 17.713 ; 17.718 ; 16.141 ;
; CONFIG[4]    ; FLASH_OEn    ; 18.283 ; 19.560 ; 19.861 ; 17.988 ;
; CONFIG[4]    ; RAM_BA[1]    ; 16.667 ; 14.597 ; 14.957 ; 15.891 ;
; CONFIG[4]    ; RAM_CASn     ; 17.512 ; 17.426 ; 17.568 ; 17.008 ;
; CONFIG[4]    ; RAM_DATA[0]  ; 18.467 ; 17.253 ; 17.811 ; 17.889 ;
; CONFIG[4]    ; RAM_DATA[1]  ; 18.433 ; 17.530 ; 18.311 ; 17.937 ;
; CONFIG[4]    ; RAM_DATA[2]  ; 19.587 ; 18.310 ; 19.075 ; 19.011 ;
; CONFIG[4]    ; RAM_DATA[3]  ; 20.494 ; 18.617 ; 19.214 ; 19.983 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 19.141 ; 17.811 ; 18.466 ; 18.645 ;
; CONFIG[4]    ; RAM_DATA[5]  ; 19.351 ; 18.223 ; 19.107 ; 18.602 ;
; CONFIG[4]    ; RAM_DATA[6]  ; 19.134 ; 18.305 ; 18.894 ; 18.797 ;
; CONFIG[4]    ; RAM_DATA[7]  ; 18.512 ; 17.646 ; 18.225 ; 18.133 ;
; CONFIG[4]    ; RAM_DATA[8]  ; 19.795 ; 18.439 ; 19.231 ; 19.263 ;
; CONFIG[4]    ; RAM_DATA[9]  ; 19.560 ; 18.501 ; 19.126 ; 18.736 ;
; CONFIG[4]    ; RAM_DATA[10] ; 18.281 ; 17.213 ; 17.836 ; 17.674 ;
; CONFIG[4]    ; RAM_DATA[11] ; 18.319 ; 17.333 ; 17.929 ; 17.860 ;
; CONFIG[4]    ; RAM_DATA[12] ; 18.803 ; 17.320 ; 17.968 ; 18.251 ;
; CONFIG[4]    ; RAM_DATA[13] ; 16.220 ; 15.874 ; 16.428 ; 15.960 ;
; CONFIG[4]    ; RAM_DATA[14] ; 18.214 ; 17.734 ; 18.560 ; 18.039 ;
; CONFIG[4]    ; RAM_DATA[15] ; 16.902 ; 16.508 ; 17.095 ; 16.658 ;
; CONFIG[5]    ; ADR[16]      ; 17.499 ; 17.068 ; 17.414 ; 17.028 ;
; CONFIG[5]    ; ADR[17]      ; 16.842 ; 16.245 ; 16.659 ; 16.418 ;
; CONFIG[5]    ; ADR[18]      ; 18.523 ; 20.501 ; 20.474 ; 18.359 ;
; CONFIG[5]    ; ADR[20]      ; 9.766  ;        ;        ; 9.755  ;
; CONFIG[5]    ; FLASH_CEn    ; 17.943 ; 18.943 ; 18.894 ; 18.032 ;
; CONFIG[5]    ; FLASH_OEn    ; 20.086 ; 20.790 ; 21.037 ; 19.879 ;
; CONFIG[5]    ; RAM_BA[1]    ; 16.958 ; 14.847 ; 15.199 ; 16.177 ;
; CONFIG[5]    ; RAM_CASn     ; 17.762 ; 17.720 ; 17.857 ; 17.250 ;
; CONFIG[5]    ; RAM_DATA[0]  ; 18.717 ; 17.503 ; 18.053 ; 18.131 ;
; CONFIG[5]    ; RAM_DATA[1]  ; 19.649 ; 17.780 ; 18.553 ; 19.099 ;
; CONFIG[5]    ; RAM_DATA[2]  ; 19.837 ; 18.560 ; 19.317 ; 19.253 ;
; CONFIG[5]    ; RAM_DATA[3]  ; 20.858 ; 18.867 ; 19.456 ; 20.349 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 19.454 ; 18.061 ; 18.708 ; 18.891 ;
; CONFIG[5]    ; RAM_DATA[5]  ; 19.601 ; 18.473 ; 19.349 ; 18.844 ;
; CONFIG[5]    ; RAM_DATA[6]  ; 19.384 ; 18.555 ; 19.136 ; 19.039 ;
; CONFIG[5]    ; RAM_DATA[7]  ; 18.762 ; 17.896 ; 18.467 ; 18.375 ;
; CONFIG[5]    ; RAM_DATA[8]  ; 20.939 ; 18.689 ; 19.473 ; 20.195 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 20.065 ; 18.751 ; 19.368 ; 19.286 ;
; CONFIG[5]    ; RAM_DATA[10] ; 18.531 ; 17.463 ; 18.078 ; 17.916 ;
; CONFIG[5]    ; RAM_DATA[11] ; 18.569 ; 17.583 ; 18.171 ; 18.102 ;
; CONFIG[5]    ; RAM_DATA[12] ; 19.217 ; 17.570 ; 18.210 ; 18.638 ;
; CONFIG[5]    ; RAM_DATA[13] ; 17.716 ; 17.370 ; 17.756 ; 17.288 ;
; CONFIG[5]    ; RAM_DATA[14] ; 19.573 ; 19.058 ; 19.675 ; 19.160 ;
; CONFIG[5]    ; RAM_DATA[15] ; 18.398 ; 18.004 ; 18.423 ; 17.986 ;
; CONFIG[6]    ; ADR[19]      ; 10.157 ;        ;        ; 10.045 ;
; DATA[0]      ; RAM_DATA[0]  ; 12.088 ;        ;        ; 11.929 ;
; DATA[1]      ; RAM_DATA[1]  ; 11.915 ;        ;        ; 11.776 ;
; DATA[2]      ; RAM_DATA[2]  ; 13.369 ;        ;        ; 13.124 ;
; DATA[3]      ; RAM_DATA[3]  ; 13.637 ;        ;        ; 13.449 ;
; DATA[4]      ; RAM_DATA[4]  ; 12.794 ;        ;        ; 12.572 ;
; DATA[5]      ; RAM_DATA[5]  ; 13.426 ;        ;        ; 13.053 ;
; DATA[6]      ; RAM_DATA[6]  ; 12.873 ;        ;        ; 12.928 ;
; DATA[7]      ; RAM_DATA[7]  ; 12.289 ;        ;        ; 12.291 ;
; DATA[8]      ; RAM_DATA[8]  ; 12.811 ;        ;        ; 12.644 ;
; DATA[9]      ; RAM_DATA[9]  ; 13.469 ;        ;        ; 13.367 ;
; DATA[10]     ; RAM_DATA[10] ; 11.954 ;        ;        ; 11.941 ;
; DATA[11]     ; RAM_DATA[11] ; 12.098 ;        ;        ; 11.966 ;
; DATA[12]     ; RAM_DATA[12] ; 15.390 ;        ;        ; 15.036 ;
; DATA[13]     ; RAM_DATA[13] ; 12.483 ;        ;        ; 12.376 ;
; DATA[14]     ; RAM_DATA[14] ; 13.560 ;        ;        ; 13.274 ;
; DATA[15]     ; RAM_DATA[15] ; 12.700 ;        ;        ; 12.575 ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 16.985 ;        ;        ; 16.591 ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 17.224 ;        ;        ; 16.565 ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 19.316 ;        ;        ; 18.356 ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 19.333 ;        ;        ; 18.658 ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 17.112 ;        ;        ; 16.500 ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 17.954 ;        ;        ; 17.068 ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 16.742 ;        ;        ; 16.294 ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 16.996 ;        ;        ; 16.466 ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 18.375 ;        ;        ; 17.710 ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 20.119 ;        ;        ; 19.194 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 16.103 ;        ;        ; 15.531 ;
; RAM_DATA[11] ; RAM_DATA[11] ; 16.418 ;        ;        ; 15.784 ;
; RAM_DATA[12] ; RAM_DATA[12] ; 15.132 ;        ;        ; 14.748 ;
; RAM_DATA[13] ; RAM_DATA[13] ; 14.121 ; 13.478 ; 14.307 ; 13.656 ;
; RAM_DATA[14] ; RAM_DATA[14] ; 16.263 ; 15.748 ; 16.455 ; 15.940 ;
; RAM_DATA[15] ; RAM_DATA[15] ; 19.276 ; 18.800 ; 19.168 ; 18.692 ;
; RESET_COREn  ; RAM_CKE      ; 4.726  ;        ;        ; 4.914  ;
; RESETn       ; KEYB_TxD     ; 9.610  ; 9.656  ; 9.816  ; 9.816  ;
+--------------+--------------+--------+--------+--------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 10.776 ; 10.776 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 10.776 ; 10.776 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 11.431 ; 11.431 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 11.431 ; 11.431 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 11.431 ; 11.431 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 11.648 ; 11.648 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 11.648 ; 11.648 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 11.866 ; 11.866 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 11.866 ; 11.866 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 11.802 ; 11.802 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 11.802 ; 11.802 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 11.812 ; 11.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 11.812 ; 11.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 11.812 ; 11.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 11.812 ; 11.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 11.835 ; 11.835 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 11.845 ; 11.845 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 7.081  ; 7.081  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 6.858  ; 6.858  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 10.619 ; 10.619 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 9.913  ; 9.913  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 9.922  ; 9.922  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 20.248 ; 20.248 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 20.598 ; 20.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 20.598 ; 20.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 20.248 ; 20.248 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 20.636 ; 20.636 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 20.636 ; 20.636 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 20.636 ; 20.636 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 20.649 ; 20.649 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 20.639 ; 20.639 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 20.657 ; 20.657 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 20.657 ; 20.657 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 21.050 ; 21.050 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 21.028 ; 21.028 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 21.040 ; 21.040 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 21.040 ; 21.040 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 21.057 ; 21.057 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 21.442 ; 21.442 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 10.040 ; 10.040 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 10.040 ; 10.040 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 9.524  ; 9.524  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 7.318  ; 7.318  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 17.506 ; 17.506 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 17.856 ; 17.856 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 17.856 ; 17.856 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 17.506 ; 17.506 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 17.894 ; 17.894 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 17.894 ; 17.894 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 17.894 ; 17.894 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 17.907 ; 17.907 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 17.897 ; 17.897 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 17.915 ; 17.915 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 17.915 ; 17.915 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 18.308 ; 18.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 18.286 ; 18.286 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 18.298 ; 18.298 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 18.298 ; 18.298 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 18.315 ; 18.315 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 18.700 ; 18.700 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 13.039 ; 13.039 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.389 ; 13.389 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.389 ; 13.389 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 13.039 ; 13.039 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.427 ; 13.427 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 13.427 ; 13.427 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.427 ; 13.427 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.440 ; 13.440 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 13.430 ; 13.430 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 13.448 ; 13.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 13.448 ; 13.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 13.841 ; 13.841 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 13.819 ; 13.819 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 13.831 ; 13.831 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 13.831 ; 13.831 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 13.848 ; 13.848 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 14.233 ; 14.233 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.784 ; 26.784 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 27.134 ; 27.134 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 27.134 ; 27.134 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 26.784 ; 26.784 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 27.172 ; 27.172 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 27.172 ; 27.172 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 27.172 ; 27.172 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 27.185 ; 27.185 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 27.175 ; 27.175 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 27.193 ; 27.193 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 27.193 ; 27.193 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 27.586 ; 27.586 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 27.564 ; 27.564 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 27.576 ; 27.576 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 27.576 ; 27.576 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 27.593 ; 27.593 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 27.978 ; 27.978 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 12.303 ; 12.303 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 12.312 ; 12.312 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 12.430 ; 12.430 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 12.430 ; 12.430 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 11.914 ; 11.914 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 7.270  ; 7.316  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 7.270  ; 7.316  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 7.899  ; 7.945  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 7.899  ; 7.945  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 7.899  ; 7.945  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 8.108  ; 8.154  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 8.108  ; 8.154  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 8.317  ; 8.363  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 8.317  ; 8.363  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 8.256  ; 8.302  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 8.256  ; 8.302  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 8.266  ; 8.312  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 8.266  ; 8.312  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 8.266  ; 8.312  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 8.266  ; 8.312  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 8.288  ; 8.334  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 8.298  ; 8.344  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 5.232  ; 5.278  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.708  ; 5.737  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 7.460  ; 7.506  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 7.520  ; 7.549  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 7.529  ; 7.558  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.007  ; 8.036  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.343  ; 8.372  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.343  ; 8.372  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.007  ; 8.036  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.379  ; 8.408  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.379  ; 8.408  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.379  ; 8.408  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.391  ; 8.420  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.381  ; 8.410  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.399  ; 8.428  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.399  ; 8.428  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.775  ; 8.804  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.755  ; 8.784  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.766  ; 8.795  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.766  ; 8.795  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.782  ; 8.811  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.152  ; 9.181  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 7.615  ; 7.661  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 7.615  ; 7.661  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 7.146  ; 7.175  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 6.150  ; 6.179  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.876  ; 7.905  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.212  ; 8.241  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.212  ; 8.241  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.876  ; 7.905  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.248  ; 8.277  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.248  ; 8.277  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.248  ; 8.277  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.260  ; 8.289  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.250  ; 8.279  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.268  ; 8.297  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.268  ; 8.297  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.644  ; 8.673  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.624  ; 8.653  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.635  ; 8.664  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.635  ; 8.664  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.651  ; 8.680  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.021  ; 9.050  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 6.085  ; 6.114  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.421  ; 6.450  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 6.421  ; 6.450  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 6.085  ; 6.114  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.457  ; 6.486  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.457  ; 6.486  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.457  ; 6.486  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.469  ; 6.498  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.459  ; 6.488  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.477  ; 6.506  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.477  ; 6.506  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 6.853  ; 6.882  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 6.833  ; 6.862  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.844  ; 6.873  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.844  ; 6.873  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.860  ; 6.889  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.230  ; 7.259  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.624  ; 8.653  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.960  ; 8.989  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.960  ; 8.989  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.624  ; 8.653  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.996  ; 9.025  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.996  ; 9.025  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.996  ; 9.025  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 9.008  ; 9.037  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.998  ; 9.027  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 9.016  ; 9.045  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.016  ; 9.045  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.392  ; 9.421  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.372  ; 9.401  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.383  ; 9.412  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.383  ; 9.412  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 9.399  ; 9.428  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.769  ; 9.798  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 10.936 ; 10.965 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 10.945 ; 10.974 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 11.031 ; 11.077 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 11.031 ; 11.077 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 10.562 ; 10.591 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 10.115    ; 10.375    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 10.115    ; 10.375    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 10.673    ; 10.933    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 10.673    ; 10.933    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 10.673    ; 10.933    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 10.860    ; 11.120    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 10.860    ; 11.120    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 11.156    ; 11.416    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 11.156    ; 11.416    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 11.079    ; 11.339    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 11.079    ; 11.339    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 11.089    ; 11.349    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 11.099    ; 11.359    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 11.099    ; 11.359    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 11.099    ; 11.359    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 11.112    ; 11.372    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 11.122    ; 11.382    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 6.637     ; 6.897     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 6.412     ; 6.652     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 10.403    ; 10.663    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 9.559     ; 9.799     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 9.565     ; 9.805     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 19.731    ; 19.971    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 20.042    ; 20.282    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 20.042    ; 20.282    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 19.731    ; 19.971    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 20.089    ; 20.329    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 20.089    ; 20.329    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 20.089    ; 20.329    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 20.099    ; 20.339    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 20.089    ; 20.329    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 20.121    ; 20.361    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 20.121    ; 20.361    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 20.467    ; 20.707    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 20.459    ; 20.699    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 20.468    ; 20.708    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 20.468    ; 20.708    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 20.501    ; 20.741    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 20.819    ; 21.059    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 9.725     ; 9.985     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 9.725     ; 9.985     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 9.201     ; 9.441     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 6.822     ; 7.062     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 13.917    ; 14.157    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 14.228    ; 14.468    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 14.228    ; 14.468    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 13.917    ; 14.157    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 14.275    ; 14.515    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 14.275    ; 14.515    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 14.275    ; 14.515    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 14.285    ; 14.525    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 14.275    ; 14.515    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 14.307    ; 14.547    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 14.307    ; 14.547    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 14.653    ; 14.893    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 14.645    ; 14.885    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 14.654    ; 14.894    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 14.654    ; 14.894    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 14.687    ; 14.927    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 15.005    ; 15.245    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 12.754    ; 12.994    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.065    ; 13.305    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.065    ; 13.305    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.754    ; 12.994    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.112    ; 13.352    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 13.112    ; 13.352    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.112    ; 13.352    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.122    ; 13.362    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 13.112    ; 13.352    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 13.144    ; 13.384    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 13.144    ; 13.384    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 13.490    ; 13.730    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 13.482    ; 13.722    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 13.491    ; 13.731    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 13.491    ; 13.731    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 13.524    ; 13.764    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 13.842    ; 14.082    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.312    ; 26.552    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 26.623    ; 26.863    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 26.623    ; 26.863    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 26.312    ; 26.552    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 26.670    ; 26.910    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 26.670    ; 26.910    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 26.670    ; 26.910    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 26.680    ; 26.920    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 26.670    ; 26.910    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 26.702    ; 26.942    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 26.702    ; 26.942    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 27.048    ; 27.288    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 27.040    ; 27.280    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 27.049    ; 27.289    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 27.049    ; 27.289    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 27.082    ; 27.322    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 27.400    ; 27.640    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 11.383    ; 11.623    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 11.389    ; 11.629    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 11.549    ; 11.809    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 11.549    ; 11.809    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 11.025    ; 11.265    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 6.713     ; 6.713     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 6.713     ; 6.713     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 7.249     ; 7.249     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 7.249     ; 7.249     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 7.249     ; 7.249     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 7.429     ; 7.429     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 7.429     ; 7.429     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 7.713     ; 7.713     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 7.713     ; 7.713     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 7.640     ; 7.640     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 7.640     ; 7.640     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 7.650     ; 7.650     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 7.659     ; 7.659     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 7.659     ; 7.659     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 7.659     ; 7.659     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 7.671     ; 7.671     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 7.681     ; 7.681     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 4.986     ; 4.986     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.510     ; 5.510     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 7.470     ; 7.470     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 7.234     ; 7.234     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 7.241     ; 7.241     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.843     ; 7.843     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.141     ; 8.141     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.141     ; 8.141     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.843     ; 7.843     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.186     ; 8.186     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.186     ; 8.186     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.186     ; 8.186     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.195     ; 8.195     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.185     ; 8.185     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.216     ; 8.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.216     ; 8.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.548     ; 8.548     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.540     ; 8.540     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.549     ; 8.549     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.549     ; 8.549     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.580     ; 8.580     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.886     ; 8.886     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 7.387     ; 7.387     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 7.387     ; 7.387     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 6.891     ; 6.891     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 5.904     ; 5.904     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.720     ; 7.720     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.018     ; 8.018     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.018     ; 8.018     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.720     ; 7.720     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.063     ; 8.063     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.063     ; 8.063     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.063     ; 8.063     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.072     ; 8.072     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.062     ; 8.062     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.093     ; 8.093     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.093     ; 8.093     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.425     ; 8.425     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.417     ; 8.417     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.426     ; 8.426     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.426     ; 8.426     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.457     ; 8.457     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.763     ; 8.763     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 5.936     ; 5.936     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.234     ; 6.234     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 6.234     ; 6.234     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.936     ; 5.936     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.279     ; 6.279     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.279     ; 6.279     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.279     ; 6.279     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.288     ; 6.288     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.278     ; 6.278     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.309     ; 6.309     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.309     ; 6.309     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 6.641     ; 6.641     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 6.633     ; 6.633     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.642     ; 6.642     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.642     ; 6.642     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.673     ; 6.673     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 6.979     ; 6.979     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.435     ; 8.435     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.733     ; 8.733     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.733     ; 8.733     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.435     ; 8.435     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.778     ; 8.778     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.778     ; 8.778     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.778     ; 8.778     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.787     ; 8.787     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.777     ; 8.777     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.808     ; 8.808     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.808     ; 8.808     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.140     ; 9.140     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.132     ; 9.132     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.141     ; 9.141     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.141     ; 9.141     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 9.172     ; 9.172     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.478     ; 9.478     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 10.282    ; 10.282    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 10.289    ; 10.289    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 10.435    ; 10.435    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 10.435    ; 10.435    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 9.939     ; 9.939     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                                                      ;
+-------------+-----------------+--------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+
; Fmax        ; Restricted Fmax ; Clock Name                                                                                             ; Note                                                          ;
+-------------+-----------------+--------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+
; 16.64 MHz   ; 16.64 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;                                                               ;
; 23.42 MHz   ; 23.42 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;                                                               ;
; 46.86 MHz   ; 46.86 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;                                                               ;
; 73.69 MHz   ; 73.69 MHz       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;                                                               ;
; 411.02 MHz  ; 250.0 MHz       ; CLK_PLL1                                                                                               ; limit due to minimum period restriction (max I/O toggle rate) ;
; 419.99 MHz  ; 402.09 MHz      ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; limit due to minimum period restriction (tmin)                ;
; 494.8 MHz   ; 402.09 MHz      ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; limit due to minimum period restriction (tmin)                ;
; 1131.22 MHz ; 402.09 MHz      ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; limit due to minimum period restriction (tmin)                ;
+-------------+-----------------+--------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                                              ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; -3.440 ; -6.498        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.403  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 1.133  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 1.209  ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 23.009 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 38.178 ; 0.000         ;
; CLK_PLL1                                                                                               ; 60.067 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 60.479 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                                              ;
+--------------------------------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                                                  ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+-------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.076 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.383 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.383 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.384 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.384 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.403 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.417 ; 0.000         ;
; CLK_PLL1                                                                                               ; 0.449 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                                           ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 22.313 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 22.339 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 28.005 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                                            ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1.530  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 3.671  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 33.125 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                                                ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 12.386 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.268 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 19.223 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 20.480 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 30.819 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 30.888 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 30.895 ; 0.000         ;
; CLK_PLL1                                                                                               ; 31.007 ; 0.000         ;
; CLK_PLL2                                                                                               ; 31.082 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------------------------------------+---------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                      ; To Node                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------+---------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.440 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 19.189     ;
; -3.233 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.982     ;
; -3.210 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.960     ;
; -3.132 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.882     ;
; -3.111 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.860     ;
; -3.058 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.807     ;
; -2.985 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.734     ;
; -2.955 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.705     ;
; -2.853 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.602     ;
; -2.851 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.600     ;
; -2.828 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.578     ;
; -2.824 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.574     ;
; -2.750 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.500     ;
; -2.729 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.478     ;
; -2.661 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.410     ;
; -2.603 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.352     ;
; -2.597 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.346     ;
; -2.573 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.323     ;
; -2.517 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.267     ;
; -2.471 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]     ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.220     ;
; -2.449 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.199     ;
; -2.442 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.192     ;
; -2.415 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.164     ;
; -2.365 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 18.097     ;
; -2.321 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[16]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 18.071     ;
; -2.279 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 18.028     ;
; -2.273 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[21]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 18.005     ;
; -2.222 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[19]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.954     ;
; -2.215 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 17.964     ;
; -2.208 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[18]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.941     ;
; -2.136 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[13] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 17.469     ;
; -2.135 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 17.885     ;
; -2.067 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 17.817     ;
; -2.054 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[11] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 17.387     ;
; -2.042 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[20]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.775     ;
; -2.033 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.122      ; 17.782     ;
; -2.023 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[12] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 17.356     ;
; -1.983 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[17]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.715     ;
; -1.939 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[16]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.123      ; 17.689     ;
; -1.935 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[23]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.667     ;
; -1.914 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[10] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 17.247     ;
; -1.891 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[21]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.623     ;
; -1.840 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[19]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.572     ;
; -1.826 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[18]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.559     ;
; -1.754 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[13] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 17.087     ;
; -1.719 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[22]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.452     ;
; -1.672 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[11] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 17.005     ;
; -1.660 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[20]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.393     ;
; -1.655 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[15] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.988     ;
; -1.652 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[8]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.985     ;
; -1.641 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[12] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.974     ;
; -1.636 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[24]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.368     ;
; -1.626 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[14] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.959     ;
; -1.594 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[18] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.911     ;
; -1.566 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[9]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.899     ;
; -1.553 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[23]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.285     ;
; -1.534 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[17] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.851     ;
; -1.532 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[10] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.865     ;
; -1.505 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[16] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.822     ;
; -1.478 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[7]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.811     ;
; -1.471 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[26] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.788     ;
; -1.435 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[25] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.752     ;
; -1.422 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.739     ;
; -1.399 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.716     ;
; -1.392 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[6]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.725     ;
; -1.366 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[29]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 17.098     ;
; -1.361 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[28]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.094     ;
; -1.355 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[3]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.688     ;
; -1.337 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[22]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.070     ;
; -1.324 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.057     ;
; -1.318 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 17.051     ;
; -1.286 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[5]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.619     ;
; -1.283 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[4]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.616     ;
; -1.273 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[15] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.606     ;
; -1.270 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[8]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.603     ;
; -1.254 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[24]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 16.986     ;
; -1.244 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[14] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.577     ;
; -1.228 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[27]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 16.961     ;
; -1.212 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[18] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.529     ;
; -1.190 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[19] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.104      ; 16.921     ;
; -1.184 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[9]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.517     ;
; -1.152 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[17] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.469     ;
; -1.123 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[16] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.440     ;
; -1.096 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[7]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.429     ;
; -1.089 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[26] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.406     ;
; -1.070 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[2]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.120      ; 16.817     ;
; -1.053 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[25] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.370     ;
; -1.040 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[20] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.357     ;
; -1.017 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[21] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.334     ;
; -1.010 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[6]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.343     ;
; -0.984 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[29]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 16.716     ;
; -0.979 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[24] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.310     ; 16.296     ;
; -0.979 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[28]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 16.712     ;
; -0.973 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[3]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.306     ;
; -0.947 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[22] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.104      ; 16.678     ;
; -0.942 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[26]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 16.675     ;
; -0.936 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[25]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 16.669     ;
; -0.904 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[5]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.237     ;
; -0.901 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_EFF_I[4]  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; -0.294     ; 16.234     ;
; -0.846 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[27]    ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 16.579     ;
+--------+--------------------------------------------------------------------------------+---------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                          ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; CLK_24576                                                                   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL1_S        ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1.970        ; -0.415     ; 1.014      ;
; 2.801 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 28.575     ;
; 2.940 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.487     ;
; 2.940 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.487     ;
; 2.956 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 28.434     ;
; 2.984 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 28.373     ;
; 2.988 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 28.369     ;
; 3.008 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 28.368     ;
; 3.031 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.125      ; 28.346     ;
; 3.109 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.125      ; 28.268     ;
; 3.130 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 28.246     ;
; 3.147 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.280     ;
; 3.147 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.280     ;
; 3.159 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 28.207     ;
; 3.160 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 28.206     ;
; 3.163 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 28.227     ;
; 3.170 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 28.258     ;
; 3.170 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 28.258     ;
; 3.186 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.139      ; 28.205     ;
; 3.191 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 28.166     ;
; 3.195 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 28.162     ;
; 3.214 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 28.144     ;
; 3.218 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 28.140     ;
; 3.248 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 28.180     ;
; 3.248 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 28.180     ;
; 3.256 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 28.120     ;
; 3.264 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.139      ; 28.127     ;
; 3.269 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.158     ;
; 3.269 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.158     ;
; 3.285 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 28.105     ;
; 3.286 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.125      ; 28.091     ;
; 3.292 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 28.066     ;
; 3.296 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 28.062     ;
; 3.313 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 28.044     ;
; 3.317 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 28.040     ;
; 3.366 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 28.000     ;
; 3.367 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.999     ;
; 3.388 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 27.988     ;
; 3.389 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.978     ;
; 3.390 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.977     ;
; 3.395 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.032     ;
; 3.395 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 28.032     ;
; 3.411 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 27.979     ;
; 3.417 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.125      ; 27.960     ;
; 3.425 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 28.003     ;
; 3.425 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 28.003     ;
; 3.439 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.918     ;
; 3.441 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.139      ; 27.950     ;
; 3.443 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.914     ;
; 3.467 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.900     ;
; 3.468 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.899     ;
; 3.469 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 27.889     ;
; 3.473 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 27.885     ;
; 3.477 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.465     ; 11.685     ;
; 3.488 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.878     ;
; 3.489 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.877     ;
; 3.527 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 27.900     ;
; 3.527 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 27.900     ;
; 3.543 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 27.847     ;
; 3.556 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 27.872     ;
; 3.556 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 27.872     ;
; 3.571 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.786     ;
; 3.572 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.139      ; 27.819     ;
; 3.574 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.162      ; 27.840     ;
; 3.575 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.782     ;
; 3.580 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 27.796     ;
; 3.600 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 27.758     ;
; 3.604 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.106      ; 27.754     ;
; 3.614 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.752     ;
; 3.615 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.751     ;
; 3.644 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 27.732     ;
; 3.644 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.723     ;
; 3.645 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.722     ;
; 3.681 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.149      ; 27.720     ;
; 3.683 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.149      ; 27.718     ;
; 3.719 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 27.708     ;
; 3.719 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 27.708     ;
; 3.724 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.125      ; 27.653     ;
; 3.735 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 27.655     ;
; 3.736 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 27.694     ;
; 3.736 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 27.694     ;
; 3.746 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.620     ;
; 3.747 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.114      ; 27.619     ;
; 3.763 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.594     ;
; 3.767 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.590     ;
; 3.775 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.592     ;
; 3.776 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.115      ; 27.591     ;
; 3.781 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.162      ; 27.633     ;
; 3.783 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 27.644     ;
; 3.783 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.175      ; 27.644     ;
; 3.792 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[14] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.125      ; 27.585     ;
; 3.799 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 27.591     ;
; 3.804 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.163      ; 27.611     ;
; 3.826 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[15] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.124      ; 27.550     ;
; 3.827 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.530     ;
; 3.831 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.105      ; 27.526     ;
; 3.850 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 27.540     ;
; 3.863 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 27.565     ;
; 3.863 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.176      ; 27.565     ;
; 3.871 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|FIFO_SYS_RD    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.465     ; 11.291     ;
+-------+-----------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                                                                                                                                                     ;
+-------+-------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                             ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.133 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.593      ;
; 1.181 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.545      ;
; 1.190 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.536      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.197 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.077      ;
; 1.238 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.488      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.254 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 9.020      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.298 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.977      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.355 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.920      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[21]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[19]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[18]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[20]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[23]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.366 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[22]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.908      ;
; 1.374 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.352      ;
; 1.378 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.897      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.395 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.881      ;
; 1.422 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.304      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[21]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[19]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[18]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[20]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[23]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.423 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[22]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.851      ;
; 1.430 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.296      ;
; 1.435 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.143     ; 8.840      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.438 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.836      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.452 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.142     ; 8.824      ;
; 1.458 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.268      ;
; 1.469 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.257      ;
; 1.478 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.248      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.780      ;
; 1.506 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.220      ;
; 1.517 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.308      ; 9.209      ;
; 1.522 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.752      ;
; 1.522 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.752      ;
; 1.522 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.752      ;
; 1.522 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.752      ;
; 1.522 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.752      ;
; 1.522 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.144     ; 8.752      ;
+-------+-------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                               ;
+-------+-----------------------------------------------------------------------------+-------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                   ; To Node                                                           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------+-------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.209 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.902     ;
; 1.337 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.771     ;
; 1.412 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.209      ; 30.049     ;
; 1.416 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.695     ;
; 1.439 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.140     ; 29.673     ;
; 1.510 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.598     ;
; 1.515 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.223      ; 29.960     ;
; 1.517 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.140     ; 29.595     ;
; 1.538 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.573     ;
; 1.544 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.564     ;
; 1.567 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.534     ;
; 1.567 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.542     ;
; 1.594 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.507     ;
; 1.619 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.209      ; 29.842     ;
; 1.642 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.210      ; 29.820     ;
; 1.645 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.464     ;
; 1.664 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.447     ;
; 1.666 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.442     ;
; 1.675 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.782     ;
; 1.694 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.140     ; 29.418     ;
; 1.717 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.391     ;
; 1.720 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.210      ; 29.742     ;
; 1.722 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.223      ; 29.753     ;
; 1.740 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.369     ;
; 1.741 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.209      ; 29.720     ;
; 1.745 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.224      ; 29.731     ;
; 1.774 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.327     ;
; 1.792 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.316     ;
; 1.796 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.315     ;
; 1.797 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 29.305     ;
; 1.801 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.300     ;
; 1.812 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.645     ;
; 1.818 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.288      ; 29.722     ;
; 1.818 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.291     ;
; 1.822 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.287     ;
; 1.823 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.224      ; 29.653     ;
; 1.824 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.139     ; 29.289     ;
; 1.824 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 29.278     ;
; 1.825 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.140     ; 29.287     ;
; 1.839 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.269     ;
; 1.844 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.223      ; 29.631     ;
; 1.867 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.209      ; 29.594     ;
; 1.875 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 29.227     ;
; 1.882 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.575     ;
; 1.896 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.205     ;
; 1.897 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.210      ; 29.565     ;
; 1.902 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 29.200     ;
; 1.905 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.206      ; 29.553     ;
; 1.920 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.181     ;
; 1.923 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.178     ;
; 1.924 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.184     ;
; 1.943 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 29.580     ;
; 1.953 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.156     ;
; 1.965 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.143     ;
; 1.970 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.223      ; 29.505     ;
; 1.983 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.206      ; 29.475     ;
; 1.988 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.123     ;
; 1.995 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 29.114     ;
; 1.999 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.209      ; 29.462     ;
; 2.000 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.224      ; 29.476     ;
; 2.004 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.453     ;
; 2.016 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[8]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.288      ; 29.524     ;
; 2.019 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.438     ;
; 2.022 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.079     ;
; 2.025 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.288      ; 29.515     ;
; 2.028 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.210      ; 29.434     ;
; 2.031 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.139     ; 29.082     ;
; 2.042 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.206      ; 29.416     ;
; 2.048 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.289      ; 29.493     ;
; 2.049 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 29.052     ;
; 2.052 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.141     ; 29.059     ;
; 2.052 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 29.050     ;
; 2.054 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.138     ; 29.060     ;
; 2.063 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.045     ;
; 2.079 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 29.023     ;
; 2.097 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 29.011     ;
; 2.102 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.223      ; 29.373     ;
; 2.114 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[27] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.142     ; 28.996     ;
; 2.116 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[11] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 28.992     ;
; 2.120 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.206      ; 29.338     ;
; 2.126 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.143     ; 28.983     ;
; 2.126 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.289      ; 29.415     ;
; 2.127 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.232      ; 29.357     ;
; 2.127 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 28.974     ;
; 2.130 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.327     ;
; 2.131 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.224      ; 29.345     ;
; 2.132 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[12] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.140     ; 28.980     ;
; 2.132 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.138     ; 28.982     ;
; 2.141 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.205      ; 29.316     ;
; 2.147 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.288      ; 29.393     ;
; 2.150 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.150     ; 28.952     ;
; 2.150 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.271      ; 29.373     ;
; 2.153 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.139     ; 28.960     ;
; 2.154 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 28.947     ;
; 2.157 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[12] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.288      ; 29.383     ;
; 2.160 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.206      ; 29.298     ;
; 2.173 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.272      ; 29.351     ;
; 2.176 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.225      ; 29.301     ;
; 2.180 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[13] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.144     ; 28.928     ;
; 2.181 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.151     ; 28.920     ;
+-------+-----------------------------------------------------------------------------+-------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                              ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 23.009 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 2.311      ;
; 23.091 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 2.229      ;
; 23.099 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 2.221      ;
; 23.605 ; CLK_24576             ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 1.715      ;
; 23.650 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 1.670      ;
; 23.654 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 1.666      ;
; 24.173 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 1.147      ;
; 24.181 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 1.139      ;
; 24.194 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 1.126      ;
; 24.550 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.072     ; 0.770      ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                      ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 38.178 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.071     ; 0.815      ;
; 38.223 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.071     ; 0.770      ;
; 38.223 ; SCLK_6M4          ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.071     ; 0.770      ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLK_PLL1'                                                                                     ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 60.067 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.364      ;
; 60.067 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.364      ;
; 60.067 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.364      ;
; 60.067 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.364      ;
; 60.067 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.364      ;
; 60.074 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.357      ;
; 60.074 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.357      ;
; 60.074 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.357      ;
; 60.074 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.357      ;
; 60.074 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.357      ;
; 60.245 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.186      ;
; 60.245 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.186      ;
; 60.245 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.186      ;
; 60.245 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.186      ;
; 60.245 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.186      ;
; 60.370 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.061      ;
; 60.370 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.061      ;
; 60.370 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.061      ;
; 60.370 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.061      ;
; 60.370 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 2.061      ;
; 60.639 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.792      ;
; 60.639 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.792      ;
; 60.639 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.792      ;
; 60.639 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.792      ;
; 60.639 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.792      ;
; 60.907 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.524      ;
; 60.914 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.517      ;
; 61.085 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.346      ;
; 61.210 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 1.221      ;
; 61.479 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 0.952      ;
; 61.617 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.071     ; 0.814      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                            ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 60.479 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.483      ;
; 60.504 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.458      ;
; 60.599 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.363      ;
; 60.645 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.317      ;
; 60.829 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.133      ;
; 60.829 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.133      ;
; 60.924 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 1.038      ;
; 61.134 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.540     ; 0.828      ;
; 61.223 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.090     ; 1.189      ;
; 61.258 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.072     ; 1.172      ;
; 61.277 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.090     ; 1.135      ;
; 61.377 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.090     ; 1.035      ;
; 61.642 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.090     ; 0.770      ;
; 61.642 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.090     ; 0.770      ;
; 61.642 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.090     ; 0.770      ;
; 61.660 ; CLK_0M5              ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.072     ; 0.770      ;
; 61.660 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.072     ; 0.770      ;
; 61.660 ; CLK_2M0              ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.072     ; 0.770      ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                   ; To Node                                                                                                     ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.076 ; CLK_24576                                                                                                   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL1_S                                                   ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.020        ; 0.471      ; 0.922      ;
; 0.384 ; VMA_68K30Ln                                                                                                 ; VMA_68K30Ln                                                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.090      ; 0.669      ;
; 0.402 ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.SHIFT_R                                                              ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.SHIFT_R                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.LOAD_R                                                               ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.LOAD_R                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\PARITY_TEST:PE_I                          ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\PARITY_TEST:PE_I                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                                  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_LOCK                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_LOCK                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.PARITY                           ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.PARITY                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.WAIT_START                       ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.WAIT_START                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:STRB_LOCK                          ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:STRB_LOCK                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[0]                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[0]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[6]                                           ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3]                ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\TIMER_READBACK:READ_C                                    ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\TIMER_READBACK:READ_C                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\TIMER_READBACK:READ_A                                    ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\TIMER_READBACK:READ_A                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\PARITY_TEST:P_ERR   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\PARITY_TEST:P_ERR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]                 ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[0]                                                ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:BITCNT[0]                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.NONE                                                         ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.NONE                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|RD_MBLOCK_I                                                        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|RD_MBLOCK_I                                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\UNDERRUN:LOCK      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\UNDERRUN:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[10]                                ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[10]                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.PARITY     ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.PARITY     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.WAIT_START ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.WAIT_START ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[1]            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[1]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[2]            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[2]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|LOOPBACK              ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|LOOPBACK              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|PARITY_I            ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|PARITY_I            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[7]        ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\P_BREAK:LOCK       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\P_BREAK:LOCK       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\TBI_STROBE:LOCK                                          ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\TBI_STROBE:LOCK                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                          ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[11]                                   ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[11]                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[12]                                   ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\ADDRESS_SECTION:BLK_TRK_ADR[12]                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|ACCESS_TO_SDC.HDD                                                                     ; WF_SD_DRIVES:I_DRIVES|ACCESS_TO_SDC.HDD                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|NEW_TRACK                                                          ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|NEW_TRACK                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\TRACKS:LOCK                                                       ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\TRACKS:LOCK                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\TRACKS:TRACK_No[2]                                                ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\TRACKS:TRACK_No[2]                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_S                                   ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_S                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[1]                       ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[1]                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0]                       ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0]                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                                      ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_DIN_S                                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_DIN_TMP[1]                                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_SYNC:SPI_DIN_TMP[1]                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|HBLANKn                                             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|HBLANKn                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I                                 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[7]                              ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[7]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_B_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_B_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_C_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_C_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[2]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[1]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[2]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[1]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[0]                                             ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[0]                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[15]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[15]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\TX_SHIFT:LOCK                                        ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\TX_SHIFT:LOCK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ADJUST                                      ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ADJUST                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|BANK                                        ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|BANK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ALARM_EN                                    ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ALARM_EN                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|SPI_PENDING[8]                              ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|SPI_PENDING[8]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[2]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[2]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[7]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[7]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[3]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[3]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[6]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[6]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQ_I                                  ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQ_I                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RDRF_I                                     ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RDRF_I                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                        ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_OVR_LOCK                ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_OVR_LOCK                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                                   ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\FIFO_RD_CTRL:LOCK                                        ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\FIFO_RD_CTRL:LOCK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|FE                                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|FE                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\FRAME_ERR:FE_I                            ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\FRAME_ERR:FE_I                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[1]                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[1]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|CTRL_MASK[1]                                          ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|CTRL_MASK[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|\CTRL_ACC_TIMING:LOCK                                 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|\CTRL_ACC_TIMING:LOCK                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_RD                                     ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_RD                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_WR                                     ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_WR                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|\IPL1n_CONTROL:SECOND                             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|\IPL1n_CONTROL:SECOND                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[3]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[3]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[1]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[1]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[2]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[2]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.WAIT_SCLK                                  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.WAIT_SCLK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.TEST_PENDING                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.TEST_PENDING                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_SCLK                                              ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_SCLK                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[2]                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[2]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[1]                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[1]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_LOW                                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_LOW                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_HI                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_HI                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|FLOPPY_DPLL:DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]          ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|FLOPPY_DPLL:DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_WR_HI                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_WR_HI                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
+-------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                                                        ;
+-------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                  ; To Node                                                                                    ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.383 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]                ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.091      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_VALID                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_VALID                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[3]                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[3]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                    ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4                ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_FLT                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_FLT                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                                   ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SSW_80[8]                               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SSW_80[8]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|\MOVEM_AR_CPY:LOCK                                                      ; WF68K30L_TOP:I_CPU|\MOVEM_AR_CPY:LOCK                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                              ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.UPDATE_PC             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.UPDATE_PC             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IBOUND                         ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IBOUND                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|EW_RDY                                       ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|EW_RDY                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                   ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_BYTES[0]                                  ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_BYTES[0]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|\ADDRESS_MODES:BD_SIZE[0] ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|\ADDRESS_MODES:BD_SIZE[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_HILOn                                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_HILOn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.JMP~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.RTR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSL~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSL~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.LSR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ASR~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ASR~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.CHK~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVEA~reg0                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.PEA~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.Scc~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.Scc~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.MOVE~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ADDQ~reg0                   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.ADDQ~reg0                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.NOP~reg0                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TRAPV~reg0                  ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OP.TRAPV~reg0                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_TRAP~reg0          ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_TRAP~reg0          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_RTE~reg0           ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_RTE~reg0           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_ILLEGAL~reg0       ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_ILLEGAL~reg0       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_1111~reg0          ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.T_1111~reg0          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0            ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|TRAP_CODE.NONE~reg0            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[9]                              ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[9]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[11]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[11]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[26]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[26]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[10]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[10]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[18]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP2_BUFFER[18]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                   ; WF68K30L_TOP:I_CPU|WF68K30L_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_1[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                   ; WF68K30L_TOP:I_CPU|WF68K30L_DATA_REGISTERS:I_DATA_REGISTERS|DR_USED_2[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[29]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[29]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[14]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[14]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[31]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[31]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[25]                             ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[25]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[0]                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[2]                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[3]                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|\MOVEM_CONTROL:MOVEM_PVAR[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|VFLAG_DIV                                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|VFLAG_DIV                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[1]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[1]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[15]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[15]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[14]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[14]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[13]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[13]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[12]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[12]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[11]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[11]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[26]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[26]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[25]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[25]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[24]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[24]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[23]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[23]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[22]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[22]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[21]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[21]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[20]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[20]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[17]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[17]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[19]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[19]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[22]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[22]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[25]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[25]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[23]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[23]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[24]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[24]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[19]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[19]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[21]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[21]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[7]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[7]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[5]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[5]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[6]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[6]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[4]                            ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[4]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[5]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[5]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[4]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[4]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[2]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[2]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[0]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[0]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1]               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2]               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0]               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                    ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_CHK               ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_CHK               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRACE             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRACE             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_DIVZERO           ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_DIVZERO           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRAP              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRAP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_FORMAT            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_FORMAT            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRAPcc            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRAPcc            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE              ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_NONE              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_TRAPV                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.071      ; 0.669      ;
+-------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                                                                                                                                                                                                                ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                      ; To Node                                                                        ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.383 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.091      ; 0.669      ;
; 0.383 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.091      ; 0.669      ;
; 0.384 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.090      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR                     ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[12]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[12]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[11]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[11]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[10]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[10]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[7]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[5]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[2]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[2]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|OP_RDY                              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|OP_RDY                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[2]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[0]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[1]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[3]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_RESPONSE_RDY                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_RESPONSE_RDY                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_DATA_RESPONSE      ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_DATA_RESPONSE      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_OUT                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_OUT                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_WR                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_WR                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[0]                                          ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[0]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[1]                                          ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[4]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[3]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_RD                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_RD                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[6]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[0]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[7]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[1]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:TOKEN              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:TOKEN              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_MBLOCK                           ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_MBLOCK                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:BITCNT[0]              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:BITCNT[0]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_0                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_0                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.SWITCH_SPI                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.SWITCH_SPI                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.POR                        ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.POR                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[19]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[19]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[7]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[6]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[5]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[3]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[1]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[2]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[8]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[8]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CARD_RELEASE:LOCK                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CARD_RELEASE:LOCK                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_RELEASE            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_RELEASE            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.669      ;
; 0.417 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.684      ;
; 0.418 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[0]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.684      ;
; 0.455 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:BITCNT[5] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:BITCNT[5] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.721      ;
; 0.480 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_CMD_RESPONSE       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.746      ;
; 0.486 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.753      ;
; 0.492 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.758      ;
; 0.499 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.765      ;
; 0.499 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.072      ; 0.766      ;
; 0.501 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[4]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.767      ;
; 0.502 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.768      ;
; 0.503 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.769      ;
; 0.503 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.769      ;
; 0.504 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.770      ;
; 0.513 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.779      ;
; 0.523 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.071      ; 0.789      ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.384 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                           ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.385 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.385 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.385 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.392 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                              ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.082      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_SBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_SBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_MBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_MBLOCK                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RW_ERROR                                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RW_ERROR                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|MBLOCK                                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|MBLOCK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:LOCK                     ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:LOCK                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:FIRST_ACCESS             ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:FIRST_ACCESS             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:REJECTED                 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:REJECTED                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK           ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK           ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IO                             ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IO                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\SPEED_DETECTION:LOCK                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\SPEED_DETECTION:LOCK                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\COMMAND_DESCRIPTOR:LOCK                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\COMMAND_DESCRIPTOR:LOCK                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IDLE                           ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IDLE                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STAT_RDY                                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STAT_RDY                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[2]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[2]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[1]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[1]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[3]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[3]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[1]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[2]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In               ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK           ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[0]                                           ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[1]             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[0]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.684      ;
; 0.418 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.684      ;
; 0.419 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[0]             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.684      ;
; 0.451 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|FIFO_RD                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.716      ;
; 0.457 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9]          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.723      ;
; 0.458 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.723      ;
; 0.467 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:ADR_PNTR[8]              ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:ADR_PNTR[8]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.733      ;
; 0.469 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.735      ;
; 0.470 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[6]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.735      ;
; 0.470 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\STARTUP:STARTUP_COUNT[24]          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\STARTUP:STARTUP_COUNT[24]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[23]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.736      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[45]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[38]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[29]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[12]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[5]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.737      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[52]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[3]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[41]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[16]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[17]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.738      ;
; 0.473 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[4]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[2]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[25]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.739      ;
; 0.473 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.071      ; 0.739      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                            ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.384 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.090      ; 0.669      ;
; 0.384 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.090      ; 0.669      ;
; 0.399 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.090      ; 0.684      ;
; 0.402 ; CLK_2M0              ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; CLK_0M5              ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 0.669      ;
; 0.638 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.090      ; 0.923      ;
; 0.708 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.090      ; 0.993      ;
; 0.709 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.090      ; 0.994      ;
; 0.823 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.072      ; 1.090      ;
; 0.907 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 0.724      ;
; 1.106 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 0.923      ;
; 1.174 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 0.991      ;
; 1.175 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 0.992      ;
; 1.371 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 1.188      ;
; 1.427 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 1.244      ;
; 1.503 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 1.320      ;
; 1.536 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.378     ; 1.353      ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                      ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; SCLK_6M4          ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.418 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.450 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.071      ; 0.716      ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                              ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.417 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.684      ;
; 0.688 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.955      ;
; 0.710 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.977      ;
; 0.711 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 0.978      ;
; 1.007 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 1.274      ;
; 1.009 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 1.276      ;
; 1.258 ; CLK_24576             ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 1.525      ;
; 1.568 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 1.835      ;
; 1.578 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 1.845      ;
; 1.581 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.072      ; 1.848      ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLK_PLL1'                                                                                     ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.449 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.715      ;
; 0.593 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.859      ;
; 0.696 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.962      ;
; 0.697 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.963      ;
; 0.698 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.964      ;
; 0.699 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.965      ;
; 0.722 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 0.988      ;
; 0.800 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.066      ;
; 0.930 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.196      ;
; 1.017 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.283      ;
; 1.017 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.283      ;
; 1.018 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.284      ;
; 1.019 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.285      ;
; 1.032 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.298      ;
; 1.033 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.299      ;
; 1.115 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.381      ;
; 1.138 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.404      ;
; 1.138 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.404      ;
; 1.139 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.405      ;
; 1.141 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.407      ;
; 1.154 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.420      ;
; 1.524 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.790      ;
; 1.524 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.790      ;
; 1.524 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.790      ;
; 1.524 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.790      ;
; 1.731 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 1.997      ;
; 1.861 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 2.127      ;
; 1.861 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 2.127      ;
; 2.069 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 2.335      ;
; 2.069 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 2.335      ;
; 2.069 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.071      ; 2.335      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                  ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                            ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[38] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[41] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[42] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.313 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.192     ; 8.747      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][8]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][9]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][11]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[15][13]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][3]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][8]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][9]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][11]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][13]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][14]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][3]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][6]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][8]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][9]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][11]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][13]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][14]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.744      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][3]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][8]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][9]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][11]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][13]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.318 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][14]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][9]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][11]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][13]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][14]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[5][15]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[13][15]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][0]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][2]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][7]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][12]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][10]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][11]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][12]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[9][14]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][12]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][14]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[7][15]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][8]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][9]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][10]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][11]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][13]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][14]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][15]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][9]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][10]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][11]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.188     ; 8.745      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][1]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][3]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][8]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][9]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][10]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][11]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][13]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][14]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[12][15]       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.189     ; 8.744      ;
; 22.319 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[10][0]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.190     ; 8.743      ;
+--------+-------------------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                            ; To Node                                                                                                   ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 22.339 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.172     ; 8.741      ;
; 22.339 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.172     ; 8.741      ;
; 22.339 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.172     ; 8.741      ;
; 22.341 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.174     ; 8.737      ;
; 22.354 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.735      ;
; 22.354 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.162     ; 8.736      ;
; 22.354 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.162     ; 8.736      ;
; 22.361 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.728      ;
; 22.361 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.728      ;
; 22.361 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.728      ;
; 22.365 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.738      ;
; 22.365 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.738      ;
; 22.365 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.738      ;
; 22.365 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.738      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.742      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.742      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.742      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.742      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.742      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.148     ; 8.736      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.148     ; 8.736      ;
; 22.368 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.148     ; 8.736      ;
; 22.377 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.745      ;
; 22.377 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.745      ;
; 22.377 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.745      ;
; 22.380 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.172     ; 8.700      ;
; 22.380 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.172     ; 8.700      ;
; 22.380 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.172     ; 8.700      ;
; 22.382 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.174     ; 8.696      ;
; 22.389 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.119     ; 8.744      ;
; 22.389 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.119     ; 8.744      ;
; 22.389 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.120     ; 8.743      ;
; 22.395 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.694      ;
; 22.395 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.162     ; 8.695      ;
; 22.395 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.162     ; 8.695      ;
; 22.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.687      ;
; 22.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.687      ;
; 22.402 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.163     ; 8.687      ;
; 22.406 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.697      ;
; 22.406 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.697      ;
; 22.406 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.697      ;
; 22.406 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.149     ; 8.697      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.701      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.701      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.701      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.701      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.142     ; 8.701      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.148     ; 8.695      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.148     ; 8.695      ;
; 22.409 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.148     ; 8.695      ;
; 22.418 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.704      ;
; 22.418 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.704      ;
; 22.418 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.704      ;
; 22.430 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.119     ; 8.703      ;
; 22.430 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.119     ; 8.703      ;
; 22.430 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.120     ; 8.702      ;
; 22.545 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.160     ; 8.547      ;
; 22.545 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.160     ; 8.547      ;
; 22.545 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.160     ; 8.547      ;
; 22.547 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.162     ; 8.543      ;
; 22.560 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.151     ; 8.541      ;
; 22.560 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.150     ; 8.542      ;
; 22.560 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.150     ; 8.542      ;
; 22.567 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.151     ; 8.534      ;
; 22.567 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.151     ; 8.534      ;
; 22.567 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.151     ; 8.534      ;
; 22.571 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 8.544      ;
; 22.571 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 8.544      ;
; 22.571 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 8.544      ;
; 22.571 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.137     ; 8.544      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.548      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.548      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.548      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.548      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.130     ; 8.548      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.136     ; 8.542      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.136     ; 8.542      ;
; 22.574 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.136     ; 8.542      ;
; 22.583 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.118     ; 8.551      ;
; 22.583 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.118     ; 8.551      ;
; 22.583 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.118     ; 8.551      ;
; 22.595 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.107     ; 8.550      ;
; 22.595 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.107     ; 8.550      ;
; 22.595 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.108     ; 8.549      ;
; 22.689 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 8.741      ;
; 22.689 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.178      ; 8.741      ;
; 22.690 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.169      ; 8.731      ;
; 22.690 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.169      ; 8.731      ;
; 22.690 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.169      ; 8.731      ;
; 22.690 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.169      ; 8.731      ;
; 22.699 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.188      ; 8.741      ;
; 22.701 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.186      ; 8.737      ;
; 22.701 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.187      ; 8.738      ;
; 22.702 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.184      ; 8.734      ;
; 22.704 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.188      ; 8.736      ;
; 22.713 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.203      ; 8.742      ;
; 22.713 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.203      ; 8.742      ;
; 22.718 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.202      ; 8.736      ;
; 22.718 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.202      ; 8.736      ;
; 22.728 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.213      ; 8.737      ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                         ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                         ; To Node                                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 28.005 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.017     ; 3.230      ;
; 28.354 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.017     ; 2.881      ;
; 28.361 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_RD     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.048     ; 2.843      ;
; 28.382 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.017     ; 2.853      ;
; 28.685 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_WR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.048     ; 2.519      ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                                          ;
+-------+----------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                ; To Node                                                                                                           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.530 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.085      ; 1.810      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.614 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 1.878      ;
; 1.885 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.161      ;
; 1.885 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.161      ;
; 1.885 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.161      ;
; 1.885 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.161      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 1.902 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.081      ; 2.178      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE                                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.082      ; 2.381      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.082      ; 2.381      ;
; 2.104 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.082      ; 2.381      ;
; 2.131 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.064      ; 2.390      ;
; 2.202 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.061      ; 2.458      ;
; 2.202 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.061      ; 2.458      ;
; 2.202 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.061      ; 2.458      ;
; 2.424 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 2.688      ;
; 2.424 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 2.688      ;
; 2.424 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 2.688      ;
; 2.424 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 2.688      ;
; 2.424 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 2.688      ;
; 2.424 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.069      ; 2.688      ;
; 2.430 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.063      ; 2.688      ;
; 2.430 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.063      ; 2.688      ;
; 2.489 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.744      ;
; 2.489 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.744      ;
; 2.489 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.744      ;
; 2.489 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.744      ;
; 2.489 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.744      ;
; 2.489 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.744      ;
; 2.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.781      ;
; 2.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.781      ;
; 2.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.781      ;
; 2.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.060      ; 2.781      ;
; 2.971 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.059      ; 3.225      ;
; 2.971 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.059      ; 3.225      ;
; 2.971 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.059      ; 3.225      ;
; 2.971 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.059      ; 3.225      ;
; 2.971 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.059      ; 3.225      ;
; 3.070 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[22]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.327      ;
; 3.070 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.327      ;
; 3.070 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.327      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[23]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[21]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[20]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.086 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.062      ; 3.343      ;
; 3.115 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.055      ; 3.365      ;
; 3.115 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.055      ; 3.365      ;
; 3.115 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.055      ; 3.365      ;
; 3.115 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.055      ; 3.365      ;
; 3.115 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.055      ; 3.365      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:9:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:9:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[13]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[14]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[14]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:9:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[14]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[14] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[10]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.078      ; 3.851      ;
; 3.578 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:8:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[10]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.079      ; 3.852      ;
+-------+----------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                      ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                                                  ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.671 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.148      ; 4.034      ;
; 3.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.264      ; 4.460      ;
; 3.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.264      ; 4.460      ;
; 3.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.264      ; 4.460      ;
; 3.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.264      ; 4.460      ;
; 3.992 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.258      ; 4.465      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.229      ; 4.459      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[3]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.455      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.455      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.229      ; 4.459      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.455      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.229      ; 4.459      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[5]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.455      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.455      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[0]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.455      ;
; 4.015 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[16]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.229      ; 4.459      ;
; 4.016 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.228      ; 4.459      ;
; 4.018 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[14]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.222      ; 4.455      ;
; 4.018 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[8]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.222      ; 4.455      ;
; 4.020 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.227      ; 4.462      ;
; 4.020 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.227      ; 4.462      ;
; 4.023 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.227      ; 4.465      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[19] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.222      ; 4.461      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.464      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.464      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.464      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.222      ; 4.461      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.464      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.222      ; 4.461      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.221      ; 4.460      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.464      ;
; 4.024 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.225      ; 4.464      ;
; 4.025 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.223      ; 4.463      ;
; 4.025 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.223      ; 4.463      ;
; 4.027 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.215      ; 4.457      ;
; 4.029 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.192      ; 4.436      ;
; 4.029 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.192      ; 4.436      ;
; 4.029 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.192      ; 4.436      ;
; 4.029 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.192      ; 4.436      ;
; 4.029 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.192      ; 4.436      ;
; 4.029 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.192      ; 4.436      ;
; 4.031 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.214      ; 4.460      ;
; 4.032 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.221      ; 4.468      ;
; 4.032 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.221      ; 4.468      ;
; 4.035 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.209      ; 4.459      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.214      ; 4.465      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.214      ; 4.465      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.207      ; 4.458      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.214      ; 4.465      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.207      ; 4.458      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.214      ; 4.465      ;
; 4.036 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.214      ; 4.465      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[11]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[10]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[12]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[14]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[15]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.038 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[8]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.453      ;
; 4.039 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[19]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.206      ; 4.460      ;
; 4.039 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.206      ; 4.460      ;
; 4.039 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[18]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.206      ; 4.460      ;
; 4.039 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.186      ; 4.440      ;
; 4.039 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.206      ; 4.460      ;
; 4.040 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.211      ; 4.466      ;
; 4.040 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.209      ; 4.464      ;
; 4.040 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.211      ; 4.466      ;
; 4.040 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.211      ; 4.466      ;
; 4.042 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.208      ; 4.465      ;
; 4.042 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.208      ; 4.465      ;
; 4.042 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.208      ; 4.465      ;
; 4.043 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.209      ; 4.467      ;
; 4.043 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.206      ; 4.464      ;
; 4.043 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.208      ; 4.466      ;
; 4.046 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.202      ; 4.463      ;
; 4.046 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.202      ; 4.463      ;
; 4.046 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.202      ; 4.463      ;
; 4.048 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.201      ; 4.464      ;
; 4.048 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.191      ; 4.454      ;
; 4.051 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.466      ;
; 4.051 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.466      ;
; 4.051 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.466      ;
; 4.051 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.466      ;
; 4.051 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.200      ; 4.466      ;
; 4.058 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.182      ; 4.455      ;
; 4.058 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.186      ; 4.459      ;
; 4.063 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.184      ; 4.462      ;
; 4.063 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.184      ; 4.462      ;
; 4.063 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.184      ; 4.462      ;
; 4.064 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.180      ; 4.459      ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                          ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                         ; To Node                                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 33.125 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_WR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.126      ; 2.216      ;
; 33.364 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_RD     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.125      ; 2.454      ;
; 33.381 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.124      ; 2.470      ;
; 33.458 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.124      ; 2.547      ;
; 33.732 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.124      ; 2.821      ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 12.386 ; 12.602       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 12.386 ; 12.602       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 12.386 ; 12.602       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 12.386 ; 12.602       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
; 12.599 ; 12.783       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 12.599 ; 12.783       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 12.599 ; 12.783       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 12.599 ; 12.783       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
; 12.656 ; 12.656       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576|clk                                                                 ;
; 12.656 ; 12.656       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                                                     ;
; 12.656 ; 12.656       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                                                     ;
; 12.656 ; 12.656       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                                                     ;
; 12.659 ; 12.659       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] ;
; 12.659 ; 12.659       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk   ;
; 12.729 ; 12.729       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] ;
; 12.729 ; 12.729       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk   ;
; 12.732 ; 12.732       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576|clk                                                                 ;
; 12.732 ; 12.732       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                                                     ;
; 12.732 ; 12.732       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                                                     ;
; 12.732 ; 12.732       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                                                     ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 22.903 ; 25.390       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                                   ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------+
; 15.268 ; 15.484       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[7]                ;
; 15.269 ; 15.485       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[3]                ;
; 15.269 ; 15.485       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[4]                ;
; 15.269 ; 15.485       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[5]                ;
; 15.269 ; 15.485       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[11] ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[12] ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[14] ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]              ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]              ;
; 15.270 ; 15.486       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ;
; 15.271 ; 15.487       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                   ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[2]                   ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[3]                   ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[7]                   ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[0]  ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10] ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15] ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[2]  ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[3]  ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[4]  ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[6]  ;
; 15.273 ; 15.489       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]         ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                  ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                  ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[2]      ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[7]      ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[10]   ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[15]   ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[1]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[2]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[3]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[6]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[8]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[8]  ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[2]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[4]    ;
; 15.274 ; 15.490       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[2]                ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[11]                  ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[13]                  ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[9]                   ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[0]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[4]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[5]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[7]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18] ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[10]             ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[11]             ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[12]             ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[14]             ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[15]             ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[8]              ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[4]     ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ;
; 15.275 ; 15.491       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]   ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]   ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[18]             ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[22]             ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[23]             ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[6]     ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                              ;
; 15.276 ; 15.492       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                              ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[0]                ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                  ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[4]                   ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]   ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[16] ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[0]         ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]         ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ;
; 15.277 ; 15.493       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]             ;
; 15.278 ; 15.494       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|MEMCONFIG[1]                ;
; 15.278 ; 15.494       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[22]                  ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 19.223 ; 19.439       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 19.223 ; 19.439       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
; 19.434 ; 19.618       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 19.434 ; 19.618       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
; 19.493 ; 19.493       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4|clk                                                                  ;
; 19.493 ; 19.493       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]|clk                                                         ;
; 19.495 ; 19.495       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.495 ; 19.495       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.565 ; 19.565       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.565 ; 19.565       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.567 ; 19.567       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4|clk                                                                  ;
; 19.567 ; 19.567       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]|clk                                                         ;
; 36.575 ; 39.062       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 36.575 ; 39.062       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                      ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------+
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[112]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[113]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[114]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[115]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[116]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[117]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[118]                   ;
; 20.480 ; 20.696       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[119]                   ;
; 20.482 ; 20.698       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[72]                    ;
; 20.482 ; 20.698       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[73]                    ;
; 20.482 ; 20.698       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]         ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[32]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[33]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[34]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[35]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[36]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[37]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[38]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[39]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[64]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[65]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[66]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[67]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[68]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[69]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[70]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[71]                    ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]          ;
; 20.483 ; 20.699       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]          ;
; 20.484 ; 20.700       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[31]             ;
; 20.484 ; 20.700       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.CMD_12            ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[100]                   ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[101]                   ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[102]                   ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[103]                   ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[96]                    ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[97]                    ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[98]                    ;
; 20.485 ; 20.701       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[99]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[48]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[49]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[50]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[51]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[52]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[53]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[54]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[55]                    ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[126]                   ;
; 20.486 ; 20.702       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[127]                   ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[56]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[57]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[58]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[59]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[60]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[61]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[62]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[63]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[48]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[49]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[50]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[51]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[52]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[53]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[54]                    ;
; 20.488 ; 20.704       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[55]                    ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[0]                     ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[5]                     ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[7]                     ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]              ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[7]              ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]         ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]         ;
; 20.490 ; 20.706       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]          ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                     ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR            ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.CMD_13            ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.CMD_17            ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.CMD_18            ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_10       ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_16       ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_55       ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS   ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_OCR   ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_59       ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_8        ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_9        ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_A41      ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]         ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]         ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]         ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]         ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]         ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]         ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0] ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1] ;
; 20.526 ; 20.742       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2] ;
; 20.527 ; 20.743       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]                    ;
; 20.527 ; 20.743       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]                    ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                          ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                                                  ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------+
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[2]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[3]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[4]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[5]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[6]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[7]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[8]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[9]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[0]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[10]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[11]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[12]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[13]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[14]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[15]~_Duplicate_2 ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[1]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[2]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[3]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[4]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[5]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[6]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[7]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[8]~_Duplicate_2  ;
; 30.819 ; 31.201       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[9]~_Duplicate_2  ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[29]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[30]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[31]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[18]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[19]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[20]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[21]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[22]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[23]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[24]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[25]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[26]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[27]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[28]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[29]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[30]~_Duplicate_1 ;
; 30.821 ; 31.203       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[31]~_Duplicate_1 ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[2]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[3]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[4]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[5]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[6]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[7]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[8]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[9]               ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[18]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[19]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[20]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[21]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[22]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[23]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[24]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[25]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[26]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[27]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[28]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[29]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[30]              ;
; 30.822 ; 31.204       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP2[31]              ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 30.824 ; 31.206       ; 0.382          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                          ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                                                    ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------+
; 30.888 ; 31.104       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[7][13]                                   ;
; 30.888 ; 31.104       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_X_INCR[4]                                         ;
; 30.892 ; 31.108       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|OP_I[1]                                               ;
; 30.892 ; 31.108       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|OP_I[3]                                               ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[12]                                       ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[1]                                        ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[2]                                        ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[3]                                        ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_Y_INCR[4]                                        ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][4]                                    ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][5]                                    ;
; 30.893 ; 31.109       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][9]                                    ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[10][0]                                   ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[10][10]                                  ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[10][11]                                  ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[10][6]                                   ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[10][7]                                   ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][12]                                   ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][4]                                    ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][5]                                    ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][6]                                    ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][8]                                    ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][9]                                    ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[0]                            ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[5]                            ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[6]                            ;
; 30.894 ; 31.110       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[7]                            ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[10]                                       ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[11]                                       ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[4]                                        ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[5]                                        ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[8]                                        ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[9]                                        ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][1]                                    ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[12]                                        ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[1]                                         ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[2]                                         ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[3]                                         ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[8]                                         ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[9]                                         ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|ENV_FREQ[14]                              ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|ENV_FREQ[15]                              ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[5]                            ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[6]                            ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[7]                            ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[2]                                         ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[4]                                         ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[5]                                         ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[6]                                         ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[7]                                         ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[4]                                           ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[5]                                           ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[6]                                           ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]                                           ;
; 30.896 ; 31.112       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][11]                                   ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][13]                                   ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][14]                                   ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[0][3]                                    ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][12]                                   ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][4]                                    ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_Y_INCR[4]                                         ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|ADR_I[0]                                                                  ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|ADR_I[1]                                                                  ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|ADR_I[2]                                                                  ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|ADR_I[3]                                                                  ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[2]                            ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_B[4]                            ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|FREQUENCY_C[0]                            ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|NOISE_FREQ[0]                             ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|NOISE_FREQ[1]                             ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|NOISE_FREQ[2]                             ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|NOISE_FREQ[3]                             ;
; 30.897 ; 31.113       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|NOISE_FREQ[4]                             ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[12]                                       ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[3]                                        ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[6]                                        ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_X_INCR[7]                                        ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[3]                                           ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[7]                                           ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[8]                                           ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK2[9]                                           ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[15][12]                                  ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[15][1]                                   ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[15][2]                                   ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[15][3]                                   ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[15][8]                                   ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[1][0]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[1][11]                                   ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[1][1]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[1][2]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[1][3]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][11]                                   ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][1]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][2]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][3]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][5]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][8]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[6][9]                                    ;
; 30.898 ; 31.114       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[7][12]                                   ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 30.895 ; 31.111       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 30.944 ; 31.160       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 30.944 ; 31.160       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 30.944 ; 31.160       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
; 31.151 ; 31.335       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 31.151 ; 31.335       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 31.151 ; 31.335       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
; 31.165 ; 31.165       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                                                      ;
; 31.165 ; 31.165       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                                                      ;
; 31.165 ; 31.165       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                                                      ;
; 31.199 ; 31.383       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 31.199 ; 31.383       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 31.199 ; 31.383       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 31.214 ; 31.214       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5|clk                                                                   ;
; 31.214 ; 31.214       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0|clk                                                                   ;
; 31.214 ; 31.214       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                                                      ;
; 31.215 ; 31.215       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ;
; 31.215 ; 31.215       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk   ;
; 31.284 ; 31.284       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5|clk                                                                   ;
; 31.284 ; 31.284       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0|clk                                                                   ;
; 31.284 ; 31.284       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ;
; 31.284 ; 31.284       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk   ;
; 31.284 ; 31.284       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                                                      ;
; 31.332 ; 31.332       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                                                      ;
; 31.332 ; 31.332       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                                                      ;
; 31.332 ; 31.332       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                                                      ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL1'                                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                            ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 31.007 ; 31.191       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
; 31.080 ; 31.080       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.080 ; 31.080       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.080 ; 31.080       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.080 ; 31.080       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]           ;
; 31.080 ; 31.080       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 31.089 ; 31.305       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 31.089 ; 31.305       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 31.089 ; 31.305       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 31.089 ; 31.305       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 31.089 ; 31.305       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 31.089 ; 31.305       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 31.090 ; 31.306       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 31.090 ; 31.306       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
; 31.135 ; 31.135       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|o                                                  ;
; 31.138 ; 31.138       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|inclk[0]                                    ;
; 31.138 ; 31.138       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|outclk                                      ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                                                    ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT|clk                                                     ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                                          ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                                          ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                                          ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                                          ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                                          ;
; 31.140 ; 31.140       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                                               ;
; 31.159 ; 31.159       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|i                                                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|i                                                  ;
; 31.340 ; 31.340       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.359 ; 31.359       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT|clk                                                     ;
; 31.359 ; 31.359       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                                          ;
; 31.359 ; 31.359       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                                          ;
; 31.359 ; 31.359       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                                          ;
; 31.359 ; 31.359       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                                          ;
; 31.359 ; 31.359       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                                          ;
; 31.360 ; 31.360       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                                                    ;
; 31.360 ; 31.360       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                                               ;
; 31.361 ; 31.361       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|inclk[0]                                    ;
; 31.361 ; 31.361       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|outclk                                      ;
; 31.365 ; 31.365       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|o                                                  ;
; 31.420 ; 31.420       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.420 ; 31.420       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.420 ; 31.420       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.420 ; 31.420       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]           ;
; 31.420 ; 31.420       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 58.500 ; 62.500       ; 4.000          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                                          ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 60.013 ; 62.500       ; 2.487          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL2'                                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                            ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; 31.082 ; 31.082       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.082 ; 31.082       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.082 ; 31.082       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.082 ; 31.082       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 31.131 ; 31.131       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|o                                                  ;
; 31.161 ; 31.161       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|i                                                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|i                                                  ;
; 31.338 ; 31.338       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.369 ; 31.369       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|o                                                  ;
; 31.418 ; 31.418       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.418 ; 31.418       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.418 ; 31.418       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.418 ; 31.418       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 58.500 ; 62.500       ; 4.000          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                                          ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; -0.180 ; 0.107  ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; 9.453  ; 8.708  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 26.542 ; 25.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 18.615 ; 18.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 18.284 ; 18.480 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 26.353 ; 25.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 26.299 ; 25.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 26.542 ; 25.772 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 15.791 ; 15.018 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 13.544 ; 12.945 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 13.636 ; 12.883 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 14.111 ; 13.066 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 14.264 ; 13.393 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 12.614 ; 11.833 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 12.192 ; 11.600 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 14.074 ; 13.146 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 14.298 ; 13.457 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 13.237 ; 12.616 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 15.494 ; 14.231 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 14.674 ; 14.161 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 15.187 ; 14.197 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 15.791 ; 15.018 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 13.101 ; 12.625 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 11.156 ; 10.954 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 11.014 ; 11.162 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 5.553  ; 5.655  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; 3.930  ; 4.201  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 6.564  ; 6.941  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; 7.188  ; 7.367  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; 4.075  ; 4.295  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 4.704  ; 4.871  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 17.871 ; 17.278 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 16.085 ; 15.052 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 15.893 ; 14.738 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 17.436 ; 15.660 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 16.398 ; 14.890 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 14.103 ; 12.990 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 14.147 ; 13.097 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 15.057 ; 13.834 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 15.064 ; 13.910 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 15.100 ; 14.051 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 17.580 ; 15.881 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 15.487 ; 14.544 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 15.048 ; 13.971 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 13.426 ; 12.989 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 13.798 ; 13.758 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 14.032 ; 13.978 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 17.871 ; 17.278 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; 2.078  ; 2.504  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 6.050  ; 6.030  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; 15.667 ; 15.060 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 7.531  ; 7.673  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; 7.531  ; 7.673  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; 6.968  ; 7.071  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 5.450  ; 5.562  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; 5.731  ; 5.927  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 7.415  ; 7.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 22.757 ; 22.067 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 15.518 ; 15.716 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 15.187 ; 15.383 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 22.568 ; 22.067 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 22.514 ; 21.799 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 22.757 ; 22.033 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 11.721 ; 11.043 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 9.888  ; 9.697  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 9.998  ; 9.579  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 10.177 ; 9.788  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 10.946 ; 10.490 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 9.586  ; 9.257  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 9.039  ; 8.808  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 10.733 ; 10.229 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 11.201 ; 10.723 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 9.794  ; 9.526  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 11.721 ; 11.043 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 9.975  ; 9.672  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 10.865 ; 10.167 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 11.255 ; 10.676 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 8.269  ; 8.082  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 7.655  ; 7.350  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 6.763  ; 6.787  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 13.807 ; 12.844 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.429 ; 11.804 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 12.255 ; 11.434 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 13.502 ; 12.382 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.080 ; 11.987 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.075 ; 10.414 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 10.994 ; 10.305 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 11.716 ; 10.917 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 11.967 ; 11.176 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 11.657 ; 10.961 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 13.807 ; 12.693 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 10.788 ; 10.055 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.726 ; 9.941  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.890  ; 8.647  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.966  ; 8.926  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.529 ; 10.475 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 13.437 ; 12.844 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 23.337 ; 22.466 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; 16.039 ; 16.237 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; 15.708 ; 15.904 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 23.148 ; 22.466 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 23.094 ; 22.198 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 23.337 ; 22.432 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; 11.777 ; 11.238 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; 10.468 ; 10.188 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; 10.397 ; 9.983  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; 11.301 ; 10.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; 11.777 ; 11.238 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; 10.034 ; 9.609  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; 10.126 ; 9.685  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; 11.411 ; 10.794 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; 11.722 ; 11.111 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; 9.924  ; 9.598  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 14.626 ; 13.395 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.009 ; 12.295 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 12.654 ; 11.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 14.626 ; 13.395 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.911 ; 12.735 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.523 ; 10.766 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.081 ; 11.182 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.394 ; 11.482 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.488 ; 11.564 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 11.787 ; 11.033 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.647  ; 9.010  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.465  ; 9.714  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.677  ; 9.032  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.710  ; 10.030 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.627  ; 9.943  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 9.807  ; 10.073 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.525  ; 9.841  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; 11.478 ; 11.045 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 13.296 ; 12.683 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 13.107 ; 12.683 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 13.053 ; 12.415 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 13.296 ; 12.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 24.249 ; 23.664 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 24.060 ; 23.664 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 24.006 ; 23.396 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 24.249 ; 23.630 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; 24.326 ; 23.741 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; 17.184 ; 17.382 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; 16.853 ; 17.049 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 24.137 ; 23.741 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 24.083 ; 23.473 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 24.326 ; 23.707 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; 14.066 ; 13.135 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; 10.936 ; 10.740 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; 11.672 ; 11.200 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; 12.599 ; 11.888 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; 12.081 ; 11.601 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; 10.601 ; 10.172 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; 10.982 ; 10.729 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; 12.205 ; 11.620 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; 12.867 ; 12.260 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; 12.075 ; 11.584 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; 14.066 ; 13.135 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; 12.586 ; 12.033 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; 13.030 ; 12.120 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; 13.317 ; 12.467 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; 10.570 ; 10.184 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; 8.732  ; 8.472  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; 8.852  ; 8.601  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 16.152 ; 15.095 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.477 ; 12.847 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.929 ; 13.055 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 15.924 ; 14.482 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 14.215 ; 13.098 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.090 ; 11.329 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.937 ; 12.226 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.188 ; 12.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 13.633 ; 12.713 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 13.938 ; 13.019 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 16.152 ; 14.785 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 13.399 ; 12.416 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 12.891 ; 11.894 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.952 ; 10.438 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 11.267 ; 11.227 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 11.608 ; 11.554 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 15.688 ; 15.095 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 8.087  ; 8.152  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; 9.988  ; 9.843  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                           ;
+---------------+------------+---------+---------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+---------+---------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; 0.876   ; 0.585   ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; -5.096  ; -5.024  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -4.485  ; -4.618  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -4.810  ; -4.940  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -4.485  ; -4.618  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -7.787  ; -7.609  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -7.868  ; -7.568  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -9.816  ; -9.406  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -4.776  ; -4.820  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -6.416  ; -6.264  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -6.274  ; -6.144  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -7.035  ; -6.825  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -6.746  ; -6.481  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -4.776  ; -4.820  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -6.003  ; -5.961  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -7.334  ; -7.140  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -6.069  ; -6.060  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -5.868  ; -5.861  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -6.743  ; -6.689  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -6.508  ; -6.395  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -6.019  ; -5.956  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -8.327  ; -7.997  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -7.211  ; -7.067  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -6.762  ; -6.394  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -6.780  ; -6.682  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; -4.737  ; -4.839  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; -2.381  ; -2.643  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; -4.645  ; -4.741  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; -5.232  ; -5.338  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; -3.316  ; -3.533  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; -3.826  ; -3.964  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -8.074  ; -7.711  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -11.075 ; -10.471 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -11.336 ; -10.525 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -12.758 ; -11.545 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -12.255 ; -11.142 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -8.888  ; -8.381  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -10.311 ; -9.593  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -11.027 ; -10.139 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -10.572 ; -9.819  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -11.156 ; -10.393 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -13.138 ; -11.944 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -10.508 ; -9.606  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -10.202 ; -9.349  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -8.074  ; -7.711  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -8.280  ; -8.235  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -8.824  ; -8.763  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -12.748 ; -12.151 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; -1.407  ; -1.820  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; -5.181  ; -5.163  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; -5.798  ; -5.769  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; -5.165  ; -5.271  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; -5.277  ; -5.450  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; -5.165  ; -5.271  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; -4.307  ; -4.390  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; -4.827  ; -5.011  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; -4.328  ; -4.468  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -6.958  ; -6.739  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -12.598 ; -12.692 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -12.279 ; -12.370 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -6.958  ; -6.780  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -7.039  ; -6.739  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -8.692  ; -8.150  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -4.436  ; -4.620  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -5.893  ; -5.824  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -4.901  ; -4.937  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -5.982  ; -5.956  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -4.436  ; -4.620  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -5.667  ; -5.632  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -5.477  ; -5.547  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -6.128  ; -6.139  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -5.759  ; -5.782  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -4.875  ; -4.980  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -5.432  ; -5.527  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -5.670  ; -5.714  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -5.100  ; -5.164  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -7.692  ; -7.502  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -5.780  ; -5.791  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -5.443  ; -5.363  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -5.353  ; -5.387  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -7.004  ; -6.959  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -10.548 ; -10.026 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -10.739 ; -10.030 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -11.705 ; -10.676 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -11.580 ; -10.594 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -9.779  ; -9.193  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -9.785  ; -9.179  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -9.945  ; -9.314  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -10.262 ; -9.541  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -10.163 ; -9.512  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -11.827 ; -10.782 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -9.671  ; -8.923  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -9.283  ; -8.557  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -7.439  ; -7.216  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -7.004  ; -6.959  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -7.793  ; -7.732  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -11.453 ; -10.856 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -4.051  ; -4.135  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; -4.452  ; -4.523  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; -4.051  ; -4.135  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -6.581  ; -6.411  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -6.662  ; -6.370  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -8.436  ; -7.987  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; -4.096  ; -4.165  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; -4.672  ; -4.771  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; -4.530  ; -4.636  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; -4.096  ; -4.165  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; -4.623  ; -4.670  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; -4.832  ; -4.913  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; -4.666  ; -4.843  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; -4.970  ; -5.153  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; -5.097  ; -5.266  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; -5.336  ; -5.352  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.043  ; -3.291  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -3.043  ; -3.291  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -3.677  ; -3.833  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -3.382  ; -3.573  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -3.725  ; -3.901  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -3.737  ; -3.781  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -3.662  ; -3.834  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -3.588  ; -3.732  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -3.676  ; -3.799  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -3.983  ; -4.082  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -3.731  ; -3.792  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -3.778  ; -3.824  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -3.675  ; -3.828  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.714  ; -3.877  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -3.687  ; -3.850  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -3.818  ; -3.912  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -3.984  ; -4.101  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; -5.044  ; -5.009  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -8.297  ; -8.036  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -8.323  ; -8.241  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -8.297  ; -8.036  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -8.530  ; -8.261  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -10.313 ; -9.754  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -10.313 ; -9.795  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -10.394 ; -9.754  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -12.031 ; -11.517 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; -7.812  ; -7.520  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; -12.860 ; -12.954 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; -12.541 ; -12.632 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -7.812  ; -7.561  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -7.893  ; -7.520  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -9.530  ; -9.283  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; -5.040  ; -5.125  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; -6.281  ; -6.165  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; -6.611  ; -6.571  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; -5.040  ; -5.155  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; -5.049  ; -5.125  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; -5.736  ; -5.716  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; -5.810  ; -5.792  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; -6.200  ; -6.240  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; -5.337  ; -5.303  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; -6.549  ; -6.481  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; -6.978  ; -6.965  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; -6.895  ; -6.837  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; -6.842  ; -6.635  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; -8.746  ; -8.391  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; -7.269  ; -7.149  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; -6.507  ; -6.385  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; -6.597  ; -6.489  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -8.362  ; -8.105  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -10.939 ; -10.370 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -11.431 ; -10.826 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -12.245 ; -11.344 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -11.496 ; -10.612 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -9.636  ; -9.031  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -10.094 ; -9.424  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -10.480 ; -9.739  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -10.583 ; -9.803  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -11.837 ; -11.013 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -13.373 ; -12.220 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -10.895 ; -10.048 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -11.025 ; -10.028 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -8.493  ; -8.105  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -8.362  ; -8.317  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -8.815  ; -8.754  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -12.555 ; -11.958 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; -3.327  ; -3.496  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; -4.736  ; -4.680  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+---------+---------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                              ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 11.467 ; 10.503 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 23.525 ; 22.183 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 22.141 ; 20.522 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 21.499 ; 20.116 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 22.288 ; 20.725 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 23.032 ; 21.464 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 22.685 ; 21.296 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 23.525 ; 21.734 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 22.135 ; 20.943 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 22.382 ; 20.833 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 19.757 ; 18.290 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 19.621 ; 18.200 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 18.377 ; 17.099 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 18.730 ; 17.619 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 18.233 ; 17.034 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 19.890 ; 19.297 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 23.011 ; 22.183 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 20.876 ; 20.192 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 14.790 ; 14.172 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 19.863 ; 19.661 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 13.370 ; 12.033 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 12.977 ; 12.017 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 11.181 ; 10.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 11.906 ; 11.065 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 12.003 ; 11.080 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 12.990 ; 12.126 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 11.972 ; 11.231 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 11.369 ; 10.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 10.892 ; 10.508 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 12.881 ; 12.325 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 12.467 ; 11.738 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 14.869 ; 13.658 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 12.000 ; 10.855 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 12.191 ; 11.113 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 12.608 ; 11.497 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 18.537 ; 17.872 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 18.344 ; 17.588 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 19.863 ; 19.661 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 11.066 ; 10.252 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 10.704 ; 9.942  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 12.242 ; 11.432 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 11.994 ; 11.193 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 7.355  ; 6.801  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 4.417  ; 4.711  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 5.272  ; 4.944  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 5.926  ; 5.572  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 6.631  ; 7.339  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 11.961 ; 11.365 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 9.506  ; 8.984  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 9.795  ; 9.728  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 8.956  ; 8.607  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 9.417  ; 9.420  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 11.374 ; 10.744 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 11.961 ; 11.365 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 10.081 ; 9.521  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 10.172 ; 9.546  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 8.584  ; 8.140  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 8.731  ; 8.182  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 9.061  ; 8.465  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 9.852  ; 9.191  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 9.152  ; 8.562  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 9.475  ; 8.828  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 9.338  ; 8.848  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 10.067 ; 9.268  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 7.201  ; 7.701  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 7.108  ; 6.462  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 5.115  ; 4.755  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 6.723  ; 6.180  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 20.100 ; 19.714 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 22.248 ; 21.550 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 7.240  ; 8.019  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.679  ; 5.240  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 9.446  ; 8.933  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 11.524 ; 10.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 8.340  ; 7.501  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 6.702  ; 6.062  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 15.944 ; 15.277 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 14.161 ; 13.656 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 14.564 ; 14.099 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 13.297 ; 12.893 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 14.841 ; 14.486 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 15.281 ; 14.832 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 14.665 ; 14.383 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 14.904 ; 14.510 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 14.783 ; 14.268 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 15.944 ; 15.183 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 13.747 ; 13.290 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 14.674 ; 14.266 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 13.495 ; 13.091 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 15.734 ; 15.277 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 16.739 ; 15.633 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 12.543 ; 11.799 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 16.739 ; 15.633 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 20.429 ; 18.968 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 30.105 ; 29.290 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 27.149 ; 26.459 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 25.126 ; 24.513 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 26.502 ; 25.892 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 26.700 ; 25.922 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 25.845 ; 24.592 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 28.692 ; 27.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 26.349 ; 25.677 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 26.036 ; 25.274 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 25.953 ; 24.751 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 27.432 ; 26.792 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 26.352 ; 25.850 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 27.983 ; 27.334 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 27.255 ; 26.261 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 27.830 ; 27.256 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 27.407 ; 26.579 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 30.105 ; 29.290 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 13.337 ; 12.623 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 14.465 ; 13.428 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 13.686 ; 13.228 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 8.765  ; 8.269  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 7.399  ; 6.679  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 16.995 ; 17.012 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;        ; 9.282  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;        ; 8.248  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;        ; 7.644  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;        ; 7.993  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;        ; 8.431  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;        ; 8.870  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;        ; 8.582  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;        ; 8.044  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;        ; 7.627  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;        ; 8.534  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;        ; 9.089  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;        ; 11.009 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;        ; 8.206  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;        ; 8.464  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;        ; 8.675  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 15.888 ; 15.223 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 15.695 ; 14.150 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 16.995 ; 17.012 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 17.451 ; 16.795 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 19.599 ; 18.631 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 12.808 ; 12.070 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 10.723 ; 10.212 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 10.851 ; 10.517 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 9.665  ; 9.289  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 11.061 ; 10.694 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 10.948 ; 10.493 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 11.375 ; 10.979 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 12.255 ; 11.861 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 11.910 ; 11.379 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 12.808 ; 12.070 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.771  ; 9.453  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.441 ; 11.125 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.434 ; 10.122 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.819 ; 11.451 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 13.318 ; 12.984 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;        ; 9.150  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 13.318 ; 12.984 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 17.008 ; 16.319 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 25.351 ; 24.536 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 22.396 ; 21.706 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 22.247 ; 21.042 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 22.172 ; 21.221 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 23.047 ; 22.269 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 22.456 ; 20.939 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 25.039 ; 24.071 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 22.696 ; 22.024 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 22.383 ; 21.621 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 23.297 ; 21.064 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 23.308 ; 22.668 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 22.699 ; 22.197 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 23.230 ; 22.581 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 22.502 ; 21.508 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 23.076 ; 22.502 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 23.471 ; 22.643 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 25.351 ; 24.536 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 10.523 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 11.651 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 17.523 ; 16.998 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 16.064 ; 15.437 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 15.775 ; 15.438 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 17.523 ; 16.998 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 8.606  ; 8.537  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 8.418  ; 8.123  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 8.606  ; 8.253  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 8.399  ; 8.537  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 8.554  ; 8.479  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 10.833 ; 10.153 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 10.833 ; 10.153 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 9.825  ; 9.540  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 8.360  ; 8.293  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 7.252  ; 6.833  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 9.376  ; 9.264  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 9.376  ; 9.264  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 8.355  ; 8.304  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 8.847  ; 8.994  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 9.271  ; 8.940  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 8.119  ; 9.100  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 17.238 ; 17.279 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 19.386 ; 19.115 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 7.364  ; 6.717  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 13.199 ; 12.489 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 11.215 ; 10.664 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.052  ; 8.918  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 10.521 ; 10.056 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 10.694 ; 10.327 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 11.294 ; 10.845 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 11.728 ; 10.576 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.772 ; 10.314 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 12.065 ; 11.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 13.199 ; 12.421 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 12.840 ; 11.383 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.713 ; 12.489 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.183 ; 9.853  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.708 ; 11.251 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 17.175 ; 15.740 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 8.432  ; 7.663  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 17.175 ; 15.740 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 20.865 ; 19.075 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 2.790  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.923 ; 25.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 25.199 ; 23.730 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 25.562 ; 24.072 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 26.224 ; 24.741 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 26.519 ; 25.442 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 26.281 ; 24.718 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 26.923 ; 25.274 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 25.381 ; 24.228 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 25.653 ; 24.469 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 26.296 ; 24.701 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 24.263 ; 23.277 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 23.279 ; 22.335 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 24.468 ; 23.819 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 24.480 ; 22.773 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 24.315 ; 23.741 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 25.467 ; 24.639 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 26.590 ; 25.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 11.406 ; 10.610 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 12.534 ; 11.415 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 9.829  ; 9.340  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 10.171 ; 9.961  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 12.718 ; 11.620 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 2.756  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;        ; 2.558  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;        ; 2.524  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 28.368 ; 27.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 20.359 ; 19.255 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 19.476 ; 18.781 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 18.812 ; 17.964 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 18.943 ; 18.139 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 19.542 ; 18.568 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 20.294 ; 19.092 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 19.891 ; 18.941 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 19.155 ; 18.326 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 18.871 ; 18.048 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 20.009 ; 19.071 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 20.523 ; 19.562 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 22.776 ; 21.372 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 19.988 ; 18.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 20.115 ; 19.185 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 20.675 ; 19.728 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 26.909 ; 26.282 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 26.425 ; 26.093 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 28.368 ; 27.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 28.181 ; 28.219 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 30.329 ; 30.055 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 23.934 ; 23.265 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 22.085 ; 21.580 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 22.631 ; 22.166 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 20.684 ; 20.280 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 22.146 ; 21.791 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 22.838 ; 22.389 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 23.165 ; 22.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 22.043 ; 21.518 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 23.060 ; 22.545 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 23.934 ; 23.173 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 20.901 ; 20.444 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 22.730 ; 22.322 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 21.402 ; 20.998 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 23.722 ; 23.265 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 24.856 ; 24.003 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 21.426 ; 20.454 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 24.856 ; 24.003 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 28.575 ; 27.338 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 35.928 ; 35.113 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 32.972 ; 32.282 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 33.460 ; 32.255 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 33.307 ; 31.935 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 33.602 ; 32.576 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 33.375 ; 32.314 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 34.515 ; 33.547 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 32.894 ; 31.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 32.736 ; 31.552 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 34.027 ; 32.552 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 33.255 ; 32.615 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 32.175 ; 31.673 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 33.806 ; 33.157 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 33.385 ; 32.091 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 33.653 ; 33.079 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 34.370 ; 33.542 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 35.928 ; 35.113 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 19.709 ; 18.823 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 19.513 ; 18.878 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 13.736 ; 13.836 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 9.661  ; 9.127  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 15.554 ; 15.101 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 14.095 ; 13.468 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 13.878 ; 13.469 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 15.554 ; 15.101 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 15.341 ; 15.310 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 17.489 ; 17.146 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 15.206 ; 13.843 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 15.206 ; 13.843 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 18.896 ; 17.178 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 25.733 ; 24.252 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 24.278 ; 22.560 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 24.372 ; 22.882 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 25.034 ; 23.551 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 25.329 ; 24.252 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 25.091 ; 23.528 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 25.733 ; 24.084 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 24.191 ; 23.038 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 24.463 ; 23.279 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 25.092 ; 23.511 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 23.238 ; 22.059 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 22.089 ; 20.773 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 23.046 ; 21.458 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 23.290 ; 21.787 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 22.764 ; 21.768 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 24.571 ; 23.743 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 23.857 ; 23.173 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 13.910 ; 13.519 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 13.901 ; 13.385 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 4.803  ; 4.543  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 8.957  ; 7.920  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 8.315  ; 7.546  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 5.798  ; 5.524  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 10.749 ; 10.218 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 10.749 ; 10.218 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 7.841  ; 6.990  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.904  ; 4.535  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 11.181 ; 10.219 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 14.431 ; 13.959 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 16.018 ; 15.188 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 16.263 ; 15.268 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 17.615 ; 16.452 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 19.039 ; 17.837 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 16.846 ; 15.847 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 18.812 ; 17.528 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 15.892 ; 14.947 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 15.870 ; 15.300 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 16.565 ; 15.953 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 15.950 ; 15.530 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 14.431 ; 14.163 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 14.815 ; 14.602 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 15.510 ; 15.132 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 14.600 ; 13.959 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 16.662 ; 15.911 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 15.223 ; 14.622 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 14.324 ; 13.714 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 5.139  ; 4.674  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 6.690  ; 6.241  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 7.024  ; 6.597  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 5.749  ; 5.287  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 6.855  ; 6.373  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 5.889  ; 5.446  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 6.431  ; 5.850  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 5.892  ; 5.510  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 6.167  ; 5.801  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 5.821  ; 5.442  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 6.438  ; 5.934  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 5.366  ; 5.049  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 7.829  ; 6.932  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 5.535  ; 4.966  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 5.623  ; 5.112  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 5.139  ; 4.674  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 5.156  ; 4.735  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 5.482  ; 5.058  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 6.345  ; 5.613  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 6.755  ; 6.082  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 6.345  ; 5.755  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 7.858  ; 7.198  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 7.488  ; 6.825  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 5.782  ; 5.407  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 3.922  ; 4.208  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 4.754  ; 4.434  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 5.381  ; 5.037  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 4.968  ; 5.319  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 5.569  ; 5.188  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 6.908  ; 6.216  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 6.535  ; 5.933  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 6.457  ; 5.949  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 6.283  ; 5.890  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 7.252  ; 6.916  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 9.156  ; 8.442  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 7.178  ; 6.588  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 6.655  ; 6.015  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 5.569  ; 5.188  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 5.848  ; 5.297  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 6.026  ; 5.500  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 6.717  ; 6.137  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 6.184  ; 5.597  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 6.333  ; 5.776  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 6.293  ; 5.867  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 6.963  ; 6.224  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 5.921  ; 6.719  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 5.949  ; 5.388  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 4.598  ; 4.247  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 5.595  ; 5.119  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 6.928  ; 6.382  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 9.223  ; 8.387  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 5.999  ; 6.704  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.144  ; 4.718  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 7.460  ; 6.864  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 6.824  ; 5.999  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 7.781  ; 6.957  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 6.119  ; 5.501  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 8.851  ; 8.459  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 9.473  ; 8.994  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.477  ; 9.064  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 8.851  ; 8.459  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 9.416  ; 9.116  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 9.962  ; 9.502  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.033 ; 9.604  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.298 ; 9.788  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 9.685  ; 9.191  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 11.940 ; 11.161 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.273  ; 8.912  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 10.552 ; 10.146 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 9.762  ; 9.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.604 ; 11.218 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 8.943  ; 8.779  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 8.943  ; 8.779  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 10.193 ; 9.475  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 11.503 ; 10.479 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.970  ; 7.072  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.397  ; 7.434  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.094  ; 7.072  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 9.803  ; 8.616  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 9.933  ; 9.313  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 9.747  ; 9.117  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 10.999 ; 9.822  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.740  ; 7.960  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.802  ; 7.935  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 9.572  ; 8.857  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.470  ; 8.540  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.375  ; 7.628  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.587  ; 7.659  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.134  ; 8.513  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.251  ; 7.502  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 9.576  ; 8.787  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.970  ; 7.203  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 9.066  ; 8.527  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 10.112 ; 9.237  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 11.079 ; 10.892 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 7.436  ; 6.797  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 6.789  ; 6.094  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 10.194 ; 7.002  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;        ; 8.599  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;        ; 7.561  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;        ; 7.002  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;        ; 7.252  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;        ; 7.786  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;        ; 8.137  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;        ; 7.862  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;        ; 7.297  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;        ; 7.006  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;        ; 7.766  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;        ; 8.377  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;        ; 10.266 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;        ; 7.502  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;        ; 7.748  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;        ; 7.944  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 10.687 ; 8.716  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 10.194 ; 9.196  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 11.460 ; 9.297  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 12.197 ; 11.593 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 14.349 ; 13.429 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 8.727  ; 8.330  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 9.468  ; 8.935  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.156  ; 8.678  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 8.727  ; 8.330  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 9.370  ; 8.881  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 9.788  ; 9.323  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.208 ; 9.787  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.059 ; 9.544  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 9.765  ; 9.092  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 11.954 ; 11.170 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 8.984  ; 8.603  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 10.637 ; 10.231 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 9.645  ; 9.241  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 10.928 ; 10.488 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 11.569 ; 8.454  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;        ; 8.454  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 11.569 ; 10.759 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 11.857 ; 13.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 9.253  ; 8.745  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 9.754  ; 9.308  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 9.426  ; 8.987  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 9.784  ; 9.427  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.408 ; 9.765  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 9.253  ; 8.745  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.556 ; 10.617 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 9.554  ; 8.979  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 9.780  ; 9.148  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 9.684  ; 9.162  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.620  ; 9.095  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.538  ; 9.450  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.991  ; 9.416  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.772 ; 9.964  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.405 ; 9.548  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.024 ; 9.483  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.825 ; 10.181 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 9.420  ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 10.466 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 10.867 ; 10.509 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 11.473 ; 10.855 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 10.867 ; 10.509 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 12.582 ; 11.660 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 6.050  ; 5.484  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 6.107  ; 5.485  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 6.932  ; 6.191  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 6.050  ; 5.484  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 6.303  ; 5.641  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 5.915  ; 5.502  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 9.200  ; 8.156  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 7.610  ; 6.936  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 5.915  ; 5.502  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 6.494  ; 6.002  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 6.153  ; 5.701  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 7.232  ; 6.534  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 6.804  ; 6.223  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 6.153  ; 5.701  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 6.934  ; 6.276  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 7.400  ; 8.345  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 12.787 ; 13.362 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 14.939 ; 15.198 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 5.872  ; 5.452  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 5.262  ; 5.086  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 6.876  ; 6.146  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 5.919  ; 5.379  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 6.075  ; 5.560  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 6.299  ; 5.786  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 6.550  ; 5.974  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 6.095  ; 5.439  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 6.530  ; 5.953  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 7.128  ; 6.437  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 8.040  ; 7.143  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 6.325  ; 5.941  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 6.306  ; 5.957  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 5.262  ; 5.086  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.570  ; 5.346  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 5.915  ; 5.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 5.915  ; 5.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 6.179  ; 5.525  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 6.822  ; 6.677  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 2.375  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 5.212  ; 4.707  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 5.227  ; 4.966  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 5.493  ; 5.276  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.632  ; 5.247  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.023  ; 5.636  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 5.212  ; 4.707  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.517  ; 6.581  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.516  ; 4.944  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.737  ; 5.108  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.205  ; 5.660  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.009  ; 5.558  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 5.724  ; 5.314  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 5.853  ; 5.442  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.124  ; 5.831  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 5.963  ; 5.576  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.099  ; 5.615  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 6.619  ; 6.173  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 5.459  ; 5.196  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 5.928  ; 5.498  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 5.856  ; 5.670  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 5.201  ; 5.721  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 10.271 ; 9.356  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 2.342  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;        ; 2.148  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;        ; 2.114  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 7.825  ; 7.166  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 9.633  ; 8.756  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 8.882  ; 8.204  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 8.018  ; 7.352  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 8.237  ; 7.531  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 8.747  ; 7.816  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 9.305  ; 8.273  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 8.738  ; 7.993  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 8.121  ; 7.434  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 7.825  ; 7.166  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 8.869  ; 8.068  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 9.113  ; 8.421  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 11.612 ; 10.363 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 8.508  ; 7.637  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 8.671  ; 7.886  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 9.675  ; 8.871  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 10.408 ; 9.639  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 9.636  ; 8.717  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 11.345 ; 10.222 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 11.603 ; 11.706 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 13.755 ; 13.542 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 9.222  ; 8.771  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 9.625  ; 9.092  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.799  ; 9.321  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 9.222  ; 8.771  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 9.649  ; 9.160  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 9.818  ; 9.353  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.344 ; 9.923  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.190 ; 9.675  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 9.902  ; 9.229  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 11.883 ; 11.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.286  ; 8.905  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 10.681 ; 10.275 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 9.742  ; 9.338  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 11.063 ; 10.623 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 9.557  ; 8.746  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 9.557  ; 8.746  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 10.711 ; 9.666  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 11.786 ; 10.494 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 9.121  ; 8.200  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 9.623  ; 8.846  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 9.889  ; 8.814  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 10.307 ; 10.065 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.419 ; 9.988  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 9.896  ; 9.388  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.199 ; 11.260 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 10.197 ; 9.622  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 10.414 ; 9.419  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 10.320 ; 9.762  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 10.256 ; 9.695  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.822  ; 8.744  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.949  ; 8.869  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.520 ; 9.709  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.121  ; 8.200  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.609 ; 9.401  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.033 ; 9.244  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 9.357  ; 8.529  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 9.325  ; 8.394  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 9.888  ; 10.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 8.969  ; 8.451  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 10.580 ; 9.535  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 11.226 ; 10.581 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 10.580 ; 9.535  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 12.000 ; 11.480 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 12.421 ; 12.650 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 14.573 ; 14.486 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 12.857 ; 11.492 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 12.857 ; 11.492 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 13.383 ; 12.058 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 10.800 ; 9.895  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.285 ; 10.929 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 11.197 ; 10.018 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.594 ; 11.241 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.100 ; 10.994 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 13.764 ; 12.516 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 14.831 ; 13.632 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.645 ; 11.510 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.581 ; 11.465 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 14.430 ; 12.728 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 13.605 ; 12.187 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 13.266 ; 11.813 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 11.359 ; 10.321 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 13.083 ; 11.781 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.800 ; 9.895  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.742 ; 11.613 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 12.487 ; 11.537 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 10.954 ; 10.093 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 10.899 ; 9.949  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 4.295  ; 4.042  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 8.369  ; 7.357  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 7.674  ; 6.930  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 4.280  ; 3.954  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 6.358  ; 5.903  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 6.358  ; 5.903  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 7.218  ; 6.396  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.400  ; 4.041  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------+
; Propagation Delay                                               ;
+--------------+--------------+--------+--------+--------+--------+
; Input Port   ; Output Port  ; RR     ; RF     ; FR     ; FF     ;
+--------------+--------------+--------+--------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 20.326 ; 18.713 ; 20.524 ; 18.798 ;
; CONFIG[1]    ; RAM_DATA[12] ; 11.288 ; 11.053 ; 11.644 ; 10.677 ;
; CONFIG[1]    ; RAM_DATA[13] ; 10.940 ; 10.786 ; 11.207 ; 10.515 ;
; CONFIG[1]    ; RAM_DATA[14] ; 10.491 ; 10.161 ; 10.574 ; 10.100 ;
; CONFIG[1]    ; RAM_DATA[15] ; 10.672 ; 11.616 ; 12.128 ; 10.232 ;
; CONFIG[2]    ; RAM_DATA[7]  ; 19.995 ; 18.383 ; 20.191 ; 18.464 ;
; CONFIG[2]    ; RAM_DATA[12] ; 10.946 ; 10.711 ; 11.371 ; 10.404 ;
; CONFIG[2]    ; RAM_DATA[13] ; 10.598 ; 10.444 ; 10.934 ; 10.242 ;
; CONFIG[2]    ; RAM_DATA[14] ; 10.149 ; 9.819  ; 10.301 ; 9.827  ;
; CONFIG[2]    ; RAM_DATA[15] ; 10.330 ; 11.274 ; 11.855 ; 9.959  ;
; CONFIG[3]    ; ADR[16]      ; 20.671 ; 20.044 ; 20.275 ; 19.648 ;
; CONFIG[3]    ; ADR[17]      ; 20.447 ; 19.855 ; 19.742 ; 19.459 ;
; CONFIG[3]    ; ADR[18]      ; 22.130 ; 21.764 ; 21.734 ; 21.059 ;
; CONFIG[3]    ; ADR[22]      ; 10.597 ;        ;        ; 10.201 ;
; CONFIG[3]    ; FLASH_CEn    ; 22.203 ; 21.981 ; 21.498 ; 21.585 ;
; CONFIG[3]    ; FLASH_OEn    ; 24.351 ; 23.817 ; 23.646 ; 23.421 ;
; CONFIG[3]    ; RAM_BA[1]    ; 18.675 ; 17.938 ; 18.390 ; 17.299 ;
; CONFIG[3]    ; RAM_CASn     ; 22.365 ; 21.273 ; 22.109 ; 20.634 ;
; CONFIG[3]    ; RAM_DATA[0]  ; 26.872 ; 25.513 ; 26.167 ; 25.117 ;
; CONFIG[3]    ; RAM_DATA[1]  ; 27.222 ; 26.017 ; 26.826 ; 25.621 ;
; CONFIG[3]    ; RAM_DATA[2]  ; 27.069 ; 25.697 ; 26.673 ; 25.301 ;
; CONFIG[3]    ; RAM_DATA[3]  ; 27.524 ; 26.338 ; 26.968 ; 25.942 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 27.208 ; 26.076 ; 26.741 ; 25.680 ;
; CONFIG[3]    ; RAM_DATA[5]  ; 28.043 ; 26.823 ; 27.641 ; 26.427 ;
; CONFIG[3]    ; RAM_DATA[6]  ; 26.656 ; 25.472 ; 26.260 ; 25.076 ;
; CONFIG[3]    ; RAM_DATA[7]  ; 26.498 ; 25.314 ; 26.102 ; 24.918 ;
; CONFIG[3]    ; RAM_DATA[8]  ; 28.049 ; 26.314 ; 27.344 ; 25.918 ;
; CONFIG[3]    ; RAM_DATA[9]  ; 26.927 ; 25.961 ; 26.531 ; 25.565 ;
; CONFIG[3]    ; RAM_DATA[10] ; 25.314 ; 24.729 ; 24.918 ; 24.333 ;
; CONFIG[3]    ; RAM_DATA[11] ; 26.590 ; 25.577 ; 26.194 ; 25.181 ;
; CONFIG[3]    ; RAM_DATA[12] ; 27.147 ; 25.853 ; 26.751 ; 25.457 ;
; CONFIG[3]    ; RAM_DATA[13] ; 26.435 ; 25.439 ; 25.888 ; 24.892 ;
; CONFIG[3]    ; RAM_DATA[14] ; 28.223 ; 27.395 ; 27.736 ; 26.908 ;
; CONFIG[3]    ; RAM_DATA[15] ; 27.507 ; 26.823 ; 27.022 ; 26.338 ;
; CONFIG[4]    ; ADR[16]      ; 20.617 ; 19.990 ; 20.007 ; 19.380 ;
; CONFIG[4]    ; ADR[17]      ; 20.393 ; 19.801 ; 19.474 ; 19.191 ;
; CONFIG[4]    ; ADR[18]      ; 22.076 ; 21.710 ; 21.466 ; 20.791 ;
; CONFIG[4]    ; ADR[21]      ; 11.013 ;        ;        ; 10.591 ;
; CONFIG[4]    ; FLASH_CEn    ; 22.149 ; 21.927 ; 21.230 ; 21.317 ;
; CONFIG[4]    ; FLASH_OEn    ; 24.297 ; 23.763 ; 23.378 ; 23.153 ;
; CONFIG[4]    ; RAM_BA[1]    ; 18.621 ; 17.884 ; 18.122 ; 17.031 ;
; CONFIG[4]    ; RAM_CASn     ; 22.311 ; 21.219 ; 21.841 ; 20.366 ;
; CONFIG[4]    ; RAM_DATA[0]  ; 26.818 ; 25.459 ; 25.899 ; 24.849 ;
; CONFIG[4]    ; RAM_DATA[1]  ; 27.168 ; 25.963 ; 26.558 ; 25.353 ;
; CONFIG[4]    ; RAM_DATA[2]  ; 27.015 ; 25.643 ; 26.405 ; 25.033 ;
; CONFIG[4]    ; RAM_DATA[3]  ; 27.470 ; 26.284 ; 26.700 ; 25.674 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 27.154 ; 26.022 ; 26.473 ; 25.412 ;
; CONFIG[4]    ; RAM_DATA[5]  ; 27.989 ; 26.769 ; 27.373 ; 26.159 ;
; CONFIG[4]    ; RAM_DATA[6]  ; 26.602 ; 25.418 ; 25.992 ; 24.808 ;
; CONFIG[4]    ; RAM_DATA[7]  ; 26.444 ; 25.260 ; 25.834 ; 24.650 ;
; CONFIG[4]    ; RAM_DATA[8]  ; 27.995 ; 26.260 ; 27.076 ; 25.650 ;
; CONFIG[4]    ; RAM_DATA[9]  ; 26.873 ; 25.907 ; 26.263 ; 25.297 ;
; CONFIG[4]    ; RAM_DATA[10] ; 25.260 ; 24.675 ; 24.650 ; 24.065 ;
; CONFIG[4]    ; RAM_DATA[11] ; 26.536 ; 25.523 ; 25.926 ; 24.913 ;
; CONFIG[4]    ; RAM_DATA[12] ; 27.093 ; 25.799 ; 26.483 ; 25.189 ;
; CONFIG[4]    ; RAM_DATA[13] ; 26.381 ; 25.385 ; 25.620 ; 24.624 ;
; CONFIG[4]    ; RAM_DATA[14] ; 28.169 ; 27.341 ; 27.468 ; 26.640 ;
; CONFIG[4]    ; RAM_DATA[15] ; 27.453 ; 26.769 ; 26.754 ; 26.070 ;
; CONFIG[5]    ; ADR[16]      ; 20.860 ; 20.233 ; 20.241 ; 19.614 ;
; CONFIG[5]    ; ADR[17]      ; 20.636 ; 20.044 ; 19.708 ; 19.425 ;
; CONFIG[5]    ; ADR[18]      ; 22.319 ; 21.953 ; 21.700 ; 21.025 ;
; CONFIG[5]    ; ADR[20]      ; 9.550  ;        ;        ; 9.197  ;
; CONFIG[5]    ; FLASH_CEn    ; 22.392 ; 22.170 ; 21.464 ; 21.551 ;
; CONFIG[5]    ; FLASH_OEn    ; 24.540 ; 24.006 ; 23.612 ; 23.387 ;
; CONFIG[5]    ; RAM_BA[1]    ; 18.864 ; 18.127 ; 18.356 ; 17.265 ;
; CONFIG[5]    ; RAM_CASn     ; 22.554 ; 21.462 ; 22.075 ; 20.600 ;
; CONFIG[5]    ; RAM_DATA[0]  ; 27.061 ; 25.702 ; 26.133 ; 25.083 ;
; CONFIG[5]    ; RAM_DATA[1]  ; 27.411 ; 26.206 ; 26.792 ; 25.587 ;
; CONFIG[5]    ; RAM_DATA[2]  ; 27.258 ; 25.886 ; 26.639 ; 25.267 ;
; CONFIG[5]    ; RAM_DATA[3]  ; 27.713 ; 26.527 ; 26.934 ; 25.908 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 27.397 ; 26.265 ; 26.707 ; 25.646 ;
; CONFIG[5]    ; RAM_DATA[5]  ; 28.232 ; 27.012 ; 27.607 ; 26.393 ;
; CONFIG[5]    ; RAM_DATA[6]  ; 26.845 ; 25.661 ; 26.226 ; 25.042 ;
; CONFIG[5]    ; RAM_DATA[7]  ; 26.687 ; 25.503 ; 26.068 ; 24.884 ;
; CONFIG[5]    ; RAM_DATA[8]  ; 28.238 ; 26.503 ; 27.310 ; 25.884 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 27.116 ; 26.150 ; 26.497 ; 25.531 ;
; CONFIG[5]    ; RAM_DATA[10] ; 25.503 ; 24.918 ; 24.884 ; 24.299 ;
; CONFIG[5]    ; RAM_DATA[11] ; 26.779 ; 25.766 ; 26.160 ; 25.147 ;
; CONFIG[5]    ; RAM_DATA[12] ; 27.336 ; 26.042 ; 26.717 ; 25.423 ;
; CONFIG[5]    ; RAM_DATA[13] ; 26.624 ; 25.628 ; 25.854 ; 24.858 ;
; CONFIG[5]    ; RAM_DATA[14] ; 28.412 ; 27.584 ; 27.702 ; 26.874 ;
; CONFIG[5]    ; RAM_DATA[15] ; 27.696 ; 27.012 ; 26.988 ; 26.304 ;
; CONFIG[6]    ; ADR[19]      ; 9.930  ;        ;        ; 9.493  ;
; DATA[0]      ; RAM_DATA[0]  ; 14.192 ;        ;        ; 13.583 ;
; DATA[1]      ; RAM_DATA[1]  ; 14.757 ;        ;        ; 13.817 ;
; DATA[2]      ; RAM_DATA[2]  ; 15.832 ;        ;        ; 14.747 ;
; DATA[3]      ; RAM_DATA[3]  ; 17.110 ;        ;        ; 16.172 ;
; DATA[4]      ; RAM_DATA[4]  ; 15.367 ;        ;        ; 14.458 ;
; DATA[5]      ; RAM_DATA[5]  ; 15.755 ;        ;        ; 14.754 ;
; DATA[6]      ; RAM_DATA[6]  ; 15.525 ;        ;        ; 14.683 ;
; DATA[7]      ; RAM_DATA[7]  ; 16.009 ;        ;        ; 15.100 ;
; DATA[8]      ; RAM_DATA[8]  ; 16.342 ;        ;        ; 15.348 ;
; DATA[9]      ; RAM_DATA[9]  ; 17.898 ;        ;        ; 16.562 ;
; DATA[10]     ; RAM_DATA[10] ; 15.118 ;        ;        ; 14.234 ;
; DATA[11]     ; RAM_DATA[11] ; 16.388 ;        ;        ; 15.139 ;
; DATA[12]     ; RAM_DATA[12] ; 17.275 ;        ;        ; 16.008 ;
; DATA[13]     ; RAM_DATA[13] ; 13.183 ;        ;        ; 12.367 ;
; DATA[14]     ; RAM_DATA[14] ; 13.461 ;        ;        ; 12.642 ;
; DATA[15]     ; RAM_DATA[15] ; 12.491 ;        ;        ; 11.934 ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 16.733 ;        ;        ; 15.690 ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 17.014 ;        ;        ; 15.672 ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 19.157 ;        ;        ; 17.341 ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 19.244 ;        ;        ; 17.669 ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 16.856 ;        ;        ; 15.615 ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 17.710 ;        ;        ; 16.251 ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 16.508 ;        ;        ; 15.371 ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 16.775 ;        ;        ; 15.553 ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 18.205 ;        ;        ; 16.783 ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 19.984 ;        ;        ; 18.212 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 15.931 ;        ;        ; 14.617 ;
; RAM_DATA[11] ; RAM_DATA[11] ; 16.249 ;        ;        ; 14.913 ;
; RAM_DATA[12] ; RAM_DATA[12] ; 14.910 ;        ;        ; 13.979 ;
; RAM_DATA[13] ; RAM_DATA[13] ; 13.880 ; 12.884 ; 13.840 ; 12.838 ;
; RAM_DATA[14] ; RAM_DATA[14] ; 16.337 ; 15.509 ; 16.283 ; 15.455 ;
; RAM_DATA[15] ; RAM_DATA[15] ; 19.327 ; 18.643 ; 18.734 ; 18.050 ;
; RESET_COREn  ; RAM_CKE      ; 4.616  ;        ;        ; 4.945  ;
; RESETn       ; KEYB_TxD     ; 9.519  ; 9.519  ; 9.389  ; 9.290  ;
+--------------+--------------+--------+--------+--------+--------+


+-----------------------------------------------------------------+
; Minimum Propagation Delay                                       ;
+--------------+--------------+--------+--------+--------+--------+
; Input Port   ; Output Port  ; RR     ; RF     ; FR     ; FF     ;
+--------------+--------------+--------+--------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 19.639 ; 18.062 ; 19.795 ; 18.156 ;
; CONFIG[1]    ; RAM_DATA[12] ; 10.964 ; 10.715 ; 11.269 ; 10.370 ;
; CONFIG[1]    ; RAM_DATA[13] ; 10.571 ; 10.398 ; 10.822 ; 10.137 ;
; CONFIG[1]    ; RAM_DATA[14] ; 10.200 ; 9.877  ; 10.276 ; 9.816  ;
; CONFIG[1]    ; RAM_DATA[15] ; 10.373 ; 11.182 ; 11.693 ; 9.942  ;
; CONFIG[2]    ; RAM_DATA[7]  ; 19.314 ; 17.743 ; 19.474 ; 17.834 ;
; CONFIG[2]    ; RAM_DATA[12] ; 10.637 ; 10.388 ; 11.012 ; 10.113 ;
; CONFIG[2]    ; RAM_DATA[13] ; 10.244 ; 10.071 ; 10.565 ; 9.880  ;
; CONFIG[2]    ; RAM_DATA[14] ; 9.873  ; 9.550  ; 10.019 ; 9.559  ;
; CONFIG[2]    ; RAM_DATA[15] ; 10.046 ; 10.855 ; 11.436 ; 9.685  ;
; CONFIG[3]    ; ADR[16]      ; 16.463 ; 15.810 ; 16.120 ; 15.500 ;
; CONFIG[3]    ; ADR[17]      ; 15.845 ; 14.967 ; 15.474 ; 14.924 ;
; CONFIG[3]    ; ADR[18]      ; 12.845 ; 18.935 ; 18.928 ; 11.925 ;
; CONFIG[3]    ; ADR[22]      ; 10.299 ;        ;        ; 9.916  ;
; CONFIG[3]    ; FLASH_CEn    ; 15.202 ; 16.478 ; 16.515 ; 14.874 ;
; CONFIG[3]    ; FLASH_OEn    ; 17.354 ; 18.314 ; 18.667 ; 16.710 ;
; CONFIG[3]    ; RAM_BA[1]    ; 15.942 ; 13.731 ; 14.106 ; 14.670 ;
; CONFIG[3]    ; RAM_CASn     ; 16.639 ; 16.467 ; 16.434 ; 15.845 ;
; CONFIG[3]    ; RAM_DATA[0]  ; 17.459 ; 16.021 ; 16.814 ; 16.465 ;
; CONFIG[3]    ; RAM_DATA[1]  ; 17.395 ; 16.304 ; 17.308 ; 16.417 ;
; CONFIG[3]    ; RAM_DATA[2]  ; 18.609 ; 16.982 ; 18.068 ; 17.406 ;
; CONFIG[3]    ; RAM_DATA[3]  ; 19.401 ; 17.286 ; 18.181 ; 18.295 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 18.066 ; 16.586 ; 17.415 ; 17.105 ;
; CONFIG[3]    ; RAM_DATA[5]  ; 18.445 ; 17.112 ; 18.141 ; 17.388 ;
; CONFIG[3]    ; RAM_DATA[6]  ; 18.104 ; 17.005 ; 17.845 ; 17.434 ;
; CONFIG[3]    ; RAM_DATA[7]  ; 17.518 ; 16.430 ; 17.102 ; 16.850 ;
; CONFIG[3]    ; RAM_DATA[8]  ; 18.667 ; 17.145 ; 18.184 ; 17.654 ;
; CONFIG[3]    ; RAM_DATA[9]  ; 18.554 ; 17.189 ; 17.993 ; 17.083 ;
; CONFIG[3]    ; RAM_DATA[10] ; 17.273 ; 16.010 ; 16.854 ; 16.270 ;
; CONFIG[3]    ; RAM_DATA[11] ; 17.324 ; 16.150 ; 16.910 ; 16.600 ;
; CONFIG[3]    ; RAM_DATA[12] ; 17.761 ; 16.117 ; 16.965 ; 16.700 ;
; CONFIG[3]    ; RAM_DATA[13] ; 15.189 ; 14.654 ; 15.365 ; 14.724 ;
; CONFIG[3]    ; RAM_DATA[14] ; 17.043 ; 16.327 ; 17.427 ; 16.676 ;
; CONFIG[3]    ; RAM_DATA[15] ; 15.825 ; 15.265 ; 15.988 ; 15.387 ;
; CONFIG[4]    ; ADR[16]      ; 16.437 ; 15.784 ; 15.915 ; 15.295 ;
; CONFIG[4]    ; ADR[17]      ; 15.819 ; 14.941 ; 15.269 ; 14.719 ;
; CONFIG[4]    ; ADR[18]      ; 12.926 ; 18.924 ; 18.724 ; 11.884 ;
; CONFIG[4]    ; ADR[21]      ; 10.671 ;        ;        ; 10.261 ;
; CONFIG[4]    ; FLASH_CEn    ; 15.283 ; 16.559 ; 16.474 ; 14.833 ;
; CONFIG[4]    ; FLASH_OEn    ; 17.435 ; 18.395 ; 18.626 ; 16.669 ;
; CONFIG[4]    ; RAM_BA[1]    ; 15.931 ; 13.705 ; 13.901 ; 14.466 ;
; CONFIG[4]    ; RAM_CASn     ; 16.613 ; 16.455 ; 16.228 ; 15.640 ;
; CONFIG[4]    ; RAM_DATA[0]  ; 17.433 ; 15.995 ; 16.609 ; 16.260 ;
; CONFIG[4]    ; RAM_DATA[1]  ; 17.476 ; 16.278 ; 17.103 ; 16.376 ;
; CONFIG[4]    ; RAM_DATA[2]  ; 18.596 ; 16.956 ; 17.863 ; 17.365 ;
; CONFIG[4]    ; RAM_DATA[3]  ; 19.482 ; 17.260 ; 17.976 ; 18.254 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 18.147 ; 16.560 ; 17.210 ; 17.064 ;
; CONFIG[4]    ; RAM_DATA[5]  ; 18.419 ; 17.086 ; 17.936 ; 17.183 ;
; CONFIG[4]    ; RAM_DATA[6]  ; 18.078 ; 16.979 ; 17.640 ; 17.229 ;
; CONFIG[4]    ; RAM_DATA[7]  ; 17.492 ; 16.404 ; 16.897 ; 16.645 ;
; CONFIG[4]    ; RAM_DATA[8]  ; 18.748 ; 17.119 ; 17.979 ; 17.613 ;
; CONFIG[4]    ; RAM_DATA[9]  ; 18.635 ; 17.163 ; 17.788 ; 17.042 ;
; CONFIG[4]    ; RAM_DATA[10] ; 17.354 ; 15.984 ; 16.649 ; 16.065 ;
; CONFIG[4]    ; RAM_DATA[11] ; 17.298 ; 16.124 ; 16.705 ; 16.395 ;
; CONFIG[4]    ; RAM_DATA[12] ; 17.842 ; 16.091 ; 16.760 ; 16.659 ;
; CONFIG[4]    ; RAM_DATA[13] ; 15.270 ; 14.735 ; 15.324 ; 14.683 ;
; CONFIG[4]    ; RAM_DATA[14] ; 17.124 ; 16.408 ; 17.386 ; 16.635 ;
; CONFIG[4]    ; RAM_DATA[15] ; 15.906 ; 15.346 ; 15.947 ; 15.346 ;
; CONFIG[5]    ; ADR[16]      ; 16.670 ; 16.017 ; 16.140 ; 15.520 ;
; CONFIG[5]    ; ADR[17]      ; 16.052 ; 15.174 ; 15.494 ; 14.944 ;
; CONFIG[5]    ; ADR[18]      ; 17.537 ; 19.195 ; 18.994 ; 16.843 ;
; CONFIG[5]    ; ADR[20]      ; 9.266  ;        ;        ; 8.923  ;
; CONFIG[5]    ; FLASH_CEn    ; 16.920 ; 17.818 ; 17.452 ; 16.596 ;
; CONFIG[5]    ; FLASH_OEn    ; 19.072 ; 19.654 ; 19.604 ; 18.432 ;
; CONFIG[5]    ; RAM_BA[1]    ; 16.202 ; 13.938 ; 14.126 ; 14.736 ;
; CONFIG[5]    ; RAM_CASn     ; 16.846 ; 16.729 ; 16.502 ; 15.865 ;
; CONFIG[5]    ; RAM_DATA[0]  ; 17.666 ; 16.228 ; 16.834 ; 16.485 ;
; CONFIG[5]    ; RAM_DATA[1]  ; 18.568 ; 16.511 ; 17.328 ; 17.467 ;
; CONFIG[5]    ; RAM_DATA[2]  ; 18.829 ; 17.189 ; 18.088 ; 17.632 ;
; CONFIG[5]    ; RAM_DATA[3]  ; 19.760 ; 17.493 ; 18.201 ; 18.622 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 18.383 ; 16.793 ; 17.435 ; 17.314 ;
; CONFIG[5]    ; RAM_DATA[5]  ; 18.652 ; 17.319 ; 18.161 ; 17.408 ;
; CONFIG[5]    ; RAM_DATA[6]  ; 18.311 ; 17.212 ; 17.865 ; 17.454 ;
; CONFIG[5]    ; RAM_DATA[7]  ; 17.725 ; 16.637 ; 17.122 ; 16.870 ;
; CONFIG[5]    ; RAM_DATA[8]  ; 19.852 ; 17.352 ; 18.204 ; 18.341 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 19.087 ; 17.396 ; 18.013 ; 17.562 ;
; CONFIG[5]    ; RAM_DATA[10] ; 17.654 ; 16.217 ; 16.874 ; 16.290 ;
; CONFIG[5]    ; RAM_DATA[11] ; 17.531 ; 16.357 ; 16.930 ; 16.620 ;
; CONFIG[5]    ; RAM_DATA[12] ; 18.177 ; 16.324 ; 16.985 ; 17.066 ;
; CONFIG[5]    ; RAM_DATA[13] ; 16.649 ; 16.114 ; 16.471 ; 15.909 ;
; CONFIG[5]    ; RAM_DATA[14] ; 18.449 ; 17.660 ; 18.273 ; 17.484 ;
; CONFIG[5]    ; RAM_DATA[15] ; 17.285 ; 16.725 ; 17.173 ; 16.572 ;
; CONFIG[6]    ; ADR[19]      ; 9.631  ;        ;        ; 9.207  ;
; DATA[0]      ; RAM_DATA[0]  ; 11.478 ;        ;        ; 10.899 ;
; DATA[1]      ; RAM_DATA[1]  ; 11.346 ;        ;        ; 10.729 ;
; DATA[2]      ; RAM_DATA[2]  ; 12.729 ;        ;        ; 11.959 ;
; DATA[3]      ; RAM_DATA[3]  ; 12.986 ;        ;        ; 12.299 ;
; DATA[4]      ; RAM_DATA[4]  ; 12.149 ;        ;        ; 11.508 ;
; DATA[5]      ; RAM_DATA[5]  ; 12.860 ;        ;        ; 12.107 ;
; DATA[6]      ; RAM_DATA[6]  ; 12.232 ;        ;        ; 11.827 ;
; DATA[7]      ; RAM_DATA[7]  ; 11.675 ;        ;        ; 11.246 ;
; DATA[8]      ; RAM_DATA[8]  ; 12.191 ;        ;        ; 11.558 ;
; DATA[9]      ; RAM_DATA[9]  ; 12.788 ;        ;        ; 12.209 ;
; DATA[10]     ; RAM_DATA[10] ; 11.376 ;        ;        ; 10.896 ;
; DATA[11]     ; RAM_DATA[11] ; 11.483 ;        ;        ; 10.972 ;
; DATA[12]     ; RAM_DATA[12] ; 14.609 ;        ;        ; 13.731 ;
; DATA[13]     ; RAM_DATA[13] ; 11.869 ;        ;        ; 11.270 ;
; DATA[14]     ; RAM_DATA[14] ; 12.930 ;        ;        ; 12.118 ;
; DATA[15]     ; RAM_DATA[15] ; 12.079 ;        ;        ; 11.530 ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 16.137 ;        ;        ; 15.106 ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 16.408 ;        ;        ; 15.110 ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 18.452 ;        ;        ; 16.679 ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 18.495 ;        ;        ; 16.960 ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 16.261 ;        ;        ; 15.069 ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 17.168 ;        ;        ; 15.739 ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 15.925 ;        ;        ; 14.826 ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 16.178 ;        ;        ; 15.005 ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 17.479 ;        ;        ; 16.090 ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 19.183 ;        ;        ; 17.464 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 15.376 ;        ;        ; 14.107 ;
; RAM_DATA[11] ; RAM_DATA[11] ; 15.666 ;        ;        ; 14.365 ;
; RAM_DATA[12] ; RAM_DATA[12] ; 14.356 ;        ;        ; 13.445 ;
; RAM_DATA[13] ; RAM_DATA[13] ; 13.447 ; 12.483 ; 13.407 ; 12.438 ;
; RAM_DATA[14] ; RAM_DATA[14] ; 15.337 ; 14.548 ; 15.276 ; 14.487 ;
; RAM_DATA[15] ; RAM_DATA[15] ; 18.279 ; 17.596 ; 17.682 ; 16.999 ;
; RESET_COREn  ; RAM_CKE      ; 4.562  ;        ;        ; 4.878  ;
; RESETn       ; KEYB_TxD     ; 8.941  ; 8.941  ; 8.948  ; 8.817  ;
+--------------+--------------+--------+--------+--------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 10.147 ; 10.147 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 10.147 ; 10.147 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 10.771 ; 10.771 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 10.771 ; 10.771 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 10.771 ; 10.771 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 10.993 ; 10.993 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 10.993 ; 10.993 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 11.198 ; 11.198 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 11.198 ; 11.198 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 11.145 ; 11.145 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 11.145 ; 11.145 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 11.155 ; 11.155 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 11.154 ; 11.154 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 11.154 ; 11.154 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 11.154 ; 11.154 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 11.176 ; 11.176 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 11.186 ; 11.186 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 6.657  ; 6.657  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 6.454  ; 6.454  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 9.793  ; 9.793  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 9.264  ; 9.264  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 9.274  ; 9.274  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 19.044 ; 19.044 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 19.381 ; 19.381 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 19.381 ; 19.381 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 19.044 ; 19.044 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 19.411 ; 19.411 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 19.411 ; 19.411 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 19.411 ; 19.411 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 19.418 ; 19.418 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 19.408 ; 19.408 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 19.428 ; 19.428 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 19.428 ; 19.428 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 19.805 ; 19.805 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 19.777 ; 19.777 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 19.784 ; 19.784 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 19.784 ; 19.784 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 19.804 ; 19.804 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 20.169 ; 20.169 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 9.398  ; 9.398  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 9.398  ; 9.398  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 8.898  ; 8.898  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 6.888  ; 6.888  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 16.395 ; 16.395 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 16.732 ; 16.732 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 16.732 ; 16.732 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 16.395 ; 16.395 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 16.762 ; 16.762 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 16.762 ; 16.762 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 16.762 ; 16.762 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 16.769 ; 16.769 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 16.759 ; 16.759 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 16.779 ; 16.779 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 16.779 ; 16.779 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 17.156 ; 17.156 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 17.128 ; 17.128 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 17.135 ; 17.135 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 17.135 ; 17.135 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 17.155 ; 17.155 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 17.520 ; 17.520 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 12.196 ; 12.196 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.533 ; 12.533 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 12.533 ; 12.533 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.196 ; 12.196 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.563 ; 12.563 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.563 ; 12.563 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.563 ; 12.563 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.570 ; 12.570 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.560 ; 12.560 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.580 ; 12.580 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 12.580 ; 12.580 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 12.957 ; 12.957 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 12.929 ; 12.929 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 12.936 ; 12.936 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.936 ; 12.936 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.956 ; 12.956 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 13.321 ; 13.321 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 24.991 ; 24.991 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 25.328 ; 25.328 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 25.328 ; 25.328 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 24.991 ; 24.991 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 25.358 ; 25.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 25.358 ; 25.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 25.358 ; 25.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 25.365 ; 25.365 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 25.355 ; 25.355 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 25.375 ; 25.375 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 25.375 ; 25.375 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 25.752 ; 25.752 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 25.724 ; 25.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 25.731 ; 25.731 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 25.731 ; 25.731 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 25.751 ; 25.751 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 26.116 ; 26.116 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 11.709 ; 11.709 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 11.719 ; 11.719 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 11.843 ; 11.843 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 11.843 ; 11.843 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 11.343 ; 11.343 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 7.133  ; 7.133  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 7.133  ; 7.133  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 7.732  ; 7.732  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 7.732  ; 7.732  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 7.732  ; 7.732  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 7.946  ; 7.946  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 7.946  ; 7.946  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 8.143  ; 8.143  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 8.143  ; 8.143  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 8.092  ; 8.092  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 8.092  ; 8.092  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 8.102  ; 8.102  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 8.101  ; 8.101  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 8.101  ; 8.101  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 8.101  ; 8.101  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 8.123  ; 8.123  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 8.133  ; 8.133  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 5.090  ; 5.090  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.580  ; 5.580  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 7.080  ; 7.080  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 7.296  ; 7.296  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 7.306  ; 7.306  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.694  ; 7.694  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.017  ; 8.017  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.017  ; 8.017  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.694  ; 7.694  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.045  ; 8.045  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.045  ; 8.045  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.045  ; 8.045  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.052  ; 8.052  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.042  ; 8.042  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.061  ; 8.061  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.061  ; 8.061  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.423  ; 8.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.396  ; 8.396  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.403  ; 8.403  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.403  ; 8.403  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.422  ; 8.422  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.773  ; 8.773  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 7.403  ; 7.403  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 7.403  ; 7.403  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 6.944  ; 6.944  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 5.996  ; 5.996  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.438  ; 7.438  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.761  ; 7.761  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.761  ; 7.761  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.438  ; 7.438  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 7.789  ; 7.789  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 7.789  ; 7.789  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.789  ; 7.789  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 7.796  ; 7.796  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 7.786  ; 7.786  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 7.805  ; 7.805  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.805  ; 7.805  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.167  ; 8.167  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.140  ; 8.140  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.147  ; 8.147  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.147  ; 8.147  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.166  ; 8.166  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.517  ; 8.517  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 5.810  ; 5.810  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.133  ; 6.133  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 6.133  ; 6.133  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.810  ; 5.810  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.161  ; 6.161  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.161  ; 6.161  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.161  ; 6.161  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.168  ; 6.168  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.158  ; 6.158  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.177  ; 6.177  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.177  ; 6.177  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 6.539  ; 6.539  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 6.512  ; 6.512  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.519  ; 6.519  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.519  ; 6.519  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.538  ; 6.538  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 6.889  ; 6.889  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.074  ; 8.074  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.397  ; 8.397  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.397  ; 8.397  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.074  ; 8.074  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.425  ; 8.425  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.425  ; 8.425  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.425  ; 8.425  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.432  ; 8.432  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.422  ; 8.422  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.441  ; 8.441  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.441  ; 8.441  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.803  ; 8.803  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.776  ; 8.776  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.783  ; 8.783  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.783  ; 8.783  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.802  ; 8.802  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.153  ; 9.153  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 10.625 ; 10.625 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 10.635 ; 10.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 10.732 ; 10.732 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 10.732 ; 10.732 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 10.273 ; 10.273 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 9.387     ; 9.486     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 9.387     ; 9.486     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 9.884     ; 9.983     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 9.884     ; 9.983     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 9.884     ; 9.983     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 10.045    ; 10.144    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 10.045    ; 10.144    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 10.310    ; 10.409    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 10.310    ; 10.409    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 10.244    ; 10.343    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 10.244    ; 10.343    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 10.254    ; 10.353    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 10.259    ; 10.358    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 10.259    ; 10.358    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 10.259    ; 10.358    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 10.274    ; 10.373    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 10.284    ; 10.383    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 6.114     ; 6.213     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.967     ; 6.038     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 9.748     ; 9.847     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 8.861     ; 8.932     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 8.854     ; 8.925     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 18.464    ; 18.535    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 18.740    ; 18.811    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 18.740    ; 18.811    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 18.464    ; 18.535    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 18.793    ; 18.864    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 18.793    ; 18.864    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 18.793    ; 18.864    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 18.803    ; 18.874    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 18.793    ; 18.864    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 18.820    ; 18.891    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 18.820    ; 18.891    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 19.128    ; 19.199    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 19.131    ; 19.202    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 19.141    ; 19.212    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 19.141    ; 19.212    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 19.169    ; 19.240    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 19.452    ; 19.523    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 9.003     ; 9.102     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 9.003     ; 9.102     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 8.532     ; 8.603     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 6.339     ; 6.410     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 12.981    ; 13.052    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.257    ; 13.328    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.257    ; 13.328    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.981    ; 13.052    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.310    ; 13.381    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 13.310    ; 13.381    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.310    ; 13.381    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.320    ; 13.391    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 13.310    ; 13.381    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 13.337    ; 13.408    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 13.337    ; 13.408    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 13.645    ; 13.716    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 13.648    ; 13.719    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 13.658    ; 13.729    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 13.658    ; 13.729    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 13.686    ; 13.757    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 13.969    ; 14.040    ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 11.894    ; 11.965    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.170    ; 12.241    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 12.170    ; 12.241    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 11.894    ; 11.965    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.223    ; 12.294    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.223    ; 12.294    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.223    ; 12.294    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.233    ; 12.304    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.223    ; 12.294    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.250    ; 12.321    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 12.250    ; 12.321    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 12.558    ; 12.629    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 12.561    ; 12.632    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 12.571    ; 12.642    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.571    ; 12.642    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.599    ; 12.670    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 12.882    ; 12.953    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 24.599    ; 24.670    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 24.875    ; 24.946    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 24.875    ; 24.946    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 24.599    ; 24.670    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 24.928    ; 24.999    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 24.928    ; 24.999    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 24.928    ; 24.999    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 24.938    ; 25.009    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 24.928    ; 24.999    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 24.955    ; 25.026    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 24.955    ; 25.026    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 25.263    ; 25.334    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 25.266    ; 25.337    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 25.276    ; 25.347    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 25.276    ; 25.347    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 25.304    ; 25.375    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 25.587    ; 25.658    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 10.366    ; 10.437    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 10.359    ; 10.430    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 10.508    ; 10.607    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 10.508    ; 10.607    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 10.037    ; 10.108    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 6.261     ; 6.392     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 6.261     ; 6.392     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 6.739     ; 6.870     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 6.739     ; 6.870     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 6.739     ; 6.870     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 6.893     ; 7.024     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 6.893     ; 7.024     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 7.148     ; 7.279     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 7.148     ; 7.279     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 7.085     ; 7.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 7.085     ; 7.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 7.095     ; 7.226     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 7.100     ; 7.231     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 7.100     ; 7.231     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 7.100     ; 7.231     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 7.114     ; 7.245     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 7.124     ; 7.255     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 4.704     ; 4.835     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.180     ; 5.316     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 7.085     ; 7.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 6.680     ; 6.816     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 6.674     ; 6.810     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.432     ; 7.568     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.697     ; 7.833     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.697     ; 7.833     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.432     ; 7.568     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 7.747     ; 7.883     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 7.747     ; 7.883     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.747     ; 7.883     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 7.757     ; 7.893     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 7.747     ; 7.883     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 7.773     ; 7.909     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.773     ; 7.909     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.069     ; 8.205     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.072     ; 8.208     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.080     ; 8.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.080     ; 8.216     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.108     ; 8.244     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.380     ; 8.516     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 6.822     ; 6.953     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 6.822     ; 6.953     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 6.365     ; 6.501     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 5.537     ; 5.673     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.185     ; 7.321     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.450     ; 7.586     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.450     ; 7.586     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.185     ; 7.321     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 7.500     ; 7.636     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 7.500     ; 7.636     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.500     ; 7.636     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 7.510     ; 7.646     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 7.500     ; 7.636     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 7.526     ; 7.662     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.526     ; 7.662     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 7.822     ; 7.958     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 7.825     ; 7.961     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 7.833     ; 7.969     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 7.833     ; 7.969     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 7.861     ; 7.997     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.133     ; 8.269     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 5.628     ; 5.764     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 5.893     ; 6.029     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 5.893     ; 6.029     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.628     ; 5.764     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 5.943     ; 6.079     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 5.943     ; 6.079     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.943     ; 6.079     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.953     ; 6.089     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.943     ; 6.079     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 5.969     ; 6.105     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 5.969     ; 6.105     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 6.265     ; 6.401     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 6.268     ; 6.404     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.276     ; 6.412     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.276     ; 6.412     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.304     ; 6.440     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 6.576     ; 6.712     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.785     ; 7.921     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.050     ; 8.186     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.050     ; 8.186     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.785     ; 7.921     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.100     ; 8.236     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.100     ; 8.236     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.100     ; 8.236     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.110     ; 8.246     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.100     ; 8.236     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.126     ; 8.262     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.126     ; 8.262     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.422     ; 8.558     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.425     ; 8.561     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.433     ; 8.569     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.433     ; 8.569     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.461     ; 8.597     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.733     ; 8.869     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 9.402     ; 9.538     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 9.396     ; 9.532     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 9.544     ; 9.675     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 9.544     ; 9.675     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 9.087     ; 9.223     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                                              ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1.138  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 5.920  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 5.939  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 9.574  ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 24.280 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 38.640 ; 0.000         ;
; CLK_PLL1                                                                                               ; 61.387 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 61.546 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                                               ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; -0.128 ; -0.128        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.088  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.179  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.179  ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.180  ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.188  ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.195  ; 0.000         ;
; CLK_PLL1                                                                                               ; 0.198  ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                                           ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 26.812 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 26.874 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 29.695 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                                            ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.720  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 1.791  ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 32.179 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                                                ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 12.476 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.370 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 19.312 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 20.616 ; 0.000         ;
; CLK_PLL1                                                                                               ; 30.520 ; 0.000         ;
; CLK_PLL2                                                                                               ; 30.656 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 30.990 ; 0.000         ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 30.992 ; 0.000         ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 31.032 ; 0.000         ;
+--------------------------------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                  ;
+--------+----------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                ; To Node                                                                ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.138  ; CLK_24576                                                ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL1_S              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1.970        ; -0.234     ; 0.445      ;
; 9.964  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.292     ; 5.356      ;
; 10.136 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\FIFO_RD_CTRL:LOCK   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.292     ; 5.184      ;
; 10.136 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|FIFO_SYS_RD          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.292     ; 5.184      ;
; 10.136 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|FIFO_SYS_WR          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.292     ; 5.184      ;
; 10.291 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\P_FIFO_WR_CTRL:LOCK ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.292     ; 5.029      ;
; 11.494 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BUS_FREE           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.319     ; 3.799      ;
; 11.539 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; \SLOW_CPU:TMP[2]                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.319     ; 3.754      ;
; 11.541 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; \SLOW_CPU:TMP[1]                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.319     ; 3.752      ;
; 11.542 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; \SLOW_CPU:TMP[0]                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.319     ; 3.751      ;
; 12.024 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn              ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|WAITSTATES         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 15.625       ; -0.284     ; 3.304      ;
; 15.887 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[31]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.854      ;
; 15.951 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[30]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.790      ;
; 15.955 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[29]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.786      ;
; 16.019 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[28]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.722      ;
; 16.023 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[27]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.718      ;
; 16.087 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[26]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.654      ;
; 16.091 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[25]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.650      ;
; 16.155 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[24]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.586      ;
; 16.159 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[23]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.582      ;
; 16.223 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[22]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.518      ;
; 16.227 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[21]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.514      ;
; 16.291 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[20]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.450      ;
; 16.295 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[19]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 4.446      ;
; 16.354 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[18]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 4.382      ;
; 16.358 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[17]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 4.378      ;
; 16.422 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[16]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 4.314      ;
; 16.426 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[15]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 4.310      ;
; 16.718 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[14]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 4.018      ;
; 17.033 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[5]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.093     ; 3.695      ;
; 17.033 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[4]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.093     ; 3.695      ;
; 17.108 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[9]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.089     ; 3.624      ;
; 17.108 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[13]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.089     ; 3.624      ;
; 17.108 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[14]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.089     ; 3.624      ;
; 17.145 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[3]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.086     ; 3.590      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[4]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[5]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[6]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[7]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[8]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.158 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[12]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.569      ;
; 17.163 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[4]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.566      ;
; 17.163 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[3]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.566      ;
; 17.163 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[2]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.566      ;
; 17.163 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[0]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.566      ;
; 17.163 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[1]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.566      ;
; 17.167 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[7]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.562      ;
; 17.167 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[5]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.562      ;
; 17.167 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[6]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.562      ;
; 17.171 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[9]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.558      ;
; 17.171 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[13]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.558      ;
; 17.171 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[14]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.558      ;
; 17.178 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.093     ; 3.550      ;
; 17.178 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[10]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.093     ; 3.550      ;
; 17.178 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[11]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.093     ; 3.550      ;
; 17.178 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[15]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.093     ; 3.550      ;
; 17.204 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[6]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.092     ; 3.525      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[4]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[5]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[6]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[7]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[8]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.229 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[12]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.097     ; 3.495      ;
; 17.230 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|NEW_TRACK                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.497      ;
; 17.238 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.096     ; 3.487      ;
; 17.238 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[10]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.096     ; 3.487      ;
; 17.238 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[11]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.096     ; 3.487      ;
; 17.238 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[15]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.096     ; 3.487      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[13]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[12]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[10]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[9]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[8]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[11]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.239 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[7]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.085     ; 3.497      ;
; 17.240 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|BLOCK_ADR[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.080     ; 3.501      ;
; 17.388 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.A                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.339      ;
; 17.417 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_WR        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|FDD_STATE.WAIT_SDC            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.089     ; 3.315      ;
; 17.447 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.B                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.280      ;
; 17.554 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[9]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.173      ;
; 17.554 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[13]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.173      ;
; 17.554 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[14]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.173      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[4]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[5]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[6]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[7]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[8]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.604 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[12]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.099     ; 3.118      ;
; 17.607 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|DRIVE.NONE                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.094     ; 3.120      ;
; 17.624 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.098     ; 3.099      ;
; 17.624 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD        ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_ADR_I[10]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 20.834       ; -0.098     ; 3.099      ;
+--------+----------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                                            ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                         ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[7] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[4] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[5] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[6] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[9] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 5.920 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[8] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.236     ; 1.505      ;
; 6.652 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.245     ; 0.764      ;
; 6.758 ; SCLK_6M4                                                                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK    ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 7.814        ; -0.245     ; 0.658      ;
; 6.766 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 8.951      ;
; 6.778 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.703      ;
; 6.778 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.703      ;
; 6.791 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.690      ;
; 6.791 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.690      ;
; 6.795 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.696      ;
; 6.795 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.696      ;
; 6.808 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.683      ;
; 6.808 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.683      ;
; 6.814 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.491      ;
; 6.814 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.491      ;
; 6.814 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.491      ;
; 6.819 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.488      ;
; 6.827 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.478      ;
; 6.827 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.478      ;
; 6.827 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.478      ;
; 6.830 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[13]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.677      ;
; 6.830 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.677      ;
; 6.832 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.475      ;
; 6.840 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[33]                         ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[1]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.288     ; 3.277      ;
; 6.843 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[13]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.664      ;
; 6.843 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.664      ;
; 6.846 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 8.871      ;
; 6.859 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.622      ;
; 6.859 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.622      ;
; 6.874 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.607      ;
; 6.874 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.607      ;
; 6.876 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SPEED_MODE[0]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.085     ; 3.444      ;
; 6.876 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SPEED_MODE[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.085     ; 3.444      ;
; 6.876 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.615      ;
; 6.876 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.615      ;
; 6.881 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 8.837      ;
; 6.891 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.600      ;
; 6.891 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.600      ;
; 6.892 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.415      ;
; 6.895 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.410      ;
; 6.895 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.410      ;
; 6.895 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.410      ;
; 6.899 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.408      ;
; 6.900 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.407      ;
; 6.905 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[5]                          ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[5]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.288     ; 3.212      ;
; 6.910 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.395      ;
; 6.910 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.395      ;
; 6.910 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.395      ;
; 6.911 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[13]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.596      ;
; 6.911 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.596      ;
; 6.911 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 8.806      ;
; 6.912 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.395      ;
; 6.920 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.099     ; 3.386      ;
; 6.926 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[13]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.581      ;
; 6.926 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.581      ;
; 6.931 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\DTACK_OUT:DTACK_DELAY                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 8.786      ;
; 6.933 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.099     ; 3.373      ;
; 6.935 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.106      ; 8.783      ;
; 6.942 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[99]                         ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[3]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.289     ; 3.174      ;
; 6.947 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.IDLE                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|REQn                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.358      ;
; 6.951 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.530      ;
; 6.951 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.530      ;
; 6.963 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[16]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.091      ; 3.533      ;
; 6.968 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.523      ;
; 6.968 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.523      ;
; 6.969 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.338      ;
; 6.972 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.335      ;
; 6.976 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[15]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.091      ; 3.520      ;
; 6.980 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.327      ;
; 6.981 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.120     ; 3.304      ;
; 6.981 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.120     ; 3.304      ;
; 6.981 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7] ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 15.625       ; 0.105      ; 8.736      ;
; 6.984 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]                         ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[3]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.089     ; 3.332      ;
; 6.987 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.318      ;
; 6.987 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.318      ;
; 6.987 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.318      ;
; 6.988 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.493      ;
; 6.988 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[8]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.076      ; 3.493      ;
; 6.993 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[18]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.099     ; 3.313      ;
; 6.996 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.296     ; 3.113      ;
; 6.996 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.296     ; 3.113      ;
; 6.996 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.296     ; 3.113      ;
; 6.998 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.110     ; 3.297      ;
; 6.998 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.110     ; 3.297      ;
; 7.001 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[17]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.099     ; 3.305      ;
; 7.003 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.302      ;
; 7.003 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[12]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.302      ;
; 7.003 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.100     ; 3.302      ;
; 7.003 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[13]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.504      ;
; 7.003 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[19]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SENSE_KEY[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.102      ; 3.504      ;
; 7.005 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[11]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.486      ;
; 7.005 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[10]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; 0.086      ; 3.486      ;
; 7.010 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[20]                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\OUTBUFFER:DATA_BUFFER[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 10.418       ; -0.098     ; 3.297      ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                                                                                                                                                                       ;
+-------+-------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                       ; To Node                                                               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 5.939 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.580      ;
; 5.947 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.572      ;
; 5.971 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.548      ;
; 5.979 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.540      ;
; 6.082 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.437      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.088 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.239      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.238      ;
; 6.090 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.429      ;
; 6.110 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.409      ;
; 6.111 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[9]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.408      ;
; 6.118 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.401      ;
; 6.119 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[9]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.400      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[81]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[80]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[85]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[83]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[82]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[84]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[87]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.120 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[86]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.207      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.122 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.206      ;
; 6.125 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[2]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.394      ;
; 6.126 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.393      ;
; 6.133 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[2]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.386      ;
; 6.134 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.385      ;
; 6.136 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.383      ;
; 6.144 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; 0.116      ; 4.375      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[21]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[19]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[18]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[20]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[23]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[22]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.182      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.151 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.178      ;
; 6.163 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.165      ;
; 6.168 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.080     ; 4.155      ;
; 6.168 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.080     ; 4.155      ;
; 6.168 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.080     ; 4.155      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[17]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[16]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[21]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[19]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[18]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[20]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[23]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[22]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.076     ; 4.150      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.183 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.146      ;
; 6.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.075     ; 4.133      ;
; 6.200 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.080     ; 4.123      ;
; 6.200 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.080     ; 4.123      ;
; 6.200 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.080     ; 4.123      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[89]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[88]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[93]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[91]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[90]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[92]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[95]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.212 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[94]                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.074     ; 4.117      ;
; 6.222 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[1]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.072     ; 4.109      ;
; 6.222 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[3]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.072     ; 4.109      ;
; 6.222 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[2]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.072     ; 4.109      ;
; 6.222 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[6]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 10.416       ; -0.072     ; 4.109      ;
+-------+-------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                           ;
+--------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                   ; To Node                                                                      ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.574  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SIZE_N[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.300     ; 5.738      ;
; 9.582  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SIZE_N[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.300     ; 5.730      ;
; 9.776  ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SIZE_N[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 5.540      ;
; 10.430 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[21]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 4.893      ;
; 10.430 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 4.893      ;
; 10.430 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 4.893      ;
; 10.443 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|ADR_OFFSET[5]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.873      ;
; 10.447 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|ADR_OFFSET[4]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.869      ;
; 10.511 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|ADR_OFFSET[3]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.805      ;
; 10.515 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|ADR_OFFSET[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.801      ;
; 10.529 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.285     ; 4.798      ;
; 10.529 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.285     ; 4.798      ;
; 10.552 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.283     ; 4.777      ;
; 10.579 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|ADR_OFFSET[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.737      ;
; 10.751 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|ADR_OFFSET[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.565      ;
; 10.771 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.086     ; 4.755      ;
; 10.787 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[20]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.089     ; 4.736      ;
; 10.787 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.089     ; 4.736      ;
; 10.792 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.101     ; 4.719      ;
; 10.792 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.101     ; 4.719      ;
; 10.810 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.064     ; 4.738      ;
; 10.846 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.285     ; 4.481      ;
; 11.024 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.099     ; 4.489      ;
; 11.037 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.089     ; 4.486      ;
; 11.075 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.061     ; 4.476      ;
; 11.085 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.064     ; 4.463      ;
; 11.087 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.066     ; 4.459      ;
; 11.091 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.225      ;
; 11.121 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.285     ; 4.206      ;
; 11.138 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.061     ; 4.413      ;
; 11.145 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[26]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.285     ; 4.182      ;
; 11.156 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[8]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.053     ; 4.403      ;
; 11.157 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.053     ; 4.402      ;
; 11.157 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[12]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.053     ; 4.402      ;
; 11.210 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.106      ;
; 11.213 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.061     ; 4.338      ;
; 11.268 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.296     ; 4.048      ;
; 11.271 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.061     ; 4.280      ;
; 11.289 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[27]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.285     ; 4.038      ;
; 11.481 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.281     ; 3.850      ;
; 11.588 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 3.735      ;
; 11.605 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[30]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 3.718      ;
; 11.605 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[29]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 3.718      ;
; 11.616 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[28]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.289     ; 3.707      ;
; 11.983 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DSACK_In[0]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.275     ; 3.354      ;
; 12.595 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DSACK_In[1]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15.625       ; -0.283     ; 2.734      ;
; 17.510 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.030     ; 13.697     ;
; 17.562 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.643     ;
; 17.565 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.164      ; 13.836     ;
; 17.575 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.630     ;
; 17.590 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.611     ;
; 17.590 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.030     ; 13.617     ;
; 17.625 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.029     ; 13.583     ;
; 17.642 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.563     ;
; 17.645 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.164      ; 13.756     ;
; 17.648 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.553     ;
; 17.655 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.030     ; 13.552     ;
; 17.655 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.550     ;
; 17.664 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.154      ; 13.727     ;
; 17.670 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.531     ;
; 17.677 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.031     ; 13.529     ;
; 17.679 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.029     ; 13.529     ;
; 17.680 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.165      ; 13.722     ;
; 17.690 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.031     ; 13.516     ;
; 17.705 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.035     ; 13.497     ;
; 17.707 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.498     ;
; 17.710 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.164      ; 13.691     ;
; 17.718 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.028     ; 13.491     ;
; 17.720 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.485     ;
; 17.725 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.030     ; 13.482     ;
; 17.728 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.473     ;
; 17.731 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.031     ; 13.475     ;
; 17.734 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.165      ; 13.668     ;
; 17.735 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.466     ;
; 17.738 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.152      ; 13.651     ;
; 17.744 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.154      ; 13.647     ;
; 17.744 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.031     ; 13.462     ;
; 17.749 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.152      ; 13.640     ;
; 17.759 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.035     ; 13.443     ;
; 17.760 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.029     ; 13.448     ;
; 17.763 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.035     ; 13.439     ;
; 17.770 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.431     ;
; 17.777 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.428     ;
; 17.779 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.155      ; 13.613     ;
; 17.780 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.164      ; 13.621     ;
; 17.790 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.032     ; 13.415     ;
; 17.793 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.408     ;
; 17.795 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[9]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.030     ; 13.412     ;
; 17.798 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.028     ; 13.411     ;
; 17.805 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[7]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.036     ; 13.396     ;
; 17.809 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[5]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.154      ; 13.582     ;
; 17.812 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.031     ; 13.394     ;
; 17.815 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.165      ; 13.587     ;
; 17.817 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.035     ; 13.385     ;
; 17.818 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.152      ; 13.571     ;
; 17.825 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[8]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.031     ; 13.381     ;
; 17.829 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.152      ; 13.560     ;
; 17.832 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[10] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.029     ; 13.376     ;
; 17.833 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[6]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; 0.155      ; 13.559     ;
; 17.833 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4]  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.027     ; 13.377     ;
+--------+-----------------------------------------------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                              ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node             ; To Node               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 24.280 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 1.062      ;
; 24.328 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 1.014      ;
; 24.328 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 1.014      ;
; 24.564 ; CLK_24576             ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.778      ;
; 24.596 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.746      ;
; 24.596 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.746      ;
; 24.800 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.542      ;
; 24.801 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.541      ;
; 24.810 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.532      ;
; 24.983 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 25.390       ; -0.035     ; 0.359      ;
+--------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                      ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 38.640 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.035     ; 0.374      ;
; 38.655 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.035     ; 0.359      ;
; 38.655 ; SCLK_6M4          ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 39.062       ; -0.035     ; 0.359      ;
+--------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLK_PLL1'                                                                                     ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 61.387 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.064      ;
; 61.387 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.064      ;
; 61.387 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.064      ;
; 61.387 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.064      ;
; 61.387 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.064      ;
; 61.391 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.060      ;
; 61.391 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.060      ;
; 61.391 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.060      ;
; 61.391 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.060      ;
; 61.391 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 1.060      ;
; 61.490 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.961      ;
; 61.490 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.961      ;
; 61.490 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.961      ;
; 61.490 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.961      ;
; 61.490 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.961      ;
; 61.541 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.910      ;
; 61.541 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.910      ;
; 61.541 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.910      ;
; 61.541 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.910      ;
; 61.541 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.910      ;
; 61.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.802      ;
; 61.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.802      ;
; 61.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.802      ;
; 61.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.802      ;
; 61.649 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.802      ;
; 61.761 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.690      ;
; 61.765 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.686      ;
; 61.864 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.587      ;
; 61.915 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.536      ;
; 62.023 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.428      ;
; 62.084 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; -0.036     ; 0.367      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                            ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 61.546 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.709      ;
; 61.566 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.689      ;
; 61.625 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.630      ;
; 61.646 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.609      ;
; 61.719 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.536      ;
; 61.719 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.536      ;
; 61.783 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.472      ;
; 61.876 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.232     ; 0.379      ;
; 61.877 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.043     ; 0.567      ;
; 61.905 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.036     ; 0.546      ;
; 61.906 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.043     ; 0.538      ;
; 61.971 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.043     ; 0.473      ;
; 62.085 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.043     ; 0.359      ;
; 62.085 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.043     ; 0.359      ;
; 62.085 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.043     ; 0.359      ;
; 62.092 ; CLK_0M5              ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.036     ; 0.359      ;
; 62.092 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.036     ; 0.359      ;
; 62.092 ; CLK_2M0              ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 62.500       ; -0.036     ; 0.359      ;
+--------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                                                                                           ;
+--------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                   ; To Node                                                                                                     ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.128 ; CLK_24576                                                                                                   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL1_S                                                   ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.020        ; 0.257      ; 0.393      ;
; 0.179  ; VMA_68K30Ln                                                                                                 ; VMA_68K30Ln                                                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE.SHIFTOUT   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.044      ; 0.307      ;
; 0.186  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_RD                                     ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_RD                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.WAIT_SCLK                                  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.WAIT_SCLK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA                                      ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE                                         ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                             ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[2]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[2]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[0]                                               ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|\SDC_RDWR:SHIFTER[0]                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.PARITY     ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.PARITY     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.WAIT_START ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE.WAIT_START ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                               ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                                     ; FLASHBOOT_UMASPI:I_FLASHBOOT|\SHFT:LOCK                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_TIMEOUT:TMP[26]                                                             ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_TIMEOUT:TMP[26]                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                         ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ   ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR     ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I                                 ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[7]                              ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[7]                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_A_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_A_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_C_OUT                                   ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|OSC_C_OUT                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[2]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[1]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\MUSICGENERATOR:CLK_DIV[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[2]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[1]                  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\ENVELOPE:ENV_UP_DNn                        ; WF2149IP_DIGOUT_TOP_SOC:I_SOUND|WF2149IP_WAVE_DIGOUT:I_PSG_WAVE|\ENVELOPE:ENV_UP_DNn                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF_AUDIO_DAC:I_AUDIODAC|\TX_SHIFT:LOCK                                                                      ; WF_AUDIO_DAC:I_AUDIODAC|\TX_SHIFT:LOCK                                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[0]                                             ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[0]                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[15]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_TX[15]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\TX_SHIFT:LOCK                                        ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\TX_SHIFT:LOCK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.SHIFT_R                                                              ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.SHIFT_R                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.LOAD_R                                                               ; WF_AUDIO_DAC:I_AUDIODAC|DAC_CTRL_STATE.LOAD_R                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; SYNCn                                                                                                       ; SYNCn                                                                                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ADJUST                                      ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ADJUST                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|BANK                                        ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|BANK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ALARM_EN                                    ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_REGISTERS:I_REGISTERS|ALARM_EN                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[2]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[2]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[7]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[7]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[3]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[3]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[6]                                        ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|SHIFTMODE[6]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                                    ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|BLT_STATE.BUSREQUEST                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                               ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|HOG_START                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQ_I                                  ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQ_I                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RDRF_I                                     ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RDRF_I                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                        ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|PE                                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|PE                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                                   ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|DATA_EN                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\FIFO_RD_CTRL:LOCK                                        ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|\FIFO_RD_CTRL:LOCK                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; \SLOW_CPU:TMP[1]                                                                                            ; \SLOW_CPU:TMP[1]                                                                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; \SLOW_CPU:TMP[2]                                                                                            ; \SLOW_CPU:TMP[2]                                                                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\PARITY_TEST:PE_I                          ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\PARITY_TEST:PE_I                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|FE                                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|FE                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\FRAME_ERR:FE_I                            ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\FRAME_ERR:FE_I                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[1]                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_STATUS_REG[1]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|CTRL_MASK[1]                                          ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|CTRL_MASK[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|\CTRL_ACC_TIMING:LOCK                                 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|\CTRL_ACC_TIMING:LOCK                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_WR                                     ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.SPI_WR                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|\IPL1n_CONTROL:SECOND                             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_INTERRUPTS:I_INTERRUPT|\IPL1n_CONTROL:SECOND                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[3]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[3]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[1]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[1]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[2]                                            ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|REG_PNT[2]                                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.TEST_PENDING                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|CTRL_STATE.TEST_PENDING                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_SCLK                                              ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|SPI_SCLK                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[2]                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[2]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[1]                               ; WF5C15_139xIP_TOP:I_RTC5C15|WF5C15_139xIP_CTRL:I_CTRL|\SPI_CLOCK:CLK_COUNT[1]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                                  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_STE_ENH:I_STE_ENHANCEMENTS|RESET_CNT[0]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_LOW                                    ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_LOW                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_BYTE2                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_HI                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_RD_HI                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_WR_HI                                     ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|ACSI_STATE.IDLE_WR_HI                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE_I                                       ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE_I                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.START                               ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.START                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[1]                                    ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[1]                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE_I                                   ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE_I                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.START                           ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.START                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:STRB_LOCK                        ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:STRB_LOCK                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_LOCK                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_LOCK                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2]                                ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2]                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[1]                                ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[1]                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP2                            ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP2                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP1                            ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.STOP1                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.PARITY                           ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.PARITY                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[2]                                  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[2]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1]                                  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1]                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.WAIT_START                       ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE.WAIT_START                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:STRB_LOCK                          ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:STRB_LOCK                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_LOCK                           ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_LOCK                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; E_I                                                                                                         ; E_I                                                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[0]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[0]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[8]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[8]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[9]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[9]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[11]                                     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[11]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[10]                                     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[10]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[7]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[7]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[4]                                      ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_VIDEO_TIMING:I_VIDEO|\DE_OUT:TMP[4]                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+--------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                                                                                      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                                    ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.088 ; SCLK_6M4                                                                                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:LOCK                               ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.002        ; 0.246      ; 0.580      ;
; 0.147 ; SCLK_6M4                                                                                 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]                            ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.002        ; 0.246      ; 0.639      ;
; 0.177 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                              ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|DTACK_MCUn                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.046      ; 0.307      ;
; 0.179 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_SBLOCK                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_MBLOCK                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                           ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STATUS_OUT[1]                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|SC_ASC[9]                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.IDLE                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                    ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_MODE                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.043      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IO                             ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IO                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_SBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RD_SBLOCK                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_MBLOCK                               ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|WR_MBLOCK                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|MBLOCK                                  ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|MBLOCK                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:LOCK                     ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\ADDRESS_LOGIC:LOCK                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|MW_DATA[0]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_B[0]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYN_LOAD_SHIFT:LOCK_LOAD                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SYNC:LOCK                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN             ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|\STATES:START_EN                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|\SH_CLK:LOCK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[0]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[2]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]    ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|\MONOCHROME_MASK:MASK_COUNTER[3]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.RUN                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.IDLE                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                     ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|MASK_STATE.STOP                                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                       ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_OUT:I_CROUT|STARTUP_BLANK                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[1]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[1]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[2]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[2]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[1]             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[1]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK           ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\TIME_SLICES:LOCK                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK           ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\TIME_SLICES:LOCK                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\P_LINEDOUBLING:SECOND_LINE                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|\MCU_PHASE_SWITCH:TMP                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[2]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[1]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                      ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|WR_PNT[0]                                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In               ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SINT_In                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK           ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:FCLK_LOCK                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE              ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\AUDIO_OUT:TOGGLE                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]          ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_DMASOUND:I_DMASOUND|\SAMPLECLOCKS:TEMP[0]                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[1]                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[2]                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[0]                                           ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[0]                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\SPEED_DETECTION:LOCK                   ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\SPEED_DETECTION:LOCK                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RW_ERROR                                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|RW_ERROR                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\COMMAND_DESCRIPTOR:LOCK                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\COMMAND_DESCRIPTOR:LOCK                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IDLE                           ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|BUSPHASE.IDLE                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:FIRST_ACCESS             ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:FIRST_ACCESS                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:REJECTED                 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|\P_MEDIACHANGE:REJECTED                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STAT_RDY                                ; WF_SD_DRIVES:I_DRIVES|ACSI_SDHD_CTRL:I_ACSI_CTRL|STAT_RDY                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.WRITE                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ              ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|DMA_PHASE.READ                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[2]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[2]                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[1]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[1]                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[3]     ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|\BRn_LOGIC:RDY_COUNT[3]                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.307      ;
; 0.190 ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|TRAM_DATA_IN[6]                                 ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a38~porta_datain_reg0 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.273      ; 0.587      ;
; 0.192 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[6]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[7]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.312      ;
; 0.193 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[4]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[5]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[38]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[23]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[47]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[4]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[3]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[3]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[4]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[0]             ; WF25915IP_TOP_SOC:I_GLUE|WF25915IP_BUS_ARBITER:I_Arbitration|SLICE_NUMBER[0]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[0]             ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_CTRL_SD:I_CONTROL|SLICE_NUMBER[0]                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[29]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[16]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[17]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[12]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[5]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|\P_SDINIT:TMP[0]                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[52]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[48]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[49]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[45]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[46]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[36]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[37]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[1]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[2]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[2]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[3]                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[41]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.315      ;
; 0.196 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[50]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[51]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[43]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[44]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[11]                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[12]                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[10]                  ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_A[11]                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[9]                   ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|YINT_C[10]                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[25]       ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]        ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.036      ; 0.316      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                ; To Node                                                                                  ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.179 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.044      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|\MOVEM_AR_CPY:LOCK                                                    ; WF68K30L_TOP:I_CPU|\MOVEM_AR_CPY:LOCK                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IBOUND                       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IBOUND                       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|OW_RDY                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[29]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[29]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[14]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[14]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[31]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[31]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[25]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[25]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|VFLAG_DIV                                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|VFLAG_DIV                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[1]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[14]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[14]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[13]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[13]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[12]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[12]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[26]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[26]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[25]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[25]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[24]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[24]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[20]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[20]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[17]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[17]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[19]                        ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[19]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[17]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[17]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[29]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[29]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[27]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[27]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[22]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[22]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[25]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[25]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[23]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[23]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[24]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[24]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[19]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[19]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[21]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[21]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[7]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[7]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[5]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[5]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[6]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[6]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[4]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[4]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[1]                          ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:QUOTIENT_VAR[1]                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[5]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[5]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[4]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[4]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[2]                         ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:REMAINDER_VAR[2]                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1]             ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[1]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2]             ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[2]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0]             ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_ADR_OFFS:OFFSET_VAR[0]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_VALID                          ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_VALID                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:STARTUP                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[1]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[2]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[3]                  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[3]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\RESET_FILTER:TMP[0]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[2]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_CTRL_STATE.DATA_C1C4              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_FLT                               ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BUS_FLT                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|RETRY                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SSW_80[8]                             ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SSW_80[8]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PARTITIONING:RESTORE_VAR[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_AERR            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_BERR            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_CHK             ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_CHK             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_1010            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_1010            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_PRIV            ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_PRIV            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_DIVZERO         ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_DIVZERO         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_FORMAT          ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_FORMAT          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRAPcc          ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EXCEPTION.EX_TRAPcc          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_1010                    ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_1010                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_1111                    ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_1111                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_PRIV                    ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_PRIV                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_CHK                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_DIVZERO                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_FORMAT                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                        ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[2]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                        ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[1]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                        ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_P[0]                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|OPCODE_ACCESS                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|IPIPE_B_FAULT                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[17]                      ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[17]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IVECT_OFFS[2]                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IVECT_OFFS[2]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[16]                      ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[16]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[20]                      ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[20]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[21]                      ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|VBR[21]                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IVECT_OFFS[4]                ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IVECT_OFFS[4]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_VALID                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.UPDATE_PC           ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_STATE.UPDATE_PC           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[1] ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\STACK_CTRL:STACK_POS_VAR[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|WRITE_ACCESS                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                           ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|READ_ACCESS                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|EX_P_AERR                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\PREFETCH_BUFFERS:RDY_VAR             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|MEMADR_RDY                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[30]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[30]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[31]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[31]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[28]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[28]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[29]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP1_BUFFER[29]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|READ_CYCLE                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|ADR_LATCH[1]                                                          ; WF68K30L_TOP:I_CPU|ADR_LATCH[1]                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|EW_RDY                                     ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|EW_RDY                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|FETCH_STATE.FETCH_IDATA_B2                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[15]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[15]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[13]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[13]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[24]                           ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\OPERANDS:OP3_BUFFER[24]                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_1[3]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|AR_USED_2[3]            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_BYTES[0]                                ; WF68K30L_TOP:I_CPU|WF68K30L_CONTROL:I_CONTROL|BF_BYTES[0]                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.035      ; 0.307      ;
+-------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                                                                                                                                                                                                                ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                      ; To Node                                                                        ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.179 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SDC_PWRn                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|POR_RDY                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[9]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[10]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[18]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.044      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[0]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[15]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.043      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|OP_RDY                              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|OP_RDY                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[2]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[0]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[1]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[3]                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\DESELECTION:CNT[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_OUT                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_OUT                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_WR                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_WR                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[0]                                          ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[0]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[1]                                          ; WF_SD_DRIVES:I_DRIVES|\P_LED:TMP_2[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR                     ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_CRC_ERR                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[12]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[12]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[11]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[11]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[10]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[10]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[7]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[5]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[4]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[3]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[2]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[2]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_RD                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|STOP_CLK_RD                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[2]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[6]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[0]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[7]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                             ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[1]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[1]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:TOKEN              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:TOKEN              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:BITCNT[0]              ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CMD_SHIFTER:BITCNT[0]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_58_CCS            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_0                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.INIT_CMD_0                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.SWITCH_SPI                 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.SWITCH_SPI                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.POR                        ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_STATE.POR                        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[11]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[13]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[14]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[16]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[17]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[19]                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[19]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[7]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[6]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[5]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[3]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[1]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[2]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[8]                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\POR_TIMER:CNT[8]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1                    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CARD_RELEASE:LOCK                  ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\CARD_RELEASE:LOCK                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_RELEASE            ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_RELEASE            ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_RESPONSE_RDY                   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_RESPONSE_RDY                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_DATA_RESPONSE      ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_DATA_RESPONSE      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.307      ;
; 0.189 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_MBLOCK                           ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_MBLOCK                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.034      ; 0.307      ;
; 0.195 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:BITCNT[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[0]          ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:BITCNT[0]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:BITCNT[5] ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:BITCNT[5] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.036      ; 0.316      ;
; 0.203 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[14]   ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:CRC_SHIFT_16[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.322      ;
; 0.206 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.325      ;
; 0.210 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[8]    ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Tx_DATA_SHIFTER:CRC_SHIFT_16[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.329      ;
; 0.214 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.333      ;
; 0.215 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_CMD_RESPONSE       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\COMMAND_RESPONSE_SHIFTER:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.334      ;
; 0.217 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[3]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.336      ;
; 0.222 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[1]         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|\Rx_DATA_SHIFTER:SHIFTER[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.035      ; 0.341      ;
; 0.225 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[2]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.034      ; 0.343      ;
; 0.226 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[1]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.034      ; 0.344      ;
; 0.226 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[4]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.034      ; 0.344      ;
; 0.227 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[0]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.034      ; 0.345      ;
; 0.227 ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RDY                         ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Tx_DATA_RESPONSE[3]                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000        ; 0.034      ; 0.345      ;
+-------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                            ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.180 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.043      ; 0.307      ;
; 0.180 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.043      ; 0.307      ;
; 0.187 ; CLK_2M0              ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; CLK_0M5              ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; \P_AUX_CLOCKS:TMP[3] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.043      ; 0.314      ;
; 0.275 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.043      ; 0.402      ;
; 0.307 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.043      ; 0.434      ;
; 0.308 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.043      ; 0.435      ;
; 0.349 ; \P_AUX_CLOCKS:TMP[3] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; 0.036      ; 0.469      ;
; 0.387 ; \P_AUX_CLOCKS:TMP[2] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.318      ;
; 0.472 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.403      ;
; 0.502 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.433      ;
; 0.502 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.433      ;
; 0.572 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[3] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.503      ;
; 0.606 ; \P_AUX_CLOCKS:TMP[1] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.537      ;
; 0.640 ; \P_AUX_CLOCKS:TMP[2] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.571      ;
; 0.659 ; \P_AUX_CLOCKS:TMP[0] ; CLK_0M5              ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000        ; -0.153     ; 0.590      ;
+-------+----------------------+----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                      ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node           ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.188 ; SCLK_6M4          ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.195 ; \P_6M4:TMP_6M4[0] ; \P_6M4:TMP_6M4[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.197 ; \P_6M4:TMP_6M4[0] ; SCLK_6M4          ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.035      ; 0.316      ;
+-------+-------------------+-------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                              ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node             ; To Node               ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.195 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.314      ;
; 0.296 ; \P_2M4576:TMP_2M54[2] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.415      ;
; 0.302 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.421      ;
; 0.302 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.421      ;
; 0.454 ; \P_2M4576:TMP_2M54[0] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.573      ;
; 0.455 ; \P_2M4576:TMP_2M54[1] ; \P_2M4576:TMP_2M54[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.574      ;
; 0.530 ; CLK_24576             ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.649      ;
; 0.671 ; \P_2M4576:TMP_2M54[2] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.790      ;
; 0.683 ; \P_2M4576:TMP_2M54[0] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.802      ;
; 0.684 ; \P_2M4576:TMP_2M54[1] ; CLK_24576             ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.035      ; 0.803      ;
+-------+-----------------------+-----------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLK_PLL1'                                                                                     ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.198 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.318      ;
; 0.260 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.380      ;
; 0.299 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.420      ;
; 0.310 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.430      ;
; 0.368 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.488      ;
; 0.422 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.542      ;
; 0.447 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.567      ;
; 0.447 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.567      ;
; 0.457 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.577      ;
; 0.458 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.578      ;
; 0.460 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.580      ;
; 0.461 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.581      ;
; 0.507 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.627      ;
; 0.507 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.627      ;
; 0.510 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.630      ;
; 0.513 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.633      ;
; 0.523 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.643      ;
; 0.526 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.646      ;
; 0.685 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.805      ;
; 0.685 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.805      ;
; 0.685 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.805      ;
; 0.685 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.805      ;
; 0.793 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.913      ;
; 0.847 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.967      ;
; 0.847 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 0.967      ;
; 0.932 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 1.052      ;
; 0.932 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 1.052      ;
; 0.932 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.036      ; 1.052      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                                                         ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                                   ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[38]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[39]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[40]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[41]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[42]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[54]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.812 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[55]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[16]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.104     ; 4.316      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[1]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[2]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[8]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[8]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[10]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[11]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[11] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[12]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[13]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[15]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[17]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[18]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[19]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[20]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_START_BUFFER[20] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[21]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[22]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|FRAME_END_BUFFER[23]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.098     ; 4.322      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[4]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[8]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[9]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[10]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[11]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[12]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[13]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[14]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[15]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.323      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[16]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[17]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[18]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[19]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[20]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[21]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[22]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[23]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[24]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[25]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[26]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[27]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[28]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[29]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[30]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.817 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[31]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.096     ; 4.324      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[4]          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.104     ; 4.315      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[7]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.101     ; 4.318      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][0]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][1]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][2]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][4]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][5]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][7]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][12]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[11][15]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][0]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][3]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][5]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][9]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[6][10]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][0]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][1]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][3]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][5]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][7]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][9]                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][10]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][11]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[4][15]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_REGISTERS:I_REGS|CHROMA_REG[14][1]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.099     ; 4.320      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|\P_SINT:TMP[53]        ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.097     ; 4.322      ;
; 26.818 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; MDAT_BUFFER[12]                                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.102     ; 4.317      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[2]               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.105     ; 4.313      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.315      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.315      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.315      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_CR_SHIFT_REG:I_CRSHIFT|HSCROLL[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.103     ; 4.315      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[3]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.102     ; 4.316      ;
; 26.819 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR ; WF25914IP_TOP_SOC:I_SHIFTER|WF25914IP_MICROWIRE:I_MICROWIRE|BITCNT[0]                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 31.250       ; -0.102     ; 4.316      ;
+--------+-------------------------------------------------+-------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                              ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                            ; To Node                                                                                                   ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 26.874 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.048     ; 4.315      ;
; 26.874 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.047     ; 4.316      ;
; 26.874 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.047     ; 4.316      ;
; 26.874 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.047     ; 4.316      ;
; 26.882 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.041     ; 4.314      ;
; 26.882 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.041     ; 4.314      ;
; 26.883 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.041     ; 4.313      ;
; 26.886 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.048     ; 4.303      ;
; 26.886 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.047     ; 4.304      ;
; 26.886 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.047     ; 4.304      ;
; 26.886 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.047     ; 4.304      ;
; 26.888 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.306      ;
; 26.888 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.306      ;
; 26.888 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.306      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.319      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.319      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.319      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.319      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.319      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.035     ; 4.313      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.035     ; 4.313      ;
; 26.889 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.035     ; 4.313      ;
; 26.890 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.314      ;
; 26.890 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.314      ;
; 26.890 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.314      ;
; 26.890 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.314      ;
; 26.894 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.041     ; 4.302      ;
; 26.894 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.041     ; 4.302      ;
; 26.895 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.041     ; 4.301      ;
; 26.899 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.020     ; 4.318      ;
; 26.899 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.020     ; 4.318      ;
; 26.899 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.020     ; 4.318      ;
; 26.900 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.294      ;
; 26.900 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.294      ;
; 26.900 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.294      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.307      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.307      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.307      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.307      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.029     ; 4.307      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.035     ; 4.301      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.035     ; 4.301      ;
; 26.901 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.035     ; 4.301      ;
; 26.902 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.302      ;
; 26.902 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.302      ;
; 26.902 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.302      ;
; 26.902 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.033     ; 4.302      ;
; 26.906 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.014     ; 4.317      ;
; 26.906 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.014     ; 4.317      ;
; 26.906 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.014     ; 4.317      ;
; 26.911 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.020     ; 4.306      ;
; 26.911 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.020     ; 4.306      ;
; 26.911 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.020     ; 4.306      ;
; 26.918 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.014     ; 4.305      ;
; 26.918 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.014     ; 4.305      ;
; 26.918 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.014     ; 4.305      ;
; 26.951 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.043     ; 4.243      ;
; 26.951 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.042     ; 4.244      ;
; 26.951 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.042     ; 4.244      ;
; 26.951 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.042     ; 4.244      ;
; 26.959 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.036     ; 4.242      ;
; 26.959 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.036     ; 4.242      ;
; 26.960 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.036     ; 4.241      ;
; 26.965 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.038     ; 4.234      ;
; 26.965 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.038     ; 4.234      ;
; 26.965 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.038     ; 4.234      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.024     ; 4.247      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.024     ; 4.247      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.024     ; 4.247      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.024     ; 4.247      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.024     ; 4.247      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.030     ; 4.241      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.030     ; 4.241      ;
; 26.966 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.030     ; 4.241      ;
; 26.967 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.028     ; 4.242      ;
; 26.967 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.028     ; 4.242      ;
; 26.967 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.028     ; 4.242      ;
; 26.967 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.028     ; 4.242      ;
; 26.976 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.015     ; 4.246      ;
; 26.976 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.015     ; 4.246      ;
; 26.976 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.015     ; 4.246      ;
; 26.983 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.009     ; 4.245      ;
; 26.983 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.009     ; 4.245      ;
; 26.983 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; -0.009     ; 4.245      ;
; 27.058 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 4.317      ;
; 27.058 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 4.317      ;
; 27.060 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.131      ; 4.308      ;
; 27.060 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.131      ; 4.308      ;
; 27.060 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.131      ; 4.308      ;
; 27.060 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.131      ; 4.308      ;
; 27.064 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.141      ; 4.314      ;
; 27.064 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.143      ; 4.316      ;
; 27.065 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.144      ; 4.316      ;
; 27.066 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.141      ; 4.312      ;
; 27.068 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.145      ; 4.314      ;
; 27.070 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 4.305      ;
; 27.070 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.138      ; 4.305      ;
; 27.071 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.153      ; 4.319      ;
; 27.071 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.153      ; 4.319      ;
; 27.072 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 31.250       ; 0.131      ; 4.296      ;
+--------+------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                         ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                         ; To Node                                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 29.695 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.055     ; 1.487      ;
; 29.810 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.055     ; 1.372      ;
; 29.811 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_RD     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.074     ; 1.352      ;
; 29.833 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.055     ; 1.349      ;
; 29.956 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_WR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 31.250       ; -0.074     ; 1.207      ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                                                                                                                                                                                         ;
+-------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                ; To Node                                                                                                          ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[12]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[13]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[14]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[15]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[16]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[18]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.720 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 0.847      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[1]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[2]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[3]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[4]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[5]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[6]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[7]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[8]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[9]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[10]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[11]                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.753 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[0]                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 0.871      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE                                                                     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.904 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.027      ;
; 0.906 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.029      ;
; 0.906 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.029      ;
; 0.906 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.029      ;
; 0.906 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.029      ;
; 1.008 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE                                                                      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.131      ;
; 1.008 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.131      ;
; 1.008 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.039      ; 1.131      ;
; 1.026 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.029      ; 1.139      ;
; 1.073 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.184      ;
; 1.073 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.184      ;
; 1.073 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.184      ;
; 1.166 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 1.284      ;
; 1.166 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE                                                                    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 1.284      ;
; 1.166 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 1.284      ;
; 1.166 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 1.284      ;
; 1.166 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD                                                                ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 1.284      ;
; 1.166 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.034      ; 1.284      ;
; 1.171 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.029      ; 1.284      ;
; 1.171 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.029      ; 1.284      ;
; 1.199 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.310      ;
; 1.199 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ACTIVATE                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.310      ;
; 1.199 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_KEYRELEASE                                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.310      ;
; 1.199 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_PLL_LOCK                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.310      ;
; 1.199 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ATTENTION                                                                 ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.310      ;
; 1.199 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|STARTUP                                                                             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.027      ; 1.310      ;
; 1.224 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.334      ;
; 1.224 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.334      ;
; 1.224 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.334      ;
; 1.224 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.334      ;
; 1.458 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.568      ;
; 1.458 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.568      ;
; 1.458 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.568      ;
; 1.458 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.568      ;
; 1.458 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]                                                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.026      ; 1.568      ;
; 1.519 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[22]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.631      ;
; 1.519 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.631      ;
; 1.519 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.631      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[23]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[21]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[20]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.526 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]                                                                         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.028      ; 1.638      ;
; 1.541 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMDATA                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.023      ; 1.648      ;
; 1.541 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_RAMADDR                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.023      ; 1.648      ;
; 1.541 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_KEY                                                                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.023      ; 1.648      ;
; 1.541 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.GET_JOYSTICK                                                              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.023      ; 1.648      ;
; 1.541 ; RESET_CORE_Sn                                            ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WE_PULSE                                                                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.023      ; 1.648      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.044      ; 1.940      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[7]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.044      ; 1.940      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:3:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[4]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:4:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[4]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:5:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.044      ; 1.940      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:10:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[6] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.044      ; 1.940      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:3:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:4:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[2]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:3:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[3]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:4:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[3]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:7:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[3]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.042      ; 1.938      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:3:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:6:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.042      ; 1.938      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:4:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
; 1.812 ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|CLR_In ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_FIFO:I_FIFO|WF25913IP_FIFO_UNIT:\FIFO:3:I_DMA_FIFO_UNIT|\MEM_UNIT:FIFOCELL[0]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000        ; 0.043      ; 1.939      ;
+-------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                                                                                                                      ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                                                                  ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[11]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[10]                                          ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[9]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[8]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[7]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[6]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[5]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[4]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[3]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[2]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.791 ; RESET_CORE_Sn ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|INIT_STATE[1]                                           ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.077      ; 1.972      ;
; 1.951 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[3]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.134      ; 2.189      ;
; 1.951 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[5]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.134      ; 2.189      ;
; 1.951 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[6]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.134      ; 2.189      ;
; 1.951 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[7]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.134      ; 2.189      ;
; 1.957 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[1]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.131      ; 2.192      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[19]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.124      ; 2.190      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[3]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.186      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[1]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.186      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[17]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.124      ; 2.190      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[4]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.186      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[21]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.124      ; 2.190      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[5]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.186      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[6]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.186      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[0]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.186      ;
; 1.962 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[16]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.124      ; 2.190      ;
; 1.964 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[12]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.121      ; 2.189      ;
; 1.964 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.123      ; 2.191      ;
; 1.964 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[14]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.118      ; 2.186      ;
; 1.964 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.123      ; 2.191      ;
; 1.964 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[8]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.118      ; 2.186      ;
; 1.965 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.189      ;
; 1.967 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[5]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.123      ; 2.194      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[19] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.118      ; 2.190      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[3]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.192      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[1]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.192      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[1]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.119      ; 2.191      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[2]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.192      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[4]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.119      ; 2.191      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[21] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.118      ; 2.190      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[5]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.192      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[22] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.118      ; 2.190      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[7]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.192      ;
; 1.968 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[0]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.120      ; 2.192      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[3]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.102      ; 2.175      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[9]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.118      ; 2.191      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[1]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.102      ; 2.175      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[2]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.102      ; 2.175      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[21]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.115      ; 2.188      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[5]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.102      ; 2.175      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[6]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.102      ; 2.175      ;
; 1.969 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[7]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.102      ; 2.175      ;
; 1.970 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[18] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.121      ; 2.195      ;
; 1.970 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[20] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.121      ; 2.195      ;
; 1.972 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[3]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.116      ; 2.192      ;
; 1.972 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[1]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.116      ; 2.192      ;
; 1.972 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[4]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.116      ; 2.192      ;
; 1.972 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[7]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.116      ; 2.192      ;
; 1.972 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_MID[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.116      ; 2.192      ;
; 1.974 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[19]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.189      ;
; 1.974 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[17]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.189      ;
; 1.974 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[18]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.189      ;
; 1.974 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[21]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.189      ;
; 1.975 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[10]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.109      ; 2.188      ;
; 1.975 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|LINEWIDTH[6]         ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.109      ; 2.188      ;
; 1.975 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[15]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.109      ; 2.188      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[19]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.114      ; 2.194      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[11]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[17] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.106      ; 2.186      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[9]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[10]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[4]                   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.113      ; 2.193      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[20]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.114      ; 2.194      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[12]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[5]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.097      ; 2.177      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[14]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[22]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.114      ; 2.194      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[15]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[8]              ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.184      ;
; 1.976 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|\VIDEO_CNT:LOCK      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.110      ; 2.190      ;
; 1.978 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[18]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.193      ;
; 1.978 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VADR[20]             ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.113      ; 2.195      ;
; 1.978 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[13]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.193      ;
; 1.978 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[23]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.193      ;
; 1.978 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[16]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.111      ; 2.193      ;
; 1.978 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[16] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.112      ; 2.194      ;
; 1.979 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[9]  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.110      ; 2.193      ;
; 1.979 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[5]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.108      ; 2.191      ;
; 1.979 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[6]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.108      ; 2.191      ;
; 1.979 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_LOW[0]    ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.108      ; 2.191      ;
; 1.980 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[23]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.105      ; 2.189      ;
; 1.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_CONTROL[2]      ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.100      ; 2.185      ;
; 1.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[10] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.107      ; 2.192      ;
; 1.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[13] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.107      ; 2.192      ;
; 1.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_CTRL_SD:I_DMA|DMAADR[22]                  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.101      ; 2.186      ;
; 1.981 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_START[15] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.107      ; 2.192      ;
; 1.982 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[3]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.106      ; 2.192      ;
; 1.982 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_DMA_SOUND_SD:I_DMASOUND|SOUND_FRAME_END[17]   ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.104      ; 2.190      ;
; 1.982 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[1]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.106      ; 2.192      ;
; 1.982 ; RESET_Sn      ; WF25912IP_SD_TOP_BTYPE_SOC:I_MCU|WF25912IP_VIDEO_COUNTER_SD:I_VIDEO|VIDEO_BASE_HI[2]     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 0.000        ; 0.106      ; 2.192      ;
+-------+---------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                                                                                                                                                                                          ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                         ; To Node                                                                 ; Launch Clock                                                                                           ; Latch Clock                                                                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+
; 32.179 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_WR     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.020      ; 1.053      ;
; 32.299 ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR     ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|DATA_RD     ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.019      ; 1.172      ;
; 32.330 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR   ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.017      ; 1.201      ;
; 32.338 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.017      ; 1.209      ;
; 32.518 ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|OPCODE_RD_I ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -31.250      ; 0.017      ; 1.389      ;
+--------+-----------------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 12.476 ; 12.692       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 12.476 ; 12.692       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 12.476 ; 12.692       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 12.476 ; 12.692       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
; 12.511 ; 12.695       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 12.511 ; 12.695       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 12.511 ; 12.695       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 12.511 ; 12.695       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
; 12.690 ; 12.690       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] ;
; 12.690 ; 12.690       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk   ;
; 12.691 ; 12.691       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576|clk                                                                 ;
; 12.691 ; 12.691       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                                                     ;
; 12.691 ; 12.691       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                                                     ;
; 12.691 ; 12.691       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                                                     ;
; 12.698 ; 12.698       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576|clk                                                                 ;
; 12.698 ; 12.698       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]|clk                                                     ;
; 12.698 ; 12.698       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]|clk                                                     ;
; 12.698 ; 12.698       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]|clk                                                     ;
; 12.700 ; 12.700       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0] ;
; 12.700 ; 12.700       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk   ;
; 23.390 ; 25.390       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; CLK_24576                                                                     ;
; 23.390 ; 25.390       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[0]                                                         ;
; 23.390 ; 25.390       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[1]                                                         ;
; 23.390 ; 25.390       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; \P_2M4576:TMP_2M54[2]                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]'                                                                                                                                           ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                                                  ; Clock Edge ; Target                                                                                                      ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+
; 15.370 ; 15.600       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a26~porta_address_reg0 ;
; 15.370 ; 15.600       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a26~porta_we_reg       ;
; 15.372 ; 15.602       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a26~porta_datain_reg0  ;
; 15.372 ; 15.602       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a27~porta_address_reg0 ;
; 15.372 ; 15.602       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a27~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a0~porta_address_reg0  ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a0~porta_we_reg        ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a13~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a13~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a14~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a14~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a19~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a19~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a20~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a20~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a23~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a23~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a24~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a24~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a28~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a28~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a2~porta_address_reg0  ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a2~porta_we_reg        ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a35~porta_address_reg0 ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a35~porta_we_reg       ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a3~porta_address_reg0  ;
; 15.373 ; 15.603       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a3~porta_we_reg        ;
; 15.374 ; 15.604       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a27~porta_datain_reg0  ;
; 15.374 ; 15.604       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a31~porta_address_reg0 ;
; 15.374 ; 15.604       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a31~porta_we_reg       ;
; 15.374 ; 15.604       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a4~porta_address_reg0  ;
; 15.374 ; 15.604       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a4~porta_we_reg        ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a13~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a14~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a16~porta_address_reg0 ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a16~porta_we_reg       ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a17~porta_address_reg0 ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a17~porta_we_reg       ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a19~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a1~porta_address_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a1~porta_we_reg        ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a20~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a23~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a24~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a28~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a2~porta_datain_reg0   ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a33~porta_address_reg0 ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a33~porta_we_reg       ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a35~porta_datain_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a38~porta_address_reg0 ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a38~porta_we_reg       ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a39~porta_address_reg0 ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a39~porta_we_reg       ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a3~porta_datain_reg0   ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a47~porta_address_reg0 ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a47~porta_we_reg       ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a5~porta_address_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a5~porta_we_reg        ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a6~porta_address_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a6~porta_we_reg        ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a7~porta_address_reg0  ;
; 15.375 ; 15.605       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a7~porta_we_reg        ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a10~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a10~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a11~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a11~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a12~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a12~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a15~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a15~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a18~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a18~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a21~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a21~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a22~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a22~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a25~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a25~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a29~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a29~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a30~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a30~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a31~porta_datain_reg0  ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a32~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a32~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a34~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a34~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a36~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a36~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a37~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a37~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a40~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a40~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a41~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a41~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a42~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a42~porta_we_reg       ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a43~porta_address_reg0 ;
; 15.376 ; 15.606       ; 0.230          ; Low Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; Rise       ; WF_SD_DRIVES:I_DRIVES|altsyncram:TRAM_rtl_0|altsyncram_dh41:auto_generated|ram_block1a43~porta_we_reg       ;
+--------+--------------+----------------+-----------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 19.312 ; 19.528       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 19.312 ; 19.528       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
; 19.347 ; 19.531       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 19.347 ; 19.531       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
; 19.526 ; 19.526       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.526 ; 19.526       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 19.527 ; 19.527       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4|clk                                                                  ;
; 19.527 ; 19.527       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]|clk                                                         ;
; 19.534 ; 19.534       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4|clk                                                                  ;
; 19.534 ; 19.534       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]|clk                                                         ;
; 19.536 ; 19.536       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 19.536 ; 19.536       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 37.062 ; 39.062       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; SCLK_6M4                                                                      ;
; 37.062 ; 39.062       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; \P_6M4:TMP_6M4[0]                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]'                                                                                                     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                               ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------+
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|LED_1                                          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|LED_2                                          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDHCXC         ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC1          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CARDTYPE.C_SDSC2          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[120]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[121]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[122]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[123]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[124]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[125]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[126]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[127]                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[24]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[25]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[26]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[27]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[28]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[29]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[30]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[31]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[4]                    ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[64]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[65]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[66]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[67]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[68]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[69]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[70]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[71]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[88]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[89]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[90]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[91]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[92]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[93]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[94]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CID[95]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_ERR                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_OUT                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[0]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[18]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[19]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[1]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[20]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[21]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[22]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[23]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[24]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[25]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[26]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[27]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[28]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[29]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[2]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[30]          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[3]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[4]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[5]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[6]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[7]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE[8]           ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_RESPONSE_RDY          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CMD_TRANSMIT_RDY          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CRC_ERR                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[47]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[56]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[57]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[58]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[59]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[60]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[61]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[62]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[63]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[80]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[81]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[82]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|CSD[83]                   ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_ERR                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|DATA_OUT[5]               ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[23]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[24]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[25]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[26]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[27]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[28]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[29]            ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[30]            ;
; 20.616 ; 20.800       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[3]             ;
; 20.616 ; 20.800       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|LAST_BLOCK[7]             ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|RELEASED                  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|REQ_RD                    ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_ERR               ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|Rx_DATA_RDY               ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.IDLE          ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.RECEIVE_DATA  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.TRANSMIT_CMD  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.TRANSMIT_DATA ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_BSY_CMD  ;
; 20.616 ; 20.832       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; Rise       ; WF_SD_DRIVES:I_DRIVES|SDCARD_CTRL:I_SDCARD|SD_BUSPHASE.WAIT_BSY_DATA ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL1'                                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                            ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; 30.520 ; 30.704       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 30.520 ; 30.704       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
; 30.521 ; 30.705       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 30.521 ; 30.705       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 30.521 ; 30.705       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 30.521 ; 30.705       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 30.521 ; 30.705       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 30.521 ; 30.705       ; 0.184          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 30.660 ; 30.660       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 30.660 ; 30.660       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 30.660 ; 30.660       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 30.660 ; 30.660       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]           ;
; 30.660 ; 30.660       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 30.697 ; 30.697       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|o                                                  ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                                                    ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT|clk                                                     ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                                          ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                                          ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                                          ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                                          ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                                          ;
; 30.700 ; 30.700       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                                               ;
; 30.705 ; 30.705       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 30.709 ; 30.709       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|inclk[0]                                    ;
; 30.709 ; 30.709       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|outclk                                      ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|i                                                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|i                                                  ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 31.578 ; 31.794       ; 0.216          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
; 31.790 ; 31.790       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|inclk[0]                                    ;
; 31.790 ; 31.790       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~inputclkctrl|outclk                                      ;
; 31.795 ; 31.795       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT|clk                                                     ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                                          ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                                          ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                                          ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                                          ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                                          ;
; 31.800 ; 31.800       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                                                    ;
; 31.800 ; 31.800       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                                               ;
; 31.803 ; 31.803       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~input|o                                                  ;
; 31.838 ; 31.838       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.838 ; 31.838       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.838 ; 31.838       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.838 ; 31.838       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]           ;
; 31.838 ; 31.838       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 58.500 ; 62.500       ; 4.000          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                                          ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; PLL_ARESET                                                        ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; PLL_FAULT                                                         ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                                              ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                                              ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                                              ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                                              ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                                              ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                                                   ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLK_PLL2'                                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                            ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+
; 30.656 ; 30.656       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 30.656 ; 30.656       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 30.656 ; 30.656       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 30.656 ; 30.656       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 30.691 ; 30.691       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|o                                                  ;
; 30.701 ; 30.701       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|i                                                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|i                                                  ;
; 31.799 ; 31.799       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]         ;
; 31.809 ; 31.809       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2~input|o                                                  ;
; 31.842 ; 31.842       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]           ;
; 31.842 ; 31.842       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]           ;
; 31.842 ; 31.842       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]           ;
; 31.842 ; 31.842       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|pll1|observablevcoout ;
; 58.500 ; 62.500       ; 4.000          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                                          ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                                     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                               ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------+
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[0]                     ;
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[12]                    ;
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[13]                    ;
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ;
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[4]                     ;
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[6]                     ;
; 30.990 ; 31.206       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[8]                     ;
; 30.991 ; 31.207       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[14]                    ;
; 30.993 ; 31.209       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[15]                    ;
; 30.999 ; 31.215       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[16]                    ;
; 31.000 ; 31.216       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[19]                    ;
; 31.003 ; 31.219       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[7]                     ;
; 31.004 ; 31.220       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[18]                    ;
; 31.004 ; 31.220       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[20]                    ;
; 31.006 ; 31.222       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ;
; 31.006 ; 31.222       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[2]                     ;
; 31.006 ; 31.222       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[5]                     ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|AVEC_In                           ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BGACK_In                          ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[10]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[11]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[24]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[25]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[26]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[27]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DSACK_In[0]                       ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DSACK_In[1]                       ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_N[0]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_N[1]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|SLICE_CNT_N[2]                    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_SYNC:BERR_VARn                 ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|\P_SYNC:HALT_VARn                 ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IRQ[1]                   ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|IRQ[2]                   ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\IRQ_FILTER:IRQ_TMP_2[1] ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\IRQ_FILTER:IRQ_TMP_2[2] ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\P_D:DATA_RDY_VAR        ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:BUSY_EXH_VAR      ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:IPIPE_FILL_VAR    ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_OPCODE_DECODER:I_OPCODE_DECODER|\P_BSY:OPCODE_RDY_VAR    ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|BR_In                             ;
; 31.021 ; 31.237       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\IRQ_FILTER:IRQ_TMP_1[1] ;
; 31.021 ; 31.237       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_EXCEPTION_HANDLER:I_EXC_HANDLER|\IRQ_FILTER:IRQ_TMP_1[2] ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[21]                    ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[22]                    ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[23]                    ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[28]                    ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[29]                    ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[30]                    ;
; 31.022 ; 31.238       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Fall       ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[31]                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[32]          ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|\P_IN_USE:DELAY     ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[16]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[17]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[18]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[19]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[20]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[21]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[22]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[23]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[24]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[25]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[26]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[27]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[28]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[29]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[30]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[31]                                                        ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[12]                          ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[1]                           ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[3]                           ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[4]                           ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[6]                           ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[8]                           ;
; 31.033 ; 31.249       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|\DIVISION:DIVISOR[9]                           ;
; 31.034 ; 31.218       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[0]                                                      ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[11]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[14]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[18]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[19]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[1]                                                      ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[20]                                                     ;
; 31.034 ; 31.218       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[22]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[23]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[25]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[26]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[27]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[28]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|ADR_LATCH[31]                                                     ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[10]                                                        ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[11]                                                        ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[12]                                                        ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[13]                                                        ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[14]                                                        ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[15]                                                        ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[1]                                                         ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[2]                                                         ;
; 31.034 ; 31.250       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; WF68K30L_TOP:I_CPU|AR_CPY[3]                                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]'                                                                                                                                          ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                                                    ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------+
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[10]                                          ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[14]                                          ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[21]                                          ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[24]                                          ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[26]                                          ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[30]                                          ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[5]                                           ;
; 30.992 ; 31.208       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[8]                                           ;
; 30.993 ; 31.209       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[13]                                          ;
; 30.993 ; 31.209       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[15]                                          ;
; 30.993 ; 31.209       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[29]                                          ;
; 30.993 ; 31.209       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[31]                                          ;
; 30.993 ; 31.209       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[7]                                           ;
; 30.995 ; 31.211       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[11]                                          ;
; 30.995 ; 31.211       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[19]                                          ;
; 30.995 ; 31.211       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[23]                                          ;
; 30.995 ; 31.211       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[27]                                          ;
; 30.995 ; 31.211       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[3]                                           ;
; 31.002 ; 31.218       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[11]                                         ;
; 31.002 ; 31.218       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[3]                                          ;
; 31.002 ; 31.218       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[7]                                          ;
; 31.003 ; 31.219       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[6]                                          ;
; 31.004 ; 31.220       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[8]                                          ;
; 31.004 ; 31.220       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[0]                                           ;
; 31.004 ; 31.220       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[16]                                          ;
; 31.005 ; 31.221       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[13]                                         ;
; 31.005 ; 31.221       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[15]                                         ;
; 31.006 ; 31.222       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[14]                                         ;
; 31.006 ; 31.222       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[5]                                          ;
; 31.006 ; 31.222       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[9]                                          ;
; 31.007 ; 31.223       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[0]                                          ;
; 31.007 ; 31.223       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[1]                                          ;
; 31.007 ; 31.223       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[2]                                          ;
; 31.007 ; 31.223       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[4]                                          ;
; 31.009 ; 31.225       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[18]                                          ;
; 31.009 ; 31.225       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[22]                                          ;
; 31.009 ; 31.225       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[2]                                           ;
; 31.009 ; 31.225       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[6]                                           ;
; 31.010 ; 31.226       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[17]                                          ;
; 31.010 ; 31.226       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[1]                                           ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[12]                                         ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[12]                                          ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[20]                                          ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[28]                                          ;
; 31.019 ; 31.235       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[4]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|DTACK_OUT_In                                                                 ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_BUFF[10]                                         ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[0]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[10]                                          ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[12]                                          ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[13]                                          ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[14]                                          ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[15]                                          ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[2]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[3]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[4]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[5]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[6]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[8]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[25]                                          ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|SRC_BUFF[9]                                           ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CTRL:I_CTRL|WAITSTATES                                            ;
; 31.020 ; 31.236       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|\DTACK_OUT:DTACK_DELAY                                                       ;
; 31.021 ; 31.237       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In                                           ;
; 31.021 ; 31.237       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF68901IP_TOP_SOC:I_MFP|DTACK_OUTn                                                                        ;
; 31.021 ; 31.237       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF68901IP_TOP_SOC:I_MFP|\DTACK_OUT:DTACK_DELAY                                                            ;
; 31.021 ; 31.237       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF_SD_DRIVES:I_DRIVES|WF_FLOPPY:I_FLOPPY|FLOPPY_DPLL:DIGITAL_PLL|WD_In                                    ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[11]                                          ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[1]                                           ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[7]                                           ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|NEW_DEST[9]                                           ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_CTRL:I_DMA_CTRL|HDRQ_I                                                  ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ;
; 31.023 ; 31.239       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Fall       ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ;
; 31.031 ; 31.215       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; VMA_68K30Ln                                                                                               ;
; 31.031 ; 31.215       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_MODE_REG[2]                                     ;
; 31.031 ; 31.215       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_MODE_REG[3]                                     ;
; 31.031 ; 31.215       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_MODE_REG[4]                                     ;
; 31.031 ; 31.215       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_MODE_REG[8]                                     ;
; 31.031 ; 31.215       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF25913IP_TOP_SOC:I_DMA|WF25913IP_REGISTERS:I_DMAREGS|DMA_MODE_REG[9]                                     ;
; 31.032 ; 31.248       ; 0.216          ; High Pulse Width ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|DEST_ADR[4]                                           ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK3[0]                                           ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK3[10]                                          ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK3[1]                                           ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|ENDMASK3[2]                                           ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][0]                                   ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][10]                                  ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][6]                                   ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[14][7]                                   ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][12]                                   ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][1]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][4]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][5]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][6]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][8]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[2][9]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[4][5]                                    ;
; 31.032 ; 31.216       ; 0.184          ; Low Pulse Width  ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; Rise       ; WF101643IP_TOP_SOC:I_BLITTER|WF101643IP_CORE:I_CORE|HALFTONE_RAM[8][2]                                    ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]'                                                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 31.032 ; 31.248       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 31.032 ; 31.248       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 31.032 ; 31.248       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
; 31.037 ; 31.221       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 31.037 ; 31.221       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 31.037 ; 31.221       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 31.060 ; 31.276       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 31.060 ; 31.276       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 31.060 ; 31.276       ; 0.216          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 31.067 ; 31.251       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 31.067 ; 31.251       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 31.067 ; 31.251       ; 0.184          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
; 31.217 ; 31.217       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                                                      ;
; 31.217 ; 31.217       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                                                      ;
; 31.217 ; 31.217       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                                                      ;
; 31.245 ; 31.245       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ;
; 31.245 ; 31.245       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk   ;
; 31.246 ; 31.246       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5|clk                                                                   ;
; 31.246 ; 31.246       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0|clk                                                                   ;
; 31.246 ; 31.246       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                                                      ;
; 31.253 ; 31.253       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5|clk                                                                   ;
; 31.253 ; 31.253       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0|clk                                                                   ;
; 31.253 ; 31.253       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]|clk                                                      ;
; 31.254 ; 31.254       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ;
; 31.254 ; 31.254       ; 0.000          ; Low Pulse Width  ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; I_AUXCLOCKS|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk   ;
; 31.282 ; 31.282       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                                                      ;
; 31.282 ; 31.282       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                                                      ;
; 31.282 ; 31.282       ; 0.000          ; High Pulse Width ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]|clk                                                      ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_0M5                                                                       ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; CLK_2M0                                                                       ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                                          ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                                          ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[2]                                                          ;
; 60.500 ; 62.500       ; 2.000          ; Min Period       ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; Rise       ; \P_AUX_CLOCKS:TMP[3]                                                          ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; -0.100 ; 0.396  ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; 4.511  ; 5.502  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 12.261 ; 13.325 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 9.001  ; 9.802  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 8.845  ; 9.626  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 12.261 ; 13.325 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 12.120 ; 13.117 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 12.202 ; 13.243 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 7.429  ; 8.646  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 6.301  ; 7.604  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 6.346  ; 7.678  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 6.445  ; 7.703  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 6.586  ; 7.928  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 5.902  ; 7.152  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 5.780  ; 6.938  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 6.540  ; 7.896  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 6.621  ; 7.978  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 6.111  ; 7.371  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 7.084  ; 8.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 6.936  ; 8.066  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 7.022  ; 8.230  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 7.429  ; 8.646  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 6.208  ; 7.306  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 5.467  ; 6.445  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 5.518  ; 6.538  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 2.945  ; 3.806  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; 2.258  ; 2.622  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 3.544  ; 4.347  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; 3.754  ; 4.669  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; 2.284  ; 3.029  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 2.583  ; 3.384  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.367  ; 9.468  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.328  ; 8.717  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.284  ; 8.668  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.762  ; 9.118  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 7.327  ; 8.683  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.468  ; 7.728  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.511  ; 7.711  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.883  ; 8.194  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.846  ; 8.176  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.816  ; 8.127  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.914  ; 9.367  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 7.093  ; 8.181  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 6.804  ; 7.986  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.298  ; 7.329  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.532  ; 7.367  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.639  ; 7.495  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.367  ; 9.468  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; 1.187  ; 1.686  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 3.171  ; 4.083  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; 7.566  ; 8.561  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 3.922  ; 4.833  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; 3.922  ; 4.833  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; 3.621  ; 4.559  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 2.913  ; 3.768  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; 3.041  ; 3.927  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 3.810  ; 4.722  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 10.394 ; 11.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 7.426  ; 8.227  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 7.270  ; 8.051  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 10.394 ; 11.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 10.253 ; 11.241 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 10.335 ; 11.367 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 5.456  ; 6.633  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 4.652  ; 5.774  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 4.699  ; 5.827  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 4.785  ; 5.898  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 5.102  ; 6.273  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 4.553  ; 5.645  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 4.375  ; 5.387  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 5.062  ; 6.239  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 5.211  ; 6.403  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 4.616  ; 5.714  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 5.456  ; 6.633  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 4.799  ; 5.897  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 5.078  ; 6.169  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 5.359  ; 6.503  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 3.992  ; 5.069  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 3.761  ; 4.748  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 3.441  ; 4.446  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 6.286  ; 7.539  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 5.679  ; 6.887  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 5.637  ; 6.817  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 6.102  ; 7.313  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 5.843  ; 7.028  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 5.119  ; 6.221  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.106  ; 6.160  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.405  ; 6.537  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.436  ; 6.601  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 5.321  ; 6.470  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.286  ; 7.539  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.956  ; 6.012  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.860  ; 5.925  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.228  ; 5.186  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.295  ; 5.130  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.940  ; 5.796  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 6.184  ; 7.285  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 10.720 ; 11.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; 7.740  ; 8.541  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; 7.584  ; 8.365  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 10.720 ; 11.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 10.579 ; 11.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 10.661 ; 11.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; 5.530  ; 6.744  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; 4.989  ; 6.131  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; 4.958  ; 6.130  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; 5.346  ; 6.520  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; 5.530  ; 6.744  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; 4.799  ; 5.918  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; 4.871  ; 5.927  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; 5.414  ; 6.652  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; 5.505  ; 6.717  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; 4.744  ; 5.855  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 6.663  ; 7.935  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.016  ; 7.244  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 5.896  ; 7.120  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 6.663  ; 7.935  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.271  ; 7.499  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 5.365  ; 6.494  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.602  ; 6.700  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.757  ; 6.950  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.730  ; 6.915  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 5.449  ; 6.611  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.412  ; 5.076  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.764  ; 5.506  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.411  ; 5.099  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.903  ; 5.628  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.862  ; 5.553  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.926  ; 5.657  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.794  ; 5.485  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; 5.403  ; 6.493  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 6.279  ; 7.314  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 6.279  ; 7.314  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 6.138  ; 7.106  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 6.220  ; 7.232  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 11.399 ; 12.434 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 11.399 ; 12.434 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 11.258 ; 12.226 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 11.340 ; 12.352 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; 11.206 ; 12.241 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; 8.252  ; 9.053  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; 8.096  ; 8.877  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 11.206 ; 12.241 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 11.065 ; 12.033 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 11.147 ; 12.159 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; 6.405  ; 7.722  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; 5.132  ; 6.293  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; 5.455  ; 6.643  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; 5.782  ; 6.951  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; 5.623  ; 6.837  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; 4.963  ; 6.098  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; 5.252  ; 6.286  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; 5.705  ; 6.913  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; 5.943  ; 7.229  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; 5.595  ; 6.793  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; 6.405  ; 7.722  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; 5.885  ; 7.084  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; 6.005  ; 7.175  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; 6.186  ; 7.440  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; 4.974  ; 6.072  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; 4.226  ; 5.234  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; 4.313  ; 5.403  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.235  ; 8.628  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.159  ; 7.406  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 6.393  ; 7.633  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.099  ; 8.366  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.364  ; 7.592  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 5.529  ; 6.674  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.983  ; 7.059  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.048  ; 7.211  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.168  ; 7.427  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.300  ; 7.549  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.235  ; 8.628  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 6.042  ; 7.199  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 5.787  ; 6.931  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 5.055  ; 6.123  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 5.298  ; 6.133  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 5.428  ; 6.284  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.232  ; 8.333  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 4.127  ; 4.946  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; 4.940  ; 5.794  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                         ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; 0.435  ; -0.073 ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; -2.600 ; -3.406 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -2.413 ; -3.203 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -2.567 ; -3.373 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -2.413 ; -3.203 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.969 ; -4.927 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.896 ; -4.824 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.632 ; -5.606 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -2.539 ; -3.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -3.240 ; -4.238 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -3.162 ; -4.134 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -3.449 ; -4.472 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -3.349 ; -4.362 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -2.539 ; -3.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -3.117 ; -4.100 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -3.677 ; -4.735 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -3.078 ; -4.074 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -3.020 ; -3.977 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -3.396 ; -4.396 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -3.344 ; -4.349 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -3.125 ; -4.043 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -4.085 ; -5.173 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -3.566 ; -4.572 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -3.378 ; -4.340 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -3.421 ; -4.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; -2.521 ; -3.369 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; -1.473 ; -1.857 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; -2.484 ; -3.323 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; -2.777 ; -3.691 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; -1.885 ; -2.623 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; -2.129 ; -2.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.813 ; -4.769 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -5.132 ; -6.258 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -5.256 ; -6.397 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -5.770 ; -6.966 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -5.496 ; -6.643 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.199 ; -5.220 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.828 ; -5.885 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -5.111 ; -6.224 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.878 ; -5.993 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -5.116 ; -6.244 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -5.956 ; -7.203 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.795 ; -5.867 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.633 ; -5.675 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.813 ; -4.769 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -4.061 ; -4.893 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -4.382 ; -5.232 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -5.961 ; -7.026 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; -0.835 ; -1.336 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; -2.722 ; -3.621 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; -3.013 ; -3.832 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; -2.746 ; -3.644 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; -2.846 ; -3.752 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; -2.746 ; -3.644 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; -2.345 ; -3.159 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; -2.578 ; -3.443 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; -2.362 ; -3.175 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -3.435 ; -4.363 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -6.112 ; -6.939 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -5.958 ; -6.769 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.508 ; -4.466 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.435 ; -4.363 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.043 ; -5.054 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -2.324 ; -3.227 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -2.954 ; -3.929 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -2.502 ; -3.389 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -2.937 ; -3.891 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -2.324 ; -3.227 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -2.803 ; -3.698 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -2.799 ; -3.749 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -3.105 ; -4.124 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -2.858 ; -3.844 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -2.537 ; -3.453 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -2.782 ; -3.725 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -2.906 ; -3.866 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -2.683 ; -3.571 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -3.811 ; -4.853 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -2.915 ; -3.883 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -2.772 ; -3.671 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -2.768 ; -3.721 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.410 ; -4.242 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -4.840 ; -5.943 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -4.937 ; -6.051 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -5.258 ; -6.385 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -5.157 ; -6.278 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.463 ; -5.508 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.510 ; -5.534 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -4.601 ; -5.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.658 ; -5.763 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -4.633 ; -5.720 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -5.342 ; -6.532 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.357 ; -5.384 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.191 ; -5.203 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.539 ; -4.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -3.410 ; -4.242 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -3.776 ; -4.626 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -5.308 ; -6.373 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -2.187 ; -2.971 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; -2.356 ; -3.131 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; -2.187 ; -2.971 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.387 ; -4.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.314 ; -4.239 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.017 ; -4.974 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; -2.246 ; -3.111 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; -2.544 ; -3.464 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; -2.463 ; -3.345 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; -2.246 ; -3.111 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; -2.482 ; -3.375 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; -2.562 ; -3.420 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; -2.523 ; -3.437 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; -2.719 ; -3.692 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; -2.682 ; -3.605 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; -2.797 ; -3.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -1.752 ; -2.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -1.752 ; -2.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -2.035 ; -2.774 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -1.899 ; -2.634 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -2.058 ; -2.809 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -2.031 ; -2.785 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -2.034 ; -2.782 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -1.987 ; -2.723 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -2.004 ; -2.764 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -2.134 ; -2.915 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -2.030 ; -2.805 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -2.032 ; -2.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -2.017 ; -2.773 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -2.042 ; -2.797 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -2.026 ; -2.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -2.073 ; -2.862 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -2.130 ; -2.909 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; -2.657 ; -3.487 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -3.959 ; -4.845 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -4.087 ; -5.021 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.959 ; -4.845 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.037 ; -4.967 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -4.821 ; -5.837 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -4.894 ; -5.940 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -4.821 ; -5.837 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -5.593 ; -6.588 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; -3.701 ; -4.668 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; -6.230 ; -7.057 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; -6.076 ; -6.887 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.774 ; -4.771 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.701 ; -4.668 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.473 ; -5.419 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; -2.569 ; -3.485 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; -3.096 ; -4.103 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; -3.260 ; -4.260 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; -2.570 ; -3.487 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; -2.569 ; -3.485 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; -2.843 ; -3.758 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; -2.937 ; -3.897 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; -3.133 ; -4.146 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; -2.674 ; -3.589 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; -3.218 ; -4.215 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; -3.452 ; -4.463 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; -3.441 ; -4.438 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; -3.350 ; -4.310 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; -4.184 ; -5.297 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; -3.556 ; -4.560 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; -3.216 ; -4.149 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; -3.263 ; -4.260 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.912 ; -4.883 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -4.988 ; -6.122 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -5.303 ; -6.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -5.508 ; -6.672 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -5.136 ; -6.259 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.391 ; -5.454 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.640 ; -5.679 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -4.803 ; -5.887 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.776 ; -5.874 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -5.314 ; -6.482 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -6.012 ; -7.270 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.892 ; -5.956 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.858 ; -5.942 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.912 ; -4.893 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -4.051 ; -4.883 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -4.220 ; -5.070 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -5.803 ; -6.868 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; -1.880 ; -2.606 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; -2.524 ; -3.329 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                              ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 5.956  ; 5.912  ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 11.212 ; 11.304 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 10.092 ; 10.421 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 9.891  ; 10.228 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 10.155 ; 10.472 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.513 ; 10.864 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 10.429 ; 10.767 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.212 ; 11.304 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 10.227 ; 10.562 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 10.167 ; 10.513 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 9.146  ; 9.422  ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.174  ; 9.461  ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.603  ; 8.822  ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.756  ; 9.008  ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.515  ; 8.734  ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.346  ; 9.325  ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.602 ; 10.757 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 9.847  ; 9.955  ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 7.211  ; 7.407  ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 9.214  ; 9.229  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 5.891  ; 6.222  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 5.826  ; 6.171  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 5.081  ; 5.200  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 5.282  ; 5.478  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 5.382  ; 5.513  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 5.750  ; 5.906  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 5.458  ; 5.615  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 5.149  ; 5.245  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 4.984  ; 5.049  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 5.815  ; 5.910  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 5.728  ; 5.888  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 7.267  ; 7.203  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 5.271  ; 5.472  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 5.371  ; 5.542  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 5.542  ; 5.872  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 8.456  ; 8.632  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 8.373  ; 8.485  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 9.214  ; 9.229  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 5.040  ; 5.207  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 4.843  ; 5.017  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 5.655  ; 5.946  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 5.433  ; 5.726  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 3.284  ; 3.454  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 2.222  ; 2.192  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 2.478  ; 2.510  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 2.816  ; 2.857  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 3.450  ; 3.289  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 6.108  ; 5.882  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 4.330  ; 4.429  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 4.630  ; 4.587  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 4.158  ; 4.249  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 4.461  ; 4.383  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 5.158  ; 5.380  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 6.108  ; 5.882  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 4.572  ; 4.698  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 4.676  ; 4.792  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 3.974  ; 4.041  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 4.018  ; 4.079  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 4.154  ; 4.242  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 4.538  ; 4.656  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 4.236  ; 4.301  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 4.370  ; 4.473  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 4.359  ; 4.467  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 4.595  ; 4.708  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 3.568  ; 3.572  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 3.192  ; 3.362  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 2.381  ; 2.434  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 3.044  ; 3.202  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 9.314  ; 9.420  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 10.820 ; 10.691 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 3.806  ; 3.590  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 2.619  ; 2.703  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 4.393  ; 4.677  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 5.746  ; 5.614  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 4.301  ; 4.216  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 3.014  ; 3.170  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 7.895  ; 7.690  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 6.404  ; 6.463  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 6.774  ; 6.814  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 6.050  ; 6.096  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 6.918  ; 6.953  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 6.924  ; 6.997  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 6.777  ; 6.835  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 6.912  ; 7.022  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 6.921  ; 7.003  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 7.895  ; 7.690  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 6.272  ; 6.353  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 6.835  ; 6.905  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 6.416  ; 6.429  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 7.200  ; 7.240  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 7.479  ; 7.722  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 5.730  ; 5.875  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 7.479  ; 7.722  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 9.052  ; 9.447  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 13.467 ; 13.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.293 ; 12.438 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 11.385 ; 11.458 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.034 ; 12.117 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.013 ; 12.127 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.502 ; 11.878 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.410 ; 13.313 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 11.848 ; 11.923 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 11.700 ; 11.799 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 11.838 ; 11.954 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 12.417 ; 12.527 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 11.937 ; 11.972 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 12.662 ; 12.743 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 12.239 ; 12.348 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.610 ; 12.719 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.521 ; 12.676 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 13.467 ; 13.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 6.084  ; 6.311  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 6.463  ; 6.860  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 6.249  ; 6.537  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 4.096  ; 4.147  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 3.312  ; 3.522  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 7.921  ; 7.936  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;        ; 4.679  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;        ; 4.212  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;        ; 3.907  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;        ; 4.044  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;        ; 4.220  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;        ; 4.447  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;        ; 4.322  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;        ; 3.952  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;        ; 3.756  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;        ; 4.347  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;        ; 4.595  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;        ; 5.910  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;        ; 4.096  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;        ; 4.207  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;        ; 4.390  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 7.163  ; 7.339  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 7.080  ; 6.881  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 7.921  ; 7.936  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 8.021  ; 8.029  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 9.527  ; 9.300  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 6.602  ; 6.397  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 5.069  ; 5.128  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 5.213  ; 5.293  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.581  ; 4.642  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 5.370  ; 5.405  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 5.246  ; 5.319  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 5.410  ; 5.477  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 5.619  ; 5.729  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 5.628  ; 5.710  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.602  ; 6.397  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.709  ; 4.790  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 5.542  ; 5.612  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 5.123  ; 5.136  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.824  ; 5.864  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 6.046  ; 6.427  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;        ; 4.582  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 6.046  ; 6.427  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 7.619  ; 8.152  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 11.516 ; 11.488 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 10.183 ; 10.328 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 9.871  ; 10.163 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 10.142 ; 10.505 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.402 ; 10.717 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 10.207 ; 10.583 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.516 ; 11.419 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 9.996  ; 10.230 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 9.904  ; 10.260 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 10.286 ; 10.256 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 10.307 ; 10.417 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 10.083 ; 10.118 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.552 ; 10.633 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.129 ; 10.238 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.500 ; 10.609 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.354 ; 10.509 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 11.357 ; 11.488 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.789  ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 5.168  ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 8.099  ; 8.186  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 7.413  ; 7.589  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 7.402  ; 7.440  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 8.099  ; 8.186  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 4.179  ; 4.088  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 4.016  ; 3.991  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 4.073  ; 4.088  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 4.179  ; 4.031  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 4.174  ; 4.060  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 5.619  ; 5.392  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 5.619  ; 5.392  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 4.697  ; 4.750  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 4.053  ; 4.001  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 3.399  ; 3.430  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 4.534  ; 4.491  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 4.534  ; 4.491  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 4.060  ; 4.032  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 4.388  ; 4.281  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 4.382  ; 4.393  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 4.283  ; 4.036  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 8.260  ; 8.178  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 9.766  ; 9.449  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 3.308  ; 3.380  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 6.629  ; 6.451  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 5.177  ; 5.240  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.331  ; 4.255  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.934  ; 4.995  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 5.001  ; 5.036  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 5.248  ; 5.321  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 5.124  ; 5.417  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 5.021  ; 5.131  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 5.621  ; 5.707  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.629  ; 6.451  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 5.621  ; 5.897  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 5.876  ; 5.636  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.694  ; 4.707  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.416  ; 5.456  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 7.640  ; 8.012  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 3.782  ; 3.961  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 7.640  ; 8.012  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 9.213  ; 9.737  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 1.337  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 12.564 ; 12.680 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 11.209 ; 11.640 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 11.434 ; 11.748 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 11.727 ; 12.090 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 11.987 ; 12.302 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.792 ; 12.168 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.564 ; 12.680 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 11.406 ; 11.815 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 11.489 ; 11.845 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 11.871 ; 12.149 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 11.168 ; 11.366 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 10.416 ; 10.756 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.979 ; 11.182 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.871 ; 11.279 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.927 ; 11.036 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 11.612 ; 11.767 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 11.784 ; 11.915 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 5.227  ; 5.399  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 5.606  ; 5.948  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 4.551  ; 4.659  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 4.725  ; 4.854  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 5.762  ; 6.184  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 1.304  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;        ; 1.312  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;        ; 1.279  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 13.005 ; 13.213 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 9.065  ; 9.313  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 8.941  ; 9.149  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 8.519  ; 8.697  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 8.668  ; 8.837  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 8.816  ; 9.005  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 9.148  ; 9.348  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 8.998  ; 9.220  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 8.731  ; 8.887  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 8.546  ; 8.696  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 9.129  ; 9.348  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 9.338  ; 9.580  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 10.920 ; 10.900 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 9.000  ; 9.180  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 9.208  ; 9.379  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 9.364  ; 9.613  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 12.440 ; 12.616 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 12.357 ; 12.294 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 13.005 ; 13.213 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 13.298 ; 13.229 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 14.804 ; 14.500 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 11.639 ; 11.461 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 10.241 ; 10.300 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 10.436 ; 10.516 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 9.663  ; 9.709  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 10.349 ; 10.384 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 10.616 ; 10.689 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 10.735 ; 10.802 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 10.291 ; 10.401 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 10.737 ; 10.819 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 11.639 ; 11.461 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 9.710  ; 9.791  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 10.527 ; 10.597 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.113 ; 10.126 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 10.908 ; 10.948 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 11.448 ; 11.630 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 9.745  ; 9.998  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 11.448 ; 11.630 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 13.021 ; 13.355 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 16.203 ; 16.334 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 15.029 ; 15.174 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 15.131 ; 15.317 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 15.029 ; 15.392 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 15.289 ; 15.604 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 15.282 ; 15.470 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 16.160 ; 16.049 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 14.934 ; 15.156 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 14.791 ; 15.147 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 15.443 ; 15.681 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 15.187 ; 15.333 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 14.673 ; 14.708 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 15.398 ; 15.479 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 15.102 ; 15.432 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 15.346 ; 15.455 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 15.629 ; 15.784 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 16.203 ; 16.334 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 8.944  ; 9.136  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 8.968  ; 9.106  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 6.572  ; 6.602  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 4.640  ; 4.608  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 7.141  ; 7.234  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 6.461  ; 6.637  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 6.450  ; 6.482  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 7.141  ; 7.234  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 7.308  ; 7.220  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 8.814  ; 8.491  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 6.682  ; 7.060  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 6.682  ; 7.060  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 8.255  ; 8.785  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 11.955 ; 12.071 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 10.753 ; 11.039 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 10.825 ; 11.139 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 11.118 ; 11.481 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 11.378 ; 11.693 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.183 ; 11.559 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.955 ; 12.071 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 10.797 ; 11.206 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 10.880 ; 11.236 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 11.262 ; 11.508 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 10.559 ; 10.725 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.807  ; 10.147 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.021 ; 10.573 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.477 ; 10.807 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.300 ; 10.407 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 11.192 ; 11.347 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 11.014 ; 11.122 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 6.534  ; 6.540  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 6.505  ; 6.558  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 2.207  ; 2.234  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 4.498  ; 4.423  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 3.739  ; 3.945  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 2.701  ; 2.683  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 4.935  ; 5.005  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 4.935  ; 5.005  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 3.468  ; 3.602  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 2.267  ; 2.277  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                    ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 5.826 ; 5.758 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.012 ; 7.023 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.522 ; 7.792 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.584 ; 7.858 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.160 ; 8.480 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.864 ; 9.119 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 7.884 ; 8.176 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 9.277 ; 9.351 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 7.491 ; 7.684 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 7.626 ; 7.781 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 7.885 ; 8.004 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.685 ; 7.804 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 7.033 ; 7.048 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 7.186 ; 7.238 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 7.462 ; 7.589 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 7.012 ; 7.023 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 7.896 ; 7.995 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.349 ; 7.411 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 6.989 ; 7.169 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 2.296 ; 2.366 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 3.070 ; 3.105 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 3.210 ; 3.289 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 2.594 ; 2.668 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 3.096 ; 3.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 2.669 ; 2.680 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 2.820 ; 2.871 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 2.677 ; 2.718 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 2.796 ; 2.826 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 2.643 ; 2.650 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 2.882 ; 2.927 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 2.441 ; 2.438 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 3.990 ; 3.855 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 2.425 ; 2.503 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 2.495 ; 2.587 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 2.296 ; 2.378 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 2.303 ; 2.366 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 2.439 ; 2.548 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 2.726 ; 2.848 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 2.999 ; 3.144 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 2.798 ; 2.947 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 3.581 ; 3.844 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 3.302 ; 3.561 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 2.607 ; 2.689 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 1.948 ; 1.921 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 2.199 ; 2.227 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 2.523 ; 2.561 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 2.489 ; 2.407 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 2.509 ; 2.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 2.986 ; 3.143 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 2.896 ; 3.048 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 2.866 ; 3.047 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 2.847 ; 2.932 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 3.379 ; 3.397 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 4.696 ; 4.558 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 3.263 ; 3.340 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 2.959 ; 3.123 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 2.509 ; 2.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 2.574 ; 2.700 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 2.679 ; 2.825 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 2.993 ; 3.172 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 2.746 ; 2.859 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 2.844 ; 2.993 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 2.877 ; 3.041 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 3.056 ; 3.231 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 3.062 ; 2.918 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 2.656 ; 2.788 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 2.103 ; 2.151 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 2.488 ; 2.596 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 3.096 ; 3.226 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 4.673 ; 4.565 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 3.132 ; 2.950 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 2.335 ; 2.413 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 3.451 ; 3.651 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 3.526 ; 3.343 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 4.005 ; 3.914 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 2.709 ; 2.858 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 4.036 ; 4.087 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 4.288 ; 4.348 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.218 ; 4.250 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.036 ; 4.087 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 4.273 ; 4.341 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 4.484 ; 4.543 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 4.645 ; 4.700 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 4.655 ; 4.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 4.386 ; 4.513 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.000 ; 5.795 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.169 ; 4.207 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 4.948 ; 4.995 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.478 ; 4.484 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.123 ; 5.162 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 4.115 ; 4.583 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 4.115 ; 4.583 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 4.585 ; 4.718 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 5.114 ; 5.418 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.444 ; 3.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 3.599 ; 3.774 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 3.444 ; 3.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 4.164 ; 4.427 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 4.500 ; 4.616 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.257 ; 4.275 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.310 ; 5.263 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 3.808 ; 3.994 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 3.789 ; 3.970 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.317 ; 4.405 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.122 ; 4.319 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 3.659 ; 3.787 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 3.671 ; 3.794 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.082 ; 4.256 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.516 ; 3.603 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.195 ; 4.319 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 3.460 ; 3.601 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.151 ; 4.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 4.508 ; 4.809 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 5.155 ; 5.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 3.396 ; 3.468 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 2.996 ; 3.195 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 4.585 ; 3.422 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;       ; 4.312 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;       ; 3.844 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;       ; 3.561 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;       ; 3.654 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;       ; 3.871 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;       ; 4.059 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;       ; 3.940 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;       ; 3.566 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;       ; 3.422 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;       ; 3.944 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;       ; 4.206 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;       ; 5.515 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;       ; 3.723 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;       ; 3.830 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;       ; 4.004 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 4.836 ; 4.411 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 4.585 ; 4.654 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 5.358 ; 4.716 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 5.780 ; 5.645 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.287 ; 6.917 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 4.108 ; 4.152 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 4.440 ; 4.463 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.431 ; 4.419 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.108 ; 4.152 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 4.471 ; 4.445 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 4.622 ; 4.674 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 4.848 ; 4.851 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 4.801 ; 4.849 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 4.487 ; 4.527 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.054 ; 5.868 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.307 ; 4.341 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 5.128 ; 5.131 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.711 ; 4.673 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.364 ; 5.366 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 5.072 ; 4.209 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;       ; 4.209 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 5.072 ; 5.321 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 5.279 ; 6.263 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 4.446 ; 4.457 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 4.757 ; 4.769 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.533 ; 4.585 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 4.766 ; 4.805 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 5.001 ; 5.033 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.446 ; 4.457 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.964 ; 5.772 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 4.582 ; 4.600 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 4.655 ; 4.682 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.561 ; 4.651 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.526 ; 4.613 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.465 ; 4.783 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.657 ; 4.754 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.973 ; 5.055 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.483 ; 4.785 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.703 ; 4.812 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.839 ; 5.173 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.316 ;       ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 4.673 ;       ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 5.045 ; 5.142 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 5.329 ; 5.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 5.045 ; 5.142 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 5.625 ; 5.766 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 2.690 ; 2.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 2.720 ; 2.850 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 3.028 ; 3.225 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 2.690 ; 2.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 2.793 ; 2.896 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 2.667 ; 2.797 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 4.596 ; 4.552 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 3.391 ; 3.629 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 2.667 ; 2.797 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 2.963 ; 3.057 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 2.776 ; 2.922 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 3.180 ; 3.381 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 3.022 ; 3.216 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 2.776 ; 2.922 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 3.075 ; 3.240 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 3.895 ; 3.658 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 6.253 ; 6.150 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.760 ; 7.422 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 2.616 ; 2.697 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 2.484 ; 2.377 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 3.016 ; 3.163 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 2.589 ; 2.691 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 2.702 ; 2.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 2.787 ; 2.868 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 2.883 ; 3.001 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 2.681 ; 2.774 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 2.893 ; 3.024 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 3.121 ; 3.275 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 4.096 ; 3.953 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 2.894 ; 2.904 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 2.898 ; 2.914 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 2.484 ; 2.377 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 2.627 ; 2.557 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 2.628 ; 2.663 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 2.628 ; 2.663 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 2.737 ; 2.844 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 3.262 ; 3.202 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 1.107 ;       ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 2.309 ; 2.331 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 2.389 ; 2.400 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 2.526 ; 2.487 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 2.495 ; 2.592 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 2.724 ; 2.739 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 2.309 ; 2.331 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 3.826 ; 3.645 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 2.445 ; 2.474 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 2.513 ; 2.551 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 2.739 ; 2.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 2.669 ; 2.756 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 2.515 ; 2.599 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 2.600 ; 2.632 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 2.801 ; 2.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 2.689 ; 2.684 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 2.708 ; 2.808 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 2.990 ; 3.037 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 2.592 ; 2.530 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 2.717 ; 2.676 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 2.743 ; 2.721 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 2.606 ; 2.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 4.626 ; 5.001 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 1.074 ;       ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;       ; 1.081 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;       ; 1.048 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 3.551 ; 3.672 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 4.315 ; 4.556 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 3.991 ; 4.206 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 3.617 ; 3.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 3.661 ; 3.837 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 3.827 ; 3.997 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 4.089 ; 4.283 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 3.966 ; 4.158 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 3.623 ; 3.788 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 3.551 ; 3.672 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 3.971 ; 4.159 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 4.205 ; 4.349 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 5.743 ; 5.713 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 3.788 ; 3.942 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 3.891 ; 4.054 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 4.406 ; 4.599 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 4.736 ; 4.910 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 4.265 ; 4.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 5.060 ; 5.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 5.574 ; 5.566 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.081 ; 6.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 4.189 ; 4.249 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 4.438 ; 4.498 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.506 ; 4.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.189 ; 4.249 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 4.377 ; 4.445 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 4.523 ; 4.582 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 4.794 ; 4.884 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 4.786 ; 4.841 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 4.524 ; 4.651 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.053 ; 5.848 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.344 ; 4.382 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 5.042 ; 5.089 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.588 ; 4.594 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.255 ; 5.294 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 4.343 ; 4.526 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 4.343 ; 4.526 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 4.790 ; 4.975 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 5.135 ; 5.452 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.900 ; 4.120 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 4.279 ; 4.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.274 ; 4.551 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 4.849 ; 4.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 4.838 ; 4.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.545 ; 4.563 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.061 ; 5.876 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 4.623 ; 4.705 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 4.492 ; 4.786 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.719 ; 4.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.684 ; 4.768 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.223 ; 4.446 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.270 ; 4.536 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.635 ; 4.939 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.900 ; 4.120 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.571 ; 4.875 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.438 ; 4.647 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.188 ; 4.368 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 4.158 ; 4.379 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 4.821 ; 4.790 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 4.274 ; 4.239 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 4.589 ; 4.879 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 5.060 ; 5.234 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 4.589 ; 4.879 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 5.418 ; 5.544 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 5.988 ; 5.890 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.495 ; 7.162 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 5.543 ; 5.925 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 5.543 ; 5.925 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 5.948 ; 6.212 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 4.737 ; 4.889 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 5.351 ; 5.684 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.874 ; 5.160 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.451 ; 5.765 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 5.326 ; 5.671 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.110 ; 6.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.129 ; 7.176 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.539 ; 5.894 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.523 ; 5.897 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.180 ; 6.560 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 5.899 ; 6.290 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 5.742 ; 6.066 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.973 ; 5.203 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 5.685 ; 6.028 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.737 ; 4.889 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 5.638 ; 5.859 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 5.564 ; 5.790 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 5.001 ; 5.128 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 4.953 ; 5.142 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 1.934 ; 1.957 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 4.195 ; 4.113 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 3.407 ; 3.603 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 1.919 ; 1.924 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 2.929 ; 2.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 2.929 ; 2.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 3.148 ; 3.274 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 1.995 ; 2.003 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------+
; Propagation Delay                                               ;
+--------------+--------------+--------+--------+--------+--------+
; Input Port   ; Output Port  ; RR     ; RF     ; FR     ; FF     ;
+--------------+--------------+--------+--------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 9.184  ; 9.704  ; 10.037 ; 10.505 ;
; CONFIG[1]    ; RAM_DATA[12] ; 5.407  ; 5.628  ; 6.426  ; 6.318  ;
; CONFIG[1]    ; RAM_DATA[13] ; 5.287  ; 5.456  ; 6.239  ; 6.197  ;
; CONFIG[1]    ; RAM_DATA[14] ; 5.118  ; 5.158  ; 5.990  ; 5.984  ;
; CONFIG[1]    ; RAM_DATA[15] ; 5.181  ; 5.870  ; 6.646  ; 6.039  ;
; CONFIG[2]    ; RAM_DATA[7]  ; 9.027  ; 9.548  ; 9.859  ; 10.329 ;
; CONFIG[2]    ; RAM_DATA[12] ; 5.256  ; 5.477  ; 6.274  ; 6.166  ;
; CONFIG[2]    ; RAM_DATA[13] ; 5.136  ; 5.305  ; 6.087  ; 6.045  ;
; CONFIG[2]    ; RAM_DATA[14] ; 4.967  ; 5.007  ; 5.838  ; 5.832  ;
; CONFIG[2]    ; RAM_DATA[15] ; 5.030  ; 5.719  ; 6.494  ; 5.887  ;
; CONFIG[3]    ; ADR[16]      ; 9.726  ; 9.902  ; 10.761 ; 10.937 ;
; CONFIG[3]    ; ADR[17]      ; 9.643  ; 9.633  ; 10.678 ; 10.736 ;
; CONFIG[3]    ; ADR[18]      ; 10.344 ; 10.499 ; 11.447 ; 11.534 ;
; CONFIG[3]    ; ADR[22]      ; 5.205  ;        ;        ; 6.173  ;
; CONFIG[3]    ; FLASH_CEn    ; 10.584 ; 10.568 ; 11.619 ; 11.671 ;
; CONFIG[3]    ; FLASH_OEn    ; 12.090 ; 11.839 ; 13.125 ; 12.942 ;
; CONFIG[3]    ; RAM_BA[1]    ; 8.735  ; 8.944  ; 9.814  ; 9.980  ;
; CONFIG[3]    ; RAM_CASn     ; 10.308 ; 10.669 ; 11.387 ; 11.705 ;
; CONFIG[3]    ; RAM_DATA[0]  ; 12.254 ; 12.388 ; 13.289 ; 13.491 ;
; CONFIG[3]    ; RAM_DATA[1]  ; 12.417 ; 12.603 ; 13.452 ; 13.638 ;
; CONFIG[3]    ; RAM_DATA[2]  ; 12.315 ; 12.678 ; 13.350 ; 13.713 ;
; CONFIG[3]    ; RAM_DATA[3]  ; 12.575 ; 12.890 ; 13.610 ; 13.952 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 12.568 ; 12.756 ; 13.603 ; 13.791 ;
; CONFIG[3]    ; RAM_DATA[5]  ; 13.446 ; 13.268 ; 14.481 ; 14.369 ;
; CONFIG[3]    ; RAM_DATA[6]  ; 12.220 ; 12.442 ; 13.255 ; 13.477 ;
; CONFIG[3]    ; RAM_DATA[7]  ; 12.077 ; 12.433 ; 13.112 ; 13.468 ;
; CONFIG[3]    ; RAM_DATA[8]  ; 12.729 ; 13.020 ; 13.764 ; 14.123 ;
; CONFIG[3]    ; RAM_DATA[9]  ; 12.473 ; 12.619 ; 13.508 ; 13.659 ;
; CONFIG[3]    ; RAM_DATA[10] ; 11.811 ; 11.856 ; 12.846 ; 12.891 ;
; CONFIG[3]    ; RAM_DATA[11] ; 12.137 ; 12.376 ; 13.172 ; 13.411 ;
; CONFIG[3]    ; RAM_DATA[12] ; 12.388 ; 12.718 ; 13.423 ; 13.753 ;
; CONFIG[3]    ; RAM_DATA[13] ; 12.023 ; 12.150 ; 13.101 ; 13.208 ;
; CONFIG[3]    ; RAM_DATA[14] ; 12.915 ; 13.070 ; 13.985 ; 14.140 ;
; CONFIG[3]    ; RAM_DATA[15] ; 12.737 ; 12.845 ; 13.801 ; 13.909 ;
; CONFIG[4]    ; ADR[16]      ; 9.585  ; 9.761  ; 10.553 ; 10.729 ;
; CONFIG[4]    ; ADR[17]      ; 9.502  ; 9.492  ; 10.470 ; 10.528 ;
; CONFIG[4]    ; ADR[18]      ; 10.203 ; 10.358 ; 11.239 ; 11.326 ;
; CONFIG[4]    ; ADR[21]      ; 5.486  ;        ;        ; 6.467  ;
; CONFIG[4]    ; FLASH_CEn    ; 10.443 ; 10.427 ; 11.411 ; 11.463 ;
; CONFIG[4]    ; FLASH_OEn    ; 11.949 ; 11.698 ; 12.917 ; 12.734 ;
; CONFIG[4]    ; RAM_BA[1]    ; 8.594  ; 8.803  ; 9.606  ; 9.772  ;
; CONFIG[4]    ; RAM_CASn     ; 10.167 ; 10.528 ; 11.179 ; 11.497 ;
; CONFIG[4]    ; RAM_DATA[0]  ; 12.113 ; 12.247 ; 13.081 ; 13.283 ;
; CONFIG[4]    ; RAM_DATA[1]  ; 12.276 ; 12.462 ; 13.244 ; 13.430 ;
; CONFIG[4]    ; RAM_DATA[2]  ; 12.174 ; 12.537 ; 13.142 ; 13.505 ;
; CONFIG[4]    ; RAM_DATA[3]  ; 12.434 ; 12.749 ; 13.402 ; 13.744 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 12.427 ; 12.615 ; 13.395 ; 13.583 ;
; CONFIG[4]    ; RAM_DATA[5]  ; 13.305 ; 13.127 ; 14.273 ; 14.161 ;
; CONFIG[4]    ; RAM_DATA[6]  ; 12.079 ; 12.301 ; 13.047 ; 13.269 ;
; CONFIG[4]    ; RAM_DATA[7]  ; 11.936 ; 12.292 ; 12.904 ; 13.260 ;
; CONFIG[4]    ; RAM_DATA[8]  ; 12.588 ; 12.879 ; 13.556 ; 13.915 ;
; CONFIG[4]    ; RAM_DATA[9]  ; 12.332 ; 12.478 ; 13.300 ; 13.451 ;
; CONFIG[4]    ; RAM_DATA[10] ; 11.670 ; 11.715 ; 12.638 ; 12.683 ;
; CONFIG[4]    ; RAM_DATA[11] ; 11.996 ; 12.235 ; 12.964 ; 13.203 ;
; CONFIG[4]    ; RAM_DATA[12] ; 12.247 ; 12.577 ; 13.215 ; 13.545 ;
; CONFIG[4]    ; RAM_DATA[13] ; 11.882 ; 12.009 ; 12.893 ; 13.000 ;
; CONFIG[4]    ; RAM_DATA[14] ; 12.774 ; 12.929 ; 13.777 ; 13.932 ;
; CONFIG[4]    ; RAM_DATA[15] ; 12.596 ; 12.704 ; 13.593 ; 13.701 ;
; CONFIG[5]    ; ADR[16]      ; 9.667  ; 9.843  ; 10.679 ; 10.855 ;
; CONFIG[5]    ; ADR[17]      ; 9.584  ; 9.574  ; 10.596 ; 10.654 ;
; CONFIG[5]    ; ADR[18]      ; 10.285 ; 10.440 ; 11.365 ; 11.452 ;
; CONFIG[5]    ; ADR[20]      ; 4.726  ;        ;        ; 5.593  ;
; CONFIG[5]    ; FLASH_CEn    ; 10.525 ; 10.509 ; 11.537 ; 11.589 ;
; CONFIG[5]    ; FLASH_OEn    ; 12.031 ; 11.780 ; 13.043 ; 12.860 ;
; CONFIG[5]    ; RAM_BA[1]    ; 8.676  ; 8.885  ; 9.732  ; 9.898  ;
; CONFIG[5]    ; RAM_CASn     ; 10.249 ; 10.610 ; 11.305 ; 11.623 ;
; CONFIG[5]    ; RAM_DATA[0]  ; 12.195 ; 12.329 ; 13.207 ; 13.409 ;
; CONFIG[5]    ; RAM_DATA[1]  ; 12.358 ; 12.544 ; 13.370 ; 13.556 ;
; CONFIG[5]    ; RAM_DATA[2]  ; 12.256 ; 12.619 ; 13.268 ; 13.631 ;
; CONFIG[5]    ; RAM_DATA[3]  ; 12.516 ; 12.831 ; 13.528 ; 13.870 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 12.509 ; 12.697 ; 13.521 ; 13.709 ;
; CONFIG[5]    ; RAM_DATA[5]  ; 13.387 ; 13.209 ; 14.399 ; 14.287 ;
; CONFIG[5]    ; RAM_DATA[6]  ; 12.161 ; 12.383 ; 13.173 ; 13.395 ;
; CONFIG[5]    ; RAM_DATA[7]  ; 12.018 ; 12.374 ; 13.030 ; 13.386 ;
; CONFIG[5]    ; RAM_DATA[8]  ; 12.670 ; 12.961 ; 13.682 ; 14.041 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 12.414 ; 12.560 ; 13.426 ; 13.577 ;
; CONFIG[5]    ; RAM_DATA[10] ; 11.752 ; 11.797 ; 12.764 ; 12.809 ;
; CONFIG[5]    ; RAM_DATA[11] ; 12.078 ; 12.317 ; 13.090 ; 13.329 ;
; CONFIG[5]    ; RAM_DATA[12] ; 12.329 ; 12.659 ; 13.341 ; 13.671 ;
; CONFIG[5]    ; RAM_DATA[13] ; 11.964 ; 12.091 ; 13.019 ; 13.126 ;
; CONFIG[5]    ; RAM_DATA[14] ; 12.856 ; 13.011 ; 13.903 ; 14.058 ;
; CONFIG[5]    ; RAM_DATA[15] ; 12.678 ; 12.786 ; 13.719 ; 13.827 ;
; CONFIG[6]    ; ADR[19]      ; 4.918  ;        ;        ; 5.787  ;
; DATA[0]      ; RAM_DATA[0]  ; 6.698  ;        ;        ; 7.816  ;
; DATA[1]      ; RAM_DATA[1]  ; 6.888  ;        ;        ; 8.040  ;
; DATA[2]      ; RAM_DATA[2]  ; 7.324  ;        ;        ; 8.478  ;
; DATA[3]      ; RAM_DATA[3]  ; 7.978  ;        ;        ; 9.239  ;
; DATA[4]      ; RAM_DATA[4]  ; 7.216  ;        ;        ; 8.370  ;
; DATA[5]      ; RAM_DATA[5]  ; 7.969  ;        ;        ; 8.776  ;
; DATA[6]      ; RAM_DATA[6]  ; 7.341  ;        ;        ; 8.566  ;
; DATA[7]      ; RAM_DATA[7]  ; 7.456  ;        ;        ; 8.681  ;
; DATA[8]      ; RAM_DATA[8]  ; 7.570  ;        ;        ; 8.762  ;
; DATA[9]      ; RAM_DATA[9]  ; 8.244  ;        ;        ; 9.534  ;
; DATA[10]     ; RAM_DATA[10] ; 7.106  ;        ;        ; 8.234  ;
; DATA[11]     ; RAM_DATA[11] ; 7.592  ;        ;        ; 8.724  ;
; DATA[12]     ; RAM_DATA[12] ; 8.056  ;        ;        ; 9.307  ;
; DATA[13]     ; RAM_DATA[13] ; 6.196  ;        ;        ; 7.255  ;
; DATA[14]     ; RAM_DATA[14] ; 6.447  ;        ;        ; 7.482  ;
; DATA[15]     ; RAM_DATA[15] ; 6.066  ;        ;        ; 7.122  ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 7.725  ;        ;        ; 8.929  ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 7.826  ;        ;        ; 9.030  ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 8.641  ;        ;        ; 9.893  ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 8.719  ;        ;        ; 9.994  ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 7.782  ;        ;        ; 8.946  ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 8.700  ;        ;        ; 9.549  ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 7.684  ;        ;        ; 8.864  ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 7.681  ;        ;        ; 8.879  ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 8.275  ;        ;        ; 9.518  ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 9.074  ;        ;        ; 10.440 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 7.263  ;        ;        ; 8.349  ;
; RAM_DATA[11] ; RAM_DATA[11] ; 7.374  ;        ;        ; 8.480  ;
; RAM_DATA[12] ; RAM_DATA[12] ; 6.925  ;        ;        ; 7.990  ;
; RAM_DATA[13] ; RAM_DATA[13] ; 6.367  ; 6.481  ; 7.209  ; 7.316  ;
; RAM_DATA[14] ; RAM_DATA[14] ; 7.521  ; 7.676  ; 8.377  ; 8.532  ;
; RAM_DATA[15] ; RAM_DATA[15] ; 8.843  ; 8.951  ; 9.944  ; 10.052 ;
; RESET_COREn  ; RAM_CKE      ; 2.479  ;        ;        ; 2.905  ;
; RESETn       ; KEYB_TxD     ; 5.666  ; 5.647  ; 6.615  ; 6.615  ;
+--------------+--------------+--------+--------+--------+--------+


+---------------------------------------------------------------+
; Minimum Propagation Delay                                     ;
+--------------+--------------+-------+-------+--------+--------+
; Input Port   ; Output Port  ; RR    ; RF    ; FR     ; FF     ;
+--------------+--------------+-------+-------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 8.882 ; 9.375 ; 9.709  ; 10.173 ;
; CONFIG[1]    ; RAM_DATA[12] ; 5.255 ; 5.451 ; 6.232  ; 6.150  ;
; CONFIG[1]    ; RAM_DATA[13] ; 5.110 ; 5.268 ; 6.046  ; 6.002  ;
; CONFIG[1]    ; RAM_DATA[14] ; 4.976 ; 5.014 ; 5.836  ; 5.830  ;
; CONFIG[1]    ; RAM_DATA[15] ; 5.037 ; 5.649 ; 6.423  ; 5.882  ;
; CONFIG[2]    ; RAM_DATA[7]  ; 8.728 ; 9.225 ; 9.539  ; 10.003 ;
; CONFIG[2]    ; RAM_DATA[12] ; 5.111 ; 5.307 ; 6.088  ; 6.006  ;
; CONFIG[2]    ; RAM_DATA[13] ; 4.966 ; 5.124 ; 5.902  ; 5.858  ;
; CONFIG[2]    ; RAM_DATA[14] ; 4.832 ; 4.870 ; 5.692  ; 5.686  ;
; CONFIG[2]    ; RAM_DATA[15] ; 4.893 ; 5.505 ; 6.279  ; 5.738  ;
; CONFIG[3]    ; ADR[16]      ; 7.706 ; 7.843 ; 8.758  ; 8.919  ;
; CONFIG[3]    ; ADR[17]      ; 7.405 ; 7.521 ; 8.355  ; 8.619  ;
; CONFIG[3]    ; ADR[18]      ; 6.095 ; 9.180 ; 10.153 ; 7.127  ;
; CONFIG[3]    ; ADR[22]      ; 5.060 ;       ;        ; 6.011  ;
; CONFIG[3]    ; FLASH_CEn    ; 7.426 ; 8.226 ; 9.026  ; 8.410  ;
; CONFIG[3]    ; FLASH_OEn    ; 8.933 ; 9.498 ; 10.533 ; 9.682  ;
; CONFIG[3]    ; RAM_BA[1]    ; 7.441 ; 6.936 ; 7.819  ; 8.650  ;
; CONFIG[3]    ; RAM_CASn     ; 7.997 ; 8.108 ; 9.099  ; 9.010  ;
; CONFIG[3]    ; RAM_DATA[0]  ; 8.112 ; 8.093 ; 8.809  ; 9.275  ;
; CONFIG[3]    ; RAM_DATA[1]  ; 8.133 ; 8.225 ; 9.007  ; 9.276  ;
; CONFIG[3]    ; RAM_DATA[2]  ; 8.614 ; 8.615 ; 9.304  ; 9.770  ;
; CONFIG[3]    ; RAM_DATA[3]  ; 8.962 ; 8.815 ; 9.449  ; 10.230 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 8.483 ; 8.398 ; 9.118  ; 9.638  ;
; CONFIG[3]    ; RAM_DATA[5]  ; 9.200 ; 8.968 ; 9.962  ; 9.980  ;
; CONFIG[3]    ; RAM_DATA[6]  ; 8.577 ; 8.606 ; 9.276  ; 9.616  ;
; CONFIG[3]    ; RAM_DATA[7]  ; 8.289 ; 8.239 ; 8.982  ; 9.304  ;
; CONFIG[3]    ; RAM_DATA[8]  ; 8.692 ; 8.697 ; 9.377  ; 9.798  ;
; CONFIG[3]    ; RAM_DATA[9]  ; 8.476 ; 8.675 ; 9.432  ; 9.757  ;
; CONFIG[3]    ; RAM_DATA[10] ; 8.023 ; 8.075 ; 8.826  ; 9.131  ;
; CONFIG[3]    ; RAM_DATA[11] ; 8.192 ; 8.089 ; 8.847  ; 9.145  ;
; CONFIG[3]    ; RAM_DATA[12] ; 8.236 ; 8.151 ; 8.866  ; 9.401  ;
; CONFIG[3]    ; RAM_DATA[13] ; 7.308 ; 7.378 ; 8.159  ; 8.170  ;
; CONFIG[3]    ; RAM_DATA[14] ; 8.225 ; 8.343 ; 9.043  ; 9.142  ;
; CONFIG[3]    ; RAM_DATA[15] ; 7.653 ; 7.738 ; 8.496  ; 8.558  ;
; CONFIG[4]    ; ADR[16]      ; 7.578 ; 7.715 ; 8.582  ; 8.743  ;
; CONFIG[4]    ; ADR[17]      ; 7.277 ; 7.393 ; 8.179  ; 8.443  ;
; CONFIG[4]    ; ADR[18]      ; 6.022 ; 9.060 ; 9.978  ; 7.024  ;
; CONFIG[4]    ; ADR[21]      ; 5.321 ;       ;        ; 6.278  ;
; CONFIG[4]    ; FLASH_CEn    ; 7.353 ; 8.153 ; 8.923  ; 8.307  ;
; CONFIG[4]    ; FLASH_OEn    ; 8.860 ; 9.425 ; 10.430 ; 9.579  ;
; CONFIG[4]    ; RAM_BA[1]    ; 7.321 ; 6.808 ; 7.643  ; 8.475  ;
; CONFIG[4]    ; RAM_CASn     ; 7.869 ; 7.986 ; 8.923  ; 8.834  ;
; CONFIG[4]    ; RAM_DATA[0]  ; 7.984 ; 7.965 ; 8.633  ; 9.099  ;
; CONFIG[4]    ; RAM_DATA[1]  ; 8.060 ; 8.097 ; 8.831  ; 9.173  ;
; CONFIG[4]    ; RAM_DATA[2]  ; 8.541 ; 8.487 ; 9.128  ; 9.617  ;
; CONFIG[4]    ; RAM_DATA[3]  ; 8.889 ; 8.687 ; 9.273  ; 10.084 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 8.410 ; 8.270 ; 8.942  ; 9.503  ;
; CONFIG[4]    ; RAM_DATA[5]  ; 9.072 ; 8.840 ; 9.786  ; 9.804  ;
; CONFIG[4]    ; RAM_DATA[6]  ; 8.449 ; 8.478 ; 9.100  ; 9.440  ;
; CONFIG[4]    ; RAM_DATA[7]  ; 8.161 ; 8.111 ; 8.806  ; 9.128  ;
; CONFIG[4]    ; RAM_DATA[8]  ; 8.619 ; 8.569 ; 9.201  ; 9.695  ;
; CONFIG[4]    ; RAM_DATA[9]  ; 8.403 ; 8.547 ; 9.256  ; 9.654  ;
; CONFIG[4]    ; RAM_DATA[10] ; 7.895 ; 7.947 ; 8.650  ; 9.018  ;
; CONFIG[4]    ; RAM_DATA[11] ; 8.064 ; 7.961 ; 8.671  ; 8.969  ;
; CONFIG[4]    ; RAM_DATA[12] ; 8.163 ; 8.023 ; 8.690  ; 9.298  ;
; CONFIG[4]    ; RAM_DATA[13] ; 7.235 ; 7.305 ; 8.056  ; 8.067  ;
; CONFIG[4]    ; RAM_DATA[14] ; 8.152 ; 8.270 ; 8.940  ; 9.039  ;
; CONFIG[4]    ; RAM_DATA[15] ; 7.580 ; 7.665 ; 8.393  ; 8.455  ;
; CONFIG[5]    ; ADR[16]      ; 7.656 ; 7.793 ; 8.704  ; 8.865  ;
; CONFIG[5]    ; ADR[17]      ; 7.355 ; 7.471 ; 8.301  ; 8.565  ;
; CONFIG[5]    ; ADR[18]      ; 8.212 ; 9.159 ; 10.120 ; 9.221  ;
; CONFIG[5]    ; ADR[20]      ; 4.593 ;       ;        ; 5.439  ;
; CONFIG[5]    ; FLASH_CEn    ; 8.125 ; 8.478 ; 9.510  ; 9.058  ;
; CONFIG[5]    ; FLASH_OEn    ; 9.632 ; 9.750 ; 11.017 ; 10.330 ;
; CONFIG[5]    ; RAM_BA[1]    ; 7.420 ; 6.886 ; 7.765  ; 8.617  ;
; CONFIG[5]    ; RAM_CASn     ; 7.947 ; 8.087 ; 9.067  ; 8.956  ;
; CONFIG[5]    ; RAM_DATA[0]  ; 8.062 ; 8.043 ; 8.755  ; 9.221  ;
; CONFIG[5]    ; RAM_DATA[1]  ; 8.564 ; 8.175 ; 8.953  ; 9.586  ;
; CONFIG[5]    ; RAM_DATA[2]  ; 8.627 ; 8.565 ; 9.250  ; 9.739  ;
; CONFIG[5]    ; RAM_DATA[3]  ; 9.118 ; 8.765 ; 9.395  ; 10.206 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 8.557 ; 8.348 ; 9.064  ; 9.625  ;
; CONFIG[5]    ; RAM_DATA[5]  ; 9.150 ; 8.918 ; 9.908  ; 9.926  ;
; CONFIG[5]    ; RAM_DATA[6]  ; 8.527 ; 8.556 ; 9.222  ; 9.562  ;
; CONFIG[5]    ; RAM_DATA[7]  ; 8.239 ; 8.189 ; 8.928  ; 9.250  ;
; CONFIG[5]    ; RAM_DATA[8]  ; 8.946 ; 8.647 ; 9.323  ; 10.142 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 8.598 ; 8.625 ; 9.378  ; 9.856  ;
; CONFIG[5]    ; RAM_DATA[10] ; 7.973 ; 8.025 ; 8.772  ; 9.140  ;
; CONFIG[5]    ; RAM_DATA[11] ; 8.142 ; 8.039 ; 8.793  ; 9.091  ;
; CONFIG[5]    ; RAM_DATA[12] ; 8.407 ; 8.101 ; 8.812  ; 9.497  ;
; CONFIG[5]    ; RAM_DATA[13] ; 7.812 ; 7.831 ; 8.617  ; 8.628  ;
; CONFIG[5]    ; RAM_DATA[14] ; 8.561 ; 8.685 ; 9.447  ; 9.571  ;
; CONFIG[5]    ; RAM_DATA[15] ; 8.157 ; 8.242 ; 8.954  ; 9.016  ;
; CONFIG[6]    ; ADR[19]      ; 4.777 ;       ;        ; 5.625  ;
; DATA[0]      ; RAM_DATA[0]  ; 5.574 ;       ;        ; 6.597  ;
; DATA[1]      ; RAM_DATA[1]  ; 5.467 ;       ;        ; 6.464  ;
; DATA[2]      ; RAM_DATA[2]  ; 6.014 ;       ;        ; 7.046  ;
; DATA[3]      ; RAM_DATA[3]  ; 6.250 ;       ;        ; 7.337  ;
; DATA[4]      ; RAM_DATA[4]  ; 5.864 ;       ;        ; 6.838  ;
; DATA[5]      ; RAM_DATA[5]  ; 6.741 ;       ;        ; 7.489  ;
; DATA[6]      ; RAM_DATA[6]  ; 5.995 ;       ;        ; 7.076  ;
; DATA[7]      ; RAM_DATA[7]  ; 5.628 ;       ;        ; 6.663  ;
; DATA[8]      ; RAM_DATA[8]  ; 5.869 ;       ;        ; 6.882  ;
; DATA[9]      ; RAM_DATA[9]  ; 6.168 ;       ;        ; 7.227  ;
; DATA[10]     ; RAM_DATA[10] ; 5.571 ;       ;        ; 6.554  ;
; DATA[11]     ; RAM_DATA[11] ; 5.618 ;       ;        ; 6.550  ;
; DATA[12]     ; RAM_DATA[12] ; 6.950 ;       ;        ; 8.113  ;
; DATA[13]     ; RAM_DATA[13] ; 5.679 ;       ;        ; 6.675  ;
; DATA[14]     ; RAM_DATA[14] ; 6.203 ;       ;        ; 7.201  ;
; DATA[15]     ; RAM_DATA[15] ; 5.878 ;       ;        ; 6.902  ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 7.466 ;       ;        ; 8.617  ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 7.561 ;       ;        ; 8.727  ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 8.335 ;       ;        ; 9.540  ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 8.397 ;       ;        ; 9.618  ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 7.524 ;       ;        ; 8.648  ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 8.452 ;       ;        ; 9.274  ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 7.429 ;       ;        ; 8.565  ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 7.428 ;       ;        ; 8.582  ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 7.965 ;       ;        ; 9.149  ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 8.728 ;       ;        ; 10.034 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 7.022 ;       ;        ; 8.072  ;
; RAM_DATA[11] ; RAM_DATA[11] ; 7.126 ;       ;        ; 8.182  ;
; RAM_DATA[12] ; RAM_DATA[12] ; 6.678 ;       ;        ; 7.709  ;
; RAM_DATA[13] ; RAM_DATA[13] ; 6.174 ; 6.286 ; 7.006  ; 7.111  ;
; RAM_DATA[14] ; RAM_DATA[14] ; 7.207 ; 7.331 ; 8.057  ; 8.181  ;
; RAM_DATA[15] ; RAM_DATA[15] ; 8.418 ; 8.518 ; 9.483  ; 9.583  ;
; RESET_COREn  ; RAM_CKE      ; 2.449 ;       ;        ; 2.878  ;
; RESETn       ; KEYB_TxD     ; 4.667 ; 4.667 ; 5.735  ; 5.603  ;
+--------------+--------------+-------+-------+--------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 5.480  ; 5.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 5.480  ; 5.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 5.738  ; 5.719  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 5.738  ; 5.719  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 5.738  ; 5.719  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 5.829  ; 5.810  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 5.829  ; 5.810  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 5.934  ; 5.915  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 5.934  ; 5.915  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 5.906  ; 5.887  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 5.906  ; 5.887  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 5.916  ; 5.897  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 5.926  ; 5.907  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 5.926  ; 5.907  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 5.926  ; 5.907  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 5.931  ; 5.912  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 5.941  ; 5.922  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 3.876  ; 3.857  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 3.836  ; 3.809  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 5.666  ; 5.647  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 5.157  ; 5.130  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 5.153  ; 5.126  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 9.659  ; 9.632  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 9.804  ; 9.777  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 9.804  ; 9.777  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 9.659  ; 9.632  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 9.822  ; 9.795  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 9.822  ; 9.795  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 9.822  ; 9.795  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 9.835  ; 9.808  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 9.825  ; 9.798  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 9.830  ; 9.803  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.830  ; 9.803  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 9.991  ; 9.964  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.992  ; 9.965  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.004 ; 9.977  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.004 ; 9.977  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.010 ; 9.983  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.168 ; 10.141 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 5.196  ; 5.177  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 5.196  ; 5.177  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.987  ; 4.960  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 4.035  ; 4.008  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 8.366  ; 8.339  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 8.511  ; 8.484  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 8.511  ; 8.484  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.366  ; 8.339  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.529  ; 8.502  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 8.529  ; 8.502  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 8.529  ; 8.502  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 8.542  ; 8.515  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 8.532  ; 8.505  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 8.537  ; 8.510  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 8.537  ; 8.510  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 8.698  ; 8.671  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 8.699  ; 8.672  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 8.711  ; 8.684  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 8.711  ; 8.684  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 8.717  ; 8.690  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 8.875  ; 8.848  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 6.494  ; 6.467  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.639  ; 6.612  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 6.639  ; 6.612  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 6.494  ; 6.467  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.657  ; 6.630  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.657  ; 6.630  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.657  ; 6.630  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.670  ; 6.643  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.660  ; 6.633  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.665  ; 6.638  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.665  ; 6.638  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 6.826  ; 6.799  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 6.827  ; 6.800  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 6.839  ; 6.812  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 6.839  ; 6.812  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 6.845  ; 6.818  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.003  ; 6.976  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 12.436 ; 12.409 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.581 ; 12.554 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 12.581 ; 12.554 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.436 ; 12.409 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.599 ; 12.572 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.599 ; 12.572 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.599 ; 12.572 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.612 ; 12.585 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.602 ; 12.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.607 ; 12.580 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 12.607 ; 12.580 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 12.768 ; 12.741 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 12.769 ; 12.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 12.781 ; 12.754 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.781 ; 12.754 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.787 ; 12.760 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 12.945 ; 12.918 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 6.013  ; 5.986  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 6.009  ; 5.982  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 6.052  ; 6.033  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 6.052  ; 6.033  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 5.843  ; 5.816  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 3.225 ; 3.225 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 3.225 ; 3.225 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 3.473 ; 3.473 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 3.473 ; 3.473 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 3.473 ; 3.473 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 3.560 ; 3.560 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 3.560 ; 3.560 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 3.662 ; 3.662 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 3.662 ; 3.662 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 3.635 ; 3.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 3.635 ; 3.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 3.645 ; 3.645 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 3.654 ; 3.654 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 3.654 ; 3.654 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 3.654 ; 3.654 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 3.659 ; 3.659 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 3.669 ; 3.669 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 2.452 ; 2.452 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 2.638 ; 2.638 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 3.613 ; 3.613 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 3.353 ; 3.353 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 3.349 ; 3.349 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.607 ; 3.607 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 3.746 ; 3.746 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 3.746 ; 3.746 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 3.607 ; 3.607 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 3.763 ; 3.763 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 3.763 ; 3.763 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 3.763 ; 3.763 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 3.776 ; 3.776 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 3.766 ; 3.766 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 3.771 ; 3.771 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 3.771 ; 3.771 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 3.925 ; 3.925 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 3.926 ; 3.926 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 3.938 ; 3.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.938 ; 3.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 3.943 ; 3.943 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.095 ; 4.095 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 3.416 ; 3.416 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 3.416 ; 3.416 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 3.190 ; 3.190 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 2.828 ; 2.828 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.737 ; 3.737 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 3.876 ; 3.876 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 3.876 ; 3.876 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 3.737 ; 3.737 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 3.893 ; 3.893 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 3.893 ; 3.893 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 3.893 ; 3.893 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 3.906 ; 3.906 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 3.896 ; 3.896 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 3.901 ; 3.901 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 3.901 ; 3.901 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.055 ; 4.055 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.056 ; 4.056 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.068 ; 4.068 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.068 ; 4.068 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.073 ; 4.073 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.225 ; 4.225 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 2.823 ; 2.823 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 2.962 ; 2.962 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 2.962 ; 2.962 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 2.823 ; 2.823 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 2.979 ; 2.979 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 2.979 ; 2.979 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 2.979 ; 2.979 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 2.992 ; 2.992 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 2.982 ; 2.982 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 2.987 ; 2.987 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 2.987 ; 2.987 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 3.141 ; 3.141 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 3.142 ; 3.142 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 3.154 ; 3.154 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.154 ; 3.154 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 3.159 ; 3.159 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 3.311 ; 3.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.895 ; 3.895 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 4.034 ; 4.034 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.034 ; 4.034 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 3.895 ; 3.895 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 4.051 ; 4.051 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.051 ; 4.051 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 4.051 ; 4.051 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 4.064 ; 4.064 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 4.054 ; 4.054 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.059 ; 4.059 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.059 ; 4.059 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.213 ; 4.213 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.214 ; 4.214 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.226 ; 4.226 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.226 ; 4.226 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.231 ; 4.231 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.383 ; 4.383 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 4.727 ; 4.727 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 4.723 ; 4.723 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 4.790 ; 4.790 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 4.790 ; 4.790 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.564 ; 4.564 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 5.660     ; 5.660     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 5.660     ; 5.660     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 5.953     ; 5.953     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 5.953     ; 5.953     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 5.953     ; 5.953     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 6.053     ; 6.053     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 6.053     ; 6.053     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 6.176     ; 6.176     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 6.176     ; 6.176     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 6.143     ; 6.143     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 6.143     ; 6.143     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 6.153     ; 6.153     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 6.161     ; 6.161     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 6.161     ; 6.161     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 6.161     ; 6.161     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 6.168     ; 6.168     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 6.178     ; 6.178     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 4.079     ; 4.079     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 4.014     ; 4.014     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 5.578     ; 5.578     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 5.374     ; 5.374     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 5.368     ; 5.368     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 9.850     ; 9.850     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 10.010    ; 10.010    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 10.010    ; 10.010    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 9.850     ; 9.850     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 10.030    ; 10.030    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 10.030    ; 10.030    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 10.030    ; 10.030    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 10.037    ; 10.037    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 10.027    ; 10.027    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 10.045    ; 10.045    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 10.045    ; 10.045    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 10.219    ; 10.219    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 10.218    ; 10.218    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.224    ; 10.224    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.224    ; 10.224    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.243    ; 10.243    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.409    ; 10.409    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 5.421     ; 5.421     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 5.421     ; 5.421     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 5.177     ; 5.177     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 4.226     ; 4.226     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.298     ; 7.298     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.458     ; 7.458     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.458     ; 7.458     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 7.298     ; 7.298     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 7.478     ; 7.478     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 7.478     ; 7.478     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.478     ; 7.478     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 7.485     ; 7.485     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 7.475     ; 7.475     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 7.493     ; 7.493     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.493     ; 7.493     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 7.667     ; 7.667     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 7.666     ; 7.666     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 7.672     ; 7.672     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 7.672     ; 7.672     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 7.691     ; 7.691     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.857     ; 7.857     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 6.691     ; 6.691     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 6.851     ; 6.851     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 6.851     ; 6.851     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 6.691     ; 6.691     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 6.871     ; 6.871     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.871     ; 6.871     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.871     ; 6.871     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 6.878     ; 6.878     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 6.868     ; 6.868     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.886     ; 6.886     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 6.886     ; 6.886     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 7.060     ; 7.060     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 7.059     ; 7.059     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 7.065     ; 7.065     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 7.065     ; 7.065     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 7.084     ; 7.084     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.250     ; 7.250     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 12.532    ; 12.532    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 12.692    ; 12.692    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 12.692    ; 12.692    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 12.532    ; 12.532    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 12.712    ; 12.712    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.712    ; 12.712    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 12.712    ; 12.712    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.719    ; 12.719    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.709    ; 12.709    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.727    ; 12.727    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 12.727    ; 12.727    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 12.901    ; 12.901    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 12.900    ; 12.900    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 12.906    ; 12.906    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.906    ; 12.906    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.925    ; 12.925    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 13.091    ; 13.091    ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 6.498     ; 6.498     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 6.492     ; 6.492     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 6.545     ; 6.545     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 6.545     ; 6.545     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 6.301     ; 6.301     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+
; DATA[*]       ; CLK_PLL1   ; 3.459     ; 3.591     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 3.459     ; 3.591     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 3.740     ; 3.872     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 3.740     ; 3.872     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 3.740     ; 3.872     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 3.836     ; 3.968     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 3.836     ; 3.968     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 3.954     ; 4.086     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 3.954     ; 4.086     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 3.923     ; 4.055     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 3.923     ; 4.055     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 3.933     ; 4.065     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 3.941     ; 4.073     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 3.941     ; 4.073     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 3.941     ; 4.073     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 3.947     ; 4.079     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 3.957     ; 4.089     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 2.539     ; 2.671     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 2.809     ; 2.926     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 3.552     ; 3.684     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 3.635     ; 3.752     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 3.629     ; 3.746     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.678     ; 3.795     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 3.831     ; 3.948     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 3.831     ; 3.948     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 3.678     ; 3.795     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 3.850     ; 3.967     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 3.850     ; 3.967     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 3.850     ; 3.967     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 3.856     ; 3.973     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 3.846     ; 3.963     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 3.864     ; 3.981     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 3.864     ; 3.981     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.031     ; 4.148     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.029     ; 4.146     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.036     ; 4.153     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.036     ; 4.153     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.054     ; 4.171     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.213     ; 4.330     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 3.706     ; 3.838     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[3]     ; CLK_PLL1   ; 3.706     ; 3.838     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 3.445     ; 3.562     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 3.012     ; 3.129     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.811     ; 3.928     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 3.964     ; 4.081     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 3.964     ; 4.081     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 3.811     ; 3.928     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 3.983     ; 4.100     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 3.983     ; 4.100     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 3.983     ; 4.100     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 3.989     ; 4.106     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 3.979     ; 4.096     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 3.997     ; 4.114     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 3.997     ; 4.114     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.164     ; 4.281     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.162     ; 4.279     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.169     ; 4.286     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.169     ; 4.286     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.187     ; 4.304     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.346     ; 4.463     ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 2.811     ; 2.928     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 2.964     ; 3.081     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 2.964     ; 3.081     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 2.811     ; 2.928     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 2.983     ; 3.100     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 2.983     ; 3.100     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 2.983     ; 3.100     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 2.989     ; 3.106     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 2.979     ; 3.096     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 2.997     ; 3.114     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 2.997     ; 3.114     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 3.164     ; 3.281     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 3.162     ; 3.279     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 3.169     ; 3.286     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.169     ; 3.286     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 3.187     ; 3.304     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 3.346     ; 3.463     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.966     ; 4.083     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 4.119     ; 4.236     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.119     ; 4.236     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 3.966     ; 4.083     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 4.138     ; 4.255     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.138     ; 4.255     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 4.138     ; 4.255     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 4.144     ; 4.261     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 4.134     ; 4.251     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.152     ; 4.269     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.152     ; 4.269     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.319     ; 4.436     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.317     ; 4.434     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.324     ; 4.441     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.324     ; 4.441     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.342     ; 4.459     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.501     ; 4.618     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 5.194     ; 5.311     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 5.188     ; 5.305     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 5.265     ; 5.397     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 5.265     ; 5.397     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 5.004     ; 5.121     ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                                   ;
+---------------------------------------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+
; Clock                                                                                                   ; Setup   ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+
; Worst-case Slack                                                                                        ; -4.791  ; -0.128 ; 21.548   ; 0.720   ; 12.384              ;
;  CLK_PLL1                                                                                               ; 59.852  ; 0.198  ; N/A      ; N/A     ; 30.520              ;
;  CLK_PLL2                                                                                               ; N/A     ; N/A    ; N/A      ; N/A     ; 30.656              ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.245   ; -0.128 ; 21.593   ; 0.720   ; 30.888              ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; -4.791  ; 0.088  ; 21.548   ; 1.791   ; 15.268              ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -0.538  ; 0.179  ; 27.749   ; 32.179  ; 30.806              ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.593   ; 0.179  ; N/A      ; N/A     ; 20.480              ;
;  cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 38.089  ; 0.188  ; N/A      ; N/A     ; 19.218              ;
;  cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 22.763  ; 0.195  ; N/A      ; N/A     ; 12.384              ;
;  cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 60.288  ; 0.180  ; N/A      ; N/A     ; 30.895              ;
; Design-wide TNS                                                                                         ; -11.697 ; -0.128 ; 0.0      ; 0.0     ; 0.0                 ;
;  CLK_PLL1                                                                                               ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  CLK_PLL2                                                                                               ; N/A     ; N/A    ; N/A      ; N/A     ; 0.000               ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 0.000   ; -0.128 ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; -9.171  ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; -2.526  ; 0.000  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
;  cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 0.000   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
+---------------------------------------------------------------------------------------------------------+---------+--------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; -0.100 ; 0.396  ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; 10.240 ; 9.948  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 28.366 ; 27.967 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 19.905 ; 20.273 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 19.546 ; 19.903 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 28.227 ; 27.967 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 28.105 ; 27.660 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 28.366 ; 27.910 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 17.046 ; 16.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 14.594 ; 14.611 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 14.673 ; 14.568 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 15.116 ; 14.793 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 15.301 ; 15.105 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 13.579 ; 13.419 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 13.169 ; 13.101 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 15.102 ; 14.847 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 15.375 ; 15.201 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 14.205 ; 14.237 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 16.550 ; 16.078 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 15.869 ; 15.882 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 16.213 ; 15.927 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 17.046 ; 16.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 14.199 ; 14.212 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 12.154 ; 12.293 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 11.907 ; 12.387 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 6.220  ; 6.520  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; 4.473  ; 4.555  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 7.377  ; 7.857  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; 7.966  ; 8.379  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; 4.686  ; 5.006  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; 5.334  ; 5.653  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 19.162 ; 19.096 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 17.222 ; 16.956 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 16.998 ; 16.559 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 18.545 ; 17.673 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 17.435 ; 16.814 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 15.135 ; 14.671 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 15.187 ; 14.765 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 16.115 ; 15.640 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 16.153 ; 15.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 16.160 ; 15.845 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 18.682 ; 17.896 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 16.677 ; 16.335 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 16.044 ; 15.675 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 14.588 ; 14.598 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 14.933 ; 15.129 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 15.162 ; 15.374 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 19.162 ; 19.096 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; 2.414  ; 2.709  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 6.717  ; 6.988  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; 17.076 ; 16.899 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; 8.312  ; 8.696  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; 8.312  ; 8.696  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; 7.702  ; 8.082  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 6.109  ; 6.425  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; 6.433  ; 6.819  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 8.207  ; 8.492  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 24.334 ; 23.898 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; 16.632 ; 17.000 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; 16.273 ; 16.630 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; 24.195 ; 23.898 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; 24.073 ; 23.591 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; 24.334 ; 23.841 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 12.653 ; 12.523 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 10.728 ; 10.998 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 10.819 ; 10.891 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 11.006 ; 11.104 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 11.807 ; 11.885 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 10.409 ; 10.556 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 9.848  ; 9.970  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 11.586 ; 11.601 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 12.102 ; 12.121 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 10.597 ; 10.836 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 12.653 ; 12.523 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 10.813 ; 10.984 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 11.686 ; 11.553 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 12.184 ; 12.090 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 9.003  ; 9.252  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 8.295  ; 8.386  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 7.434  ; 7.749  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 14.785 ; 14.341 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 13.356 ; 13.343 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.144 ; 12.882 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 14.435 ; 13.984 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 13.941 ; 13.594 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 11.965 ; 11.808 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 11.866 ; 11.634 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 12.599 ; 12.394 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 12.880 ; 12.644 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.552 ; 12.444 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 14.785 ; 14.341 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 11.621 ; 11.437 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 11.517 ; 11.301 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 9.726  ; 9.850  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 9.737  ; 9.933  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 11.300 ; 11.512 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 14.378 ; 14.312 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; 24.985 ; 24.549 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; 17.201 ; 17.569 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; 16.842 ; 17.199 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 24.846 ; 24.549 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 24.724 ; 24.242 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 24.985 ; 24.492 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; 12.695 ; 12.739 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; 11.379 ; 11.583 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; 11.269 ; 11.383 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; 12.248 ; 12.289 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; 12.695 ; 12.739 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; 10.886 ; 10.972 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; 11.021 ; 11.033 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; 12.337 ; 12.244 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; 12.671 ; 12.617 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; 10.781 ; 10.983 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 15.677 ; 15.169 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 14.007 ; 13.928 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 13.594 ; 13.374 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 15.677 ; 15.169 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 14.829 ; 14.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.442 ; 12.224 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.039 ; 12.697 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 13.350 ; 13.037 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 13.449 ; 13.140 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 12.736 ; 12.591 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 9.675  ; 10.016 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 10.546 ; 10.818 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 9.703  ; 10.069 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 10.816 ; 11.155 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 10.738 ; 11.059 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 10.901 ; 11.192 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 10.604 ; 10.945 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; 12.418 ; 12.498 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 14.384 ; 14.184 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; 14.245 ; 14.184 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; 14.123 ; 13.877 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; 14.384 ; 14.127 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; 25.953 ; 25.843 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 25.814 ; 25.843 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 25.692 ; 25.536 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 25.953 ; 25.786 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; 25.740 ; 25.615 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; 18.390 ; 18.758 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; 18.031 ; 18.388 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; 25.601 ; 25.615 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; 25.479 ; 25.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; 25.740 ; 25.558 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; 15.076 ; 14.833 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; 11.870 ; 12.179 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; 12.615 ; 12.674 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; 13.542 ; 13.460 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; 13.026 ; 13.132 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; 11.437 ; 11.572 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; 11.894 ; 12.028 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; 13.172 ; 13.143 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; 13.860 ; 13.882 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; 13.025 ; 13.150 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; 15.076 ; 14.833 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; 13.531 ; 13.582 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; 13.969 ; 13.749 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; 14.282 ; 14.085 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; 11.382 ; 11.516 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; 9.442  ; 9.602  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; 9.621  ; 9.810  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 17.208 ; 16.683 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 14.498 ; 14.524 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 14.940 ; 14.665 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 16.971 ; 16.340 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 15.160 ; 14.841 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 12.993 ; 12.824 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 13.912 ; 13.692 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 14.185 ; 13.936 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 14.638 ; 14.405 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 14.980 ; 14.758 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 17.208 ; 16.651 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 14.339 ; 14.035 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 13.800 ; 13.497 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 11.824 ; 11.845 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 12.116 ; 12.312 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 12.450 ; 12.662 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 16.749 ; 16.683 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; 8.890  ; 9.141  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; 10.858 ; 11.031 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                                         ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; RESET_COREn   ; CLK_PLL1   ; 0.995  ; 0.761  ; Rise       ; CLK_PLL1                                                                                               ;
; BOOT_ACK      ; CLK_PLL1   ; -2.600 ; -3.406 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -2.413 ; -3.203 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -2.567 ; -3.373 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -2.413 ; -3.203 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.969 ; -4.927 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.896 ; -4.824 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.632 ; -5.606 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -2.539 ; -3.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -3.240 ; -4.238 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -3.162 ; -4.134 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -3.449 ; -4.472 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -3.349 ; -4.362 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -2.539 ; -3.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -3.117 ; -4.100 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -3.677 ; -4.735 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -3.078 ; -4.074 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -3.020 ; -3.977 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -3.396 ; -4.396 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -3.344 ; -4.349 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -3.125 ; -4.043 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -4.085 ; -5.173 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -3.566 ; -4.572 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -3.378 ; -4.340 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -3.421 ; -4.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; -2.521 ; -3.369 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_RDY     ; CLK_PLL1   ; -1.473 ; -1.857 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; -2.484 ; -3.323 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; JOY_A2        ; CLK_PLL1   ; -2.777 ; -3.691 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_RxD      ; CLK_PLL1   ; -1.885 ; -2.623 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MOSI          ; CLK_PLL1   ; -2.129 ; -2.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.813 ; -4.769 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -5.132 ; -6.258 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -5.256 ; -6.397 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -5.770 ; -6.966 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -5.496 ; -6.643 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.199 ; -5.220 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.828 ; -5.885 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -5.111 ; -6.224 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.878 ; -5.993 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -5.116 ; -6.244 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -5.956 ; -7.203 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.795 ; -5.867 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.633 ; -5.675 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.813 ; -4.769 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -4.061 ; -4.893 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -4.382 ; -5.232 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -5.961 ; -7.026 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESET_COREn   ; CLK_PLL1   ; -0.835 ; -1.336 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; -2.722 ; -3.621 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_CDn       ; CLK_PLL1   ; -3.013 ; -3.832 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_D[*]      ; CLK_PLL1   ; -2.746 ; -3.644 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[1]     ; CLK_PLL1   ; -2.846 ; -3.752 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  SDC_D[2]     ; CLK_PLL1   ; -2.746 ; -3.644 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; -2.345 ; -3.159 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; SDC_WP        ; CLK_PLL1   ; -2.578 ; -3.443 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; -2.362 ; -3.175 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -3.435 ; -4.363 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[1]    ; CLK_PLL1   ; -6.112 ; -6.939 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[2]    ; CLK_PLL1   ; -5.958 ; -6.769 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.508 ; -4.466 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.435 ; -4.363 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.043 ; -5.054 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; -2.324 ; -3.227 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; -2.954 ; -3.929 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; -2.502 ; -3.389 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; -2.937 ; -3.891 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; -2.324 ; -3.227 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; -2.803 ; -3.698 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; -2.799 ; -3.749 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; -3.105 ; -4.124 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; -2.858 ; -3.844 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; -2.537 ; -3.453 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; -2.782 ; -3.725 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; -2.906 ; -3.866 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; -2.683 ; -3.571 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; -3.811 ; -4.853 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; -2.915 ; -3.883 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; -2.772 ; -3.671 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; -2.768 ; -3.721 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.410 ; -4.242 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -4.840 ; -5.943 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -4.937 ; -6.051 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -5.258 ; -6.385 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -5.157 ; -6.278 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.463 ; -5.508 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.510 ; -5.534 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -4.601 ; -5.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.658 ; -5.763 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -4.633 ; -5.720 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -5.342 ; -6.532 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.357 ; -5.384 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.191 ; -5.203 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.539 ; -4.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -3.410 ; -4.242 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -3.776 ; -4.626 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -5.308 ; -6.373 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; CONFIG[*]     ; CLK_PLL1   ; -2.187 ; -2.971 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[1]    ; CLK_PLL1   ; -2.356 ; -3.131 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[2]    ; CLK_PLL1   ; -2.187 ; -2.971 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.387 ; -4.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.314 ; -4.239 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.017 ; -4.974 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DATA[*]       ; CLK_PLL1   ; -2.246 ; -3.111 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[0]      ; CLK_PLL1   ; -2.544 ; -3.464 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[1]      ; CLK_PLL1   ; -2.463 ; -3.345 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[2]      ; CLK_PLL1   ; -2.246 ; -3.111 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[3]      ; CLK_PLL1   ; -2.482 ; -3.375 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[4]      ; CLK_PLL1   ; -2.562 ; -3.420 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[5]      ; CLK_PLL1   ; -2.523 ; -3.437 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[6]      ; CLK_PLL1   ; -2.719 ; -3.692 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[7]      ; CLK_PLL1   ; -2.682 ; -3.605 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  DATA[8]      ; CLK_PLL1   ; -2.797 ; -3.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -1.752 ; -2.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -1.752 ; -2.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -2.035 ; -2.774 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -1.899 ; -2.634 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -2.058 ; -2.809 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -2.031 ; -2.785 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -2.034 ; -2.782 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -1.987 ; -2.723 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -2.004 ; -2.764 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -2.134 ; -2.915 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -2.030 ; -2.805 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -2.032 ; -2.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -2.017 ; -2.773 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -2.042 ; -2.797 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -2.026 ; -2.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -2.073 ; -2.862 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -2.130 ; -2.909 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; SDC_CDn       ; CLK_PLL1   ; -2.657 ; -3.487 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -3.959 ; -4.845 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[3]    ; CLK_PLL1   ; -4.087 ; -5.021 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.959 ; -4.845 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.037 ; -4.967 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CONFIG[*]     ; CLK_PLL1   ; -4.821 ; -5.837 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -4.894 ; -5.940 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -4.821 ; -5.837 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -5.593 ; -6.588 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; CONFIG[*]     ; CLK_PLL1   ; -3.701 ; -4.668 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[1]    ; CLK_PLL1   ; -6.230 ; -7.057 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[2]    ; CLK_PLL1   ; -6.076 ; -6.887 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[3]    ; CLK_PLL1   ; -3.774 ; -4.771 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[4]    ; CLK_PLL1   ; -3.701 ; -4.668 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  CONFIG[5]    ; CLK_PLL1   ; -4.473 ; -5.419 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; DATA[*]       ; CLK_PLL1   ; -2.569 ; -3.485 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[0]      ; CLK_PLL1   ; -3.096 ; -4.103 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[1]      ; CLK_PLL1   ; -3.260 ; -4.260 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[2]      ; CLK_PLL1   ; -2.570 ; -3.487 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[3]      ; CLK_PLL1   ; -2.569 ; -3.485 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[4]      ; CLK_PLL1   ; -2.843 ; -3.758 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[5]      ; CLK_PLL1   ; -2.937 ; -3.897 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[6]      ; CLK_PLL1   ; -3.133 ; -4.146 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[7]      ; CLK_PLL1   ; -2.674 ; -3.589 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[8]      ; CLK_PLL1   ; -3.218 ; -4.215 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[9]      ; CLK_PLL1   ; -3.452 ; -4.463 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[10]     ; CLK_PLL1   ; -3.441 ; -4.438 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[11]     ; CLK_PLL1   ; -3.350 ; -4.310 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[12]     ; CLK_PLL1   ; -4.184 ; -5.297 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[13]     ; CLK_PLL1   ; -3.556 ; -4.560 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[14]     ; CLK_PLL1   ; -3.216 ; -4.149 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  DATA[15]     ; CLK_PLL1   ; -3.263 ; -4.260 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; -3.912 ; -4.883 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; -4.988 ; -6.122 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; -5.303 ; -6.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; -5.508 ; -6.672 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; -5.136 ; -6.259 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; -4.391 ; -5.454 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; -4.640 ; -5.679 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; -4.803 ; -5.887 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; -4.776 ; -5.874 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; -5.314 ; -6.482 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; -6.012 ; -7.270 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; -4.892 ; -5.956 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; -4.858 ; -5.942 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; -3.912 ; -4.893 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; -4.051 ; -4.883 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; -4.220 ; -5.070 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; -5.803 ; -6.868 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; MISO          ; CLK_PLL1   ; -1.880 ; -2.606 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_CDn       ; CLK_PLL1   ; -2.524 ; -3.329 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                                              ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 11.857 ; 11.166 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 24.633 ; 23.629 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 23.311 ; 22.350 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 22.659 ; 21.878 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 23.434 ; 22.535 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 24.215 ; 23.350 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 23.921 ; 23.096 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 24.633 ; 23.488 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 23.401 ; 22.676 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 23.521 ; 22.649 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 20.791 ; 19.825 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 20.659 ; 19.716 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 19.354 ; 18.547 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 19.732 ; 19.054 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 19.194 ; 18.443 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 20.939 ; 20.623 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 24.180 ; 23.629 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 22.014 ; 21.550 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 15.528 ; 15.226 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 20.910 ; 20.765 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 13.727 ; 12.842 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 13.376 ; 12.803 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 11.476 ; 10.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 12.177 ; 11.486 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 12.267 ; 11.637 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 13.306 ; 12.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 12.331 ; 11.713 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 11.688 ; 11.234 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 11.193 ; 10.888 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 13.217 ; 12.793 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 12.887 ; 12.255 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 15.283 ; 14.225 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 12.244 ; 11.406 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 12.462 ; 11.629 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 12.960 ; 12.234 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 19.320 ; 18.908 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 19.137 ; 18.719 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 20.910 ; 20.765 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 11.390 ; 10.868 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 10.992 ; 10.556 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 12.677 ; 12.184 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 12.325 ; 11.946 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 7.429  ; 7.147  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 4.464  ; 4.711  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 5.284  ; 5.020  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 5.982  ; 5.708  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 6.925  ; 7.419  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 12.317 ; 11.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 9.797  ; 9.461  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 10.248 ; 10.124 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 9.234  ; 9.013  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 9.843  ; 9.792  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 11.744 ; 11.419 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 12.317 ; 11.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 10.379 ; 10.065 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 10.459 ; 10.091 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 8.806  ; 8.542  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 8.934  ; 8.593  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 9.267  ; 8.922  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 10.107 ; 9.669  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 9.378  ; 9.007  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 9.718  ; 9.300  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 9.585  ; 9.283  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 10.294 ; 9.786  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 7.504  ; 7.856  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 7.162  ; 6.804  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 5.115  ; 4.873  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 6.760  ; 6.482  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 21.028 ; 20.952 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 23.168 ; 22.798 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 7.675  ; 8.072  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 5.679  ; 5.407  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 9.598  ; 9.437  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 11.784 ; 11.057 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 8.353  ; 7.736  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 6.702  ; 6.330  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 16.370 ; 15.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 14.537 ; 14.194 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 15.016 ; 14.686 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 13.676 ; 13.360 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 15.313 ; 15.063 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 15.707 ; 15.417 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 15.180 ; 15.005 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 15.452 ; 15.174 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 15.379 ; 14.992 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 16.370 ; 15.724 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 14.163 ; 13.819 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 15.205 ; 14.892 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 13.970 ; 13.674 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 16.180 ; 15.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 17.288 ; 16.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 12.971 ; 12.317 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 17.288 ; 16.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 21.169 ; 20.181 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 31.119 ; 30.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 28.045 ; 27.558 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 26.078 ; 25.532 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 27.360 ; 26.978 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 27.529 ; 27.015 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 26.857 ; 25.853 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 29.529 ; 28.742 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 27.152 ; 26.695 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 26.840 ; 26.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 27.059 ; 26.376 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 28.320 ; 27.869 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 27.185 ; 26.875 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 28.914 ; 28.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 28.082 ; 27.397 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 28.918 ; 28.566 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 28.545 ; 27.994 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 31.119 ; 30.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 13.804 ; 13.344 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 14.929 ; 14.278 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 14.241 ; 13.973 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 8.947  ; 8.650  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 7.454  ; 6.997  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 17.870 ; 18.023 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;        ; 9.720  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;        ; 8.662  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;        ; 7.989  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;        ; 8.349  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;        ; 8.819  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;        ; 9.342  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;        ; 8.971  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;        ; 8.412  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;        ; 7.952  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;        ; 8.987  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;        ; 9.513  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;        ; 11.483 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;        ; 8.589  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;        ; 8.809  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;        ; 9.067  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 16.578 ; 16.166 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 16.395 ; 15.069 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 17.870 ; 18.023 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 18.286 ; 17.826 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 20.426 ; 19.672 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 13.226 ; 12.595 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 11.176 ; 10.826 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 11.335 ; 11.149 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 10.050 ; 9.770  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 11.550 ; 11.285 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 11.470 ; 11.173 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 11.882 ; 11.614 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 12.686 ; 12.432 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 12.397 ; 11.992 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 13.226 ; 12.595 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 10.180 ; 9.988  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 11.965 ; 11.738 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.903 ; 10.693 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 12.459 ; 12.176 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 13.791 ; 13.796 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;        ; 9.575  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 13.791 ; 13.796 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 17.672 ; 17.439 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.193 ; 25.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 23.128 ; 22.631 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 23.196 ; 22.397 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 23.285 ; 22.360 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 24.073 ; 23.320 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 23.516 ; 22.603 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 25.834 ; 25.047 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 23.457 ; 23.000 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 23.145 ; 22.616 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 24.317 ; 22.425 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 24.090 ; 23.639 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 23.490 ; 23.180 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 23.987 ; 23.538 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 23.176 ; 22.470 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 23.992 ; 23.640 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 24.522 ; 23.971 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 26.193 ; 25.649 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 10.854 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 11.979 ;        ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 18.367 ; 18.078 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 16.719 ; 16.350 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 16.573 ; 16.348 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 18.367 ; 18.078 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 8.843  ; 8.821  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 8.640  ; 8.465  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 8.820  ; 8.624  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 8.711  ; 8.821  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 8.843  ; 8.779  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 11.046 ; 10.494 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 11.046 ; 10.494 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 10.122 ; 10.026 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 8.615  ; 8.610  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 7.275  ; 7.057  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 9.662  ; 9.647  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 9.662  ; 9.647  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 8.630  ; 8.641  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 9.186  ; 9.335  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 9.513  ; 9.309  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 8.638  ; 9.220  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 18.176 ; 18.248 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 20.316 ; 20.094 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 7.434  ; 7.025  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 13.460 ; 12.937 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 11.474 ; 11.099 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 9.432  ; 9.326  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 10.788 ; 10.448 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 11.005 ; 10.740 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 11.563 ; 11.273 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 12.017 ; 11.143 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 11.046 ; 10.747 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 12.376 ; 11.932 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 13.460 ; 12.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 13.215 ; 12.245 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 12.498 ; 12.937 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 10.443 ; 10.233 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 12.102 ; 11.734 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 17.778 ; 16.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 8.590  ; 8.048  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 17.778 ; 16.905 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 21.659 ; 20.548 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 2.790  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 27.909 ; 27.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 26.206 ; 25.238 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 26.568 ; 25.658 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 27.260 ; 26.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 27.595 ; 27.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 27.347 ; 26.343 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 27.909 ; 26.778 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 26.429 ; 25.744 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 26.663 ; 25.962 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 27.545 ; 26.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 25.531 ; 24.913 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 24.169 ; 23.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 25.225 ; 24.776 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 25.404 ; 24.410 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 25.229 ; 24.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 26.704 ; 26.153 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 27.430 ; 26.886 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 11.807 ; 11.233 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 12.932 ; 12.167 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 10.166 ; 9.854  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 10.552 ; 10.414 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 13.009 ; 12.517 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 2.756  ;        ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;        ; 2.558  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;        ; 2.524  ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 30.013 ; 29.632 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 21.338 ; 20.571 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 20.426 ; 19.967 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 19.683 ; 19.067 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 19.823 ; 19.245 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 20.420 ; 19.752 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 21.191 ; 20.390 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 20.800 ; 20.170 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 20.066 ; 19.529 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 19.763 ; 19.218 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 20.980 ; 20.342 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 21.519 ; 20.850 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 23.797 ; 22.695 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 20.914 ; 20.186 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 21.115 ; 20.434 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 21.692 ; 21.037 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 28.365 ; 27.996 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 28.004 ; 27.822 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 30.013 ; 29.632 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 29.895 ; 30.055 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 32.035 ; 31.901 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 25.009 ; 24.482 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 23.190 ; 22.847 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 23.748 ; 23.418 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 21.787 ; 21.471 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 23.275 ; 23.025 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 24.021 ; 23.731 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 24.345 ; 24.084 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 23.208 ; 22.810 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 24.279 ; 23.892 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 25.009 ; 24.355 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 21.965 ; 21.621 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 23.837 ; 23.524 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 22.484 ; 22.188 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 24.850 ; 24.482 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 26.233 ; 25.641 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 22.544 ; 21.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 26.233 ; 25.641 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 30.114 ; 29.284 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 37.490 ; 36.946 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 34.737 ; 34.049 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 35.088 ; 34.289 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 35.025 ; 34.179 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 35.435 ; 34.902 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 35.140 ; 34.616 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 35.931 ; 35.224 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 34.557 ; 33.992 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 34.428 ; 33.727 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 35.875 ; 35.001 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 34.873 ; 34.441 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 33.556 ; 33.246 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 35.285 ; 34.836 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 35.141 ; 34.391 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 35.289 ; 34.937 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 36.203 ; 35.652 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 37.490 ; 36.946 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 20.691 ; 20.084 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 20.548 ; 20.081 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 14.269 ; 14.471 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 9.942  ; 9.560  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 16.327 ; 16.091 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 14.679 ; 14.310 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 14.586 ; 14.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 16.327 ; 16.091 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 16.189 ; 16.208 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 18.329 ; 18.054 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 15.738 ; 14.918 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 15.738 ; 14.918 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 19.619 ; 18.561 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 26.694 ; 25.922 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 25.510 ; 24.364 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 25.353 ; 24.443 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 26.045 ; 25.127 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 26.380 ; 25.922 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 26.132 ; 25.128 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 26.694 ; 25.563 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 25.214 ; 24.529 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 25.448 ; 24.747 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 26.347 ; 25.375 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 24.434 ; 23.698 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 22.954 ; 22.143 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 23.956 ; 23.165 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 24.211 ; 23.308 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 23.868 ; 23.204 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 25.781 ; 25.230 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 25.056 ; 24.592 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 14.662 ; 14.336 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 14.638 ; 14.198 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 4.803  ; 4.615  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 8.980  ; 8.200  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 8.393  ; 7.942  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 5.798  ; 5.562  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 11.137 ; 10.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 11.137 ; 10.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 7.910  ; 7.354  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 4.904  ; 4.593  ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                                    ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                                        ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+
; LED3          ; CLK_PLL1   ; 5.826 ; 5.758 ; Rise       ; CLK_PLL1                                                                                               ;
; RAM_DATA[*]   ; CLK_PLL1   ; 7.012 ; 7.023 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 7.522 ; 7.792 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 7.584 ; 7.858 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 8.160 ; 8.480 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 8.864 ; 9.119 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 7.884 ; 8.176 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 9.277 ; 9.351 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 7.491 ; 7.684 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 7.626 ; 7.781 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 7.885 ; 8.004 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 7.685 ; 7.804 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[10] ; CLK_PLL1   ; 7.033 ; 7.048 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[11] ; CLK_PLL1   ; 7.186 ; 7.238 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[12] ; CLK_PLL1   ; 7.462 ; 7.589 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[13] ; CLK_PLL1   ; 7.012 ; 7.023 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[14] ; CLK_PLL1   ; 7.896 ; 7.995 ; Rise       ; CLK_PLL1                                                                                               ;
;  RAM_DATA[15] ; CLK_PLL1   ; 7.349 ; 7.411 ; Rise       ; CLK_PLL1                                                                                               ;
; RESETn        ; CLK_PLL1   ; 6.989 ; 7.169 ; Rise       ; CLK_PLL1                                                                                               ;
; ADR[*]        ; CLK_PLL1   ; 2.296 ; 2.366 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ; 3.070 ; 3.105 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ; 3.210 ; 3.289 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ; 2.594 ; 2.668 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ; 3.096 ; 3.137 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ; 2.669 ; 2.680 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ; 2.820 ; 2.871 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ; 2.677 ; 2.718 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ; 2.796 ; 2.826 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ; 2.643 ; 2.650 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ; 2.882 ; 2.927 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ; 2.441 ; 2.438 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ; 3.990 ; 3.855 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ; 2.425 ; 2.503 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ; 2.495 ; 2.587 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ; 2.296 ; 2.378 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 2.303 ; 2.366 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 2.439 ; 2.548 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 2.726 ; 2.848 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[19]      ; CLK_PLL1   ; 2.999 ; 3.144 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[20]      ; CLK_PLL1   ; 2.798 ; 2.947 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[21]      ; CLK_PLL1   ; 3.581 ; 3.844 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[22]      ; CLK_PLL1   ; 3.302 ; 3.561 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; BOOT_REQ      ; CLK_PLL1   ; 2.607 ; 2.689 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_LDACn     ; CLK_PLL1   ; 1.948 ; 1.921 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SCLK      ; CLK_PLL1   ; 2.199 ; 2.227 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SDATA     ; CLK_PLL1   ; 2.523 ; 2.561 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DAC_SYNCn     ; CLK_PLL1   ; 2.489 ; 2.407 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DATA[*]       ; CLK_PLL1   ; 2.509 ; 2.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[0]      ; CLK_PLL1   ; 2.986 ; 3.143 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[1]      ; CLK_PLL1   ; 2.896 ; 3.048 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[2]      ; CLK_PLL1   ; 2.866 ; 3.047 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[3]      ; CLK_PLL1   ; 2.847 ; 2.932 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[4]      ; CLK_PLL1   ; 3.379 ; 3.397 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[5]      ; CLK_PLL1   ; 4.696 ; 4.558 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[6]      ; CLK_PLL1   ; 3.263 ; 3.340 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[7]      ; CLK_PLL1   ; 2.959 ; 3.123 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[8]      ; CLK_PLL1   ; 2.509 ; 2.635 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[9]      ; CLK_PLL1   ; 2.574 ; 2.700 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[10]     ; CLK_PLL1   ; 2.679 ; 2.825 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[11]     ; CLK_PLL1   ; 2.993 ; 3.172 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[12]     ; CLK_PLL1   ; 2.746 ; 2.859 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[13]     ; CLK_PLL1   ; 2.844 ; 2.993 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[14]     ; CLK_PLL1   ; 2.877 ; 3.041 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  DATA[15]     ; CLK_PLL1   ; 3.056 ; 3.231 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 3.062 ; 2.918 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_CE     ; CLK_PLL1   ; 2.656 ; 2.788 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_D      ; CLK_PLL1   ; 2.103 ; 2.151 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; DS1392_SCL    ; CLK_PLL1   ; 2.488 ; 2.596 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 3.096 ; 3.226 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 4.673 ; 4.565 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_WEn     ; CLK_PLL1   ; 3.132 ; 2.950 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; HSYNC         ; CLK_PLL1   ; 2.335 ; 2.413 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; KEYB_TxD      ; CLK_PLL1   ; 3.451 ; 3.651 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED1          ; CLK_PLL1   ; 3.526 ; 3.343 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; LED3          ; CLK_PLL1   ; 4.005 ; 3.914 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; MISO          ; CLK_PLL1   ; 2.709 ; 2.858 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 4.036 ; 4.087 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 4.288 ; 4.348 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.218 ; 4.250 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.036 ; 4.087 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 4.273 ; 4.341 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 4.484 ; 4.543 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 4.645 ; 4.700 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 4.655 ; 4.710 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 4.386 ; 4.513 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.000 ; 5.795 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.169 ; 4.207 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 4.948 ; 4.995 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.478 ; 4.484 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.123 ; 5.162 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 4.115 ; 4.583 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 4.115 ; 4.583 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 4.585 ; 4.718 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 5.114 ; 5.418 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.444 ; 3.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 3.599 ; 3.774 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 3.444 ; 3.590 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 4.164 ; 4.427 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 4.500 ; 4.616 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.257 ; 4.275 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.310 ; 5.263 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 3.808 ; 3.994 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 3.789 ; 3.970 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.317 ; 4.405 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.122 ; 4.319 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 3.659 ; 3.787 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 3.671 ; 3.794 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.082 ; 4.256 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.516 ; 3.603 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.195 ; 4.319 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 3.460 ; 3.601 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.151 ; 4.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 4.508 ; 4.809 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_WEn       ; CLK_PLL1   ; 5.155 ; 5.358 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RESETn        ; CLK_PLL1   ; 3.396 ; 3.468 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; VSYNC         ; CLK_PLL1   ; 2.996 ; 3.195 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 4.585 ; 3.422 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[1]       ; CLK_PLL1   ;       ; 4.312 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[2]       ; CLK_PLL1   ;       ; 3.844 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[3]       ; CLK_PLL1   ;       ; 3.561 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[4]       ; CLK_PLL1   ;       ; 3.654 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[5]       ; CLK_PLL1   ;       ; 3.871 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[6]       ; CLK_PLL1   ;       ; 4.059 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[7]       ; CLK_PLL1   ;       ; 3.940 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[8]       ; CLK_PLL1   ;       ; 3.566 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[9]       ; CLK_PLL1   ;       ; 3.422 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[10]      ; CLK_PLL1   ;       ; 3.944 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[11]      ; CLK_PLL1   ;       ; 4.206 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[12]      ; CLK_PLL1   ;       ; 5.515 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[13]      ; CLK_PLL1   ;       ; 3.723 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[14]      ; CLK_PLL1   ;       ; 3.830 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[15]      ; CLK_PLL1   ;       ; 4.004 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[16]      ; CLK_PLL1   ; 4.836 ; 4.411 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[17]      ; CLK_PLL1   ; 4.585 ; 4.654 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  ADR[18]      ; CLK_PLL1   ; 5.358 ; 4.716 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_CEn     ; CLK_PLL1   ; 5.780 ; 5.645 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.287 ; 6.917 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 4.108 ; 4.152 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 4.440 ; 4.463 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.431 ; 4.419 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.108 ; 4.152 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 4.471 ; 4.445 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 4.622 ; 4.674 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 4.848 ; 4.851 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 4.801 ; 4.849 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 4.487 ; 4.527 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.054 ; 5.868 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.307 ; 4.341 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 5.128 ; 5.131 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.711 ; 4.673 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.364 ; 5.366 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_BA[*]     ; CLK_PLL1   ; 5.072 ; 4.209 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[0]    ; CLK_PLL1   ;       ; 4.209 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 5.072 ; 5.321 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_CASn      ; CLK_PLL1   ; 5.279 ; 6.263 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 4.446 ; 4.457 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 4.757 ; 4.769 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.533 ; 4.585 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 4.766 ; 4.805 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 5.001 ; 5.033 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.446 ; 4.457 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 5.964 ; 5.772 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 4.582 ; 4.600 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 4.655 ; 4.682 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.561 ; 4.651 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.526 ; 4.613 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.465 ; 4.783 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.657 ; 4.754 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.973 ; 5.055 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.483 ; 4.785 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.703 ; 4.812 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.839 ; 5.173 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.316 ;       ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; RAM_DQML      ; CLK_PLL1   ; 4.673 ;       ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ;
; ADR[*]        ; CLK_PLL1   ; 5.045 ; 5.142 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[16]      ; CLK_PLL1   ; 5.329 ; 5.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[17]      ; CLK_PLL1   ; 5.045 ; 5.142 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  ADR[18]      ; CLK_PLL1   ; 5.625 ; 5.766 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_B[*]      ; CLK_PLL1   ; 2.690 ; 2.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[4]     ; CLK_PLL1   ; 2.720 ; 2.850 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[5]     ; CLK_PLL1   ; 3.028 ; 3.225 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[6]     ; CLK_PLL1   ; 2.690 ; 2.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_B[7]     ; CLK_PLL1   ; 2.793 ; 2.896 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_G[*]      ; CLK_PLL1   ; 2.667 ; 2.797 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[4]     ; CLK_PLL1   ; 4.596 ; 4.552 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[5]     ; CLK_PLL1   ; 3.391 ; 3.629 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[6]     ; CLK_PLL1   ; 2.667 ; 2.797 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_G[7]     ; CLK_PLL1   ; 2.963 ; 3.057 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; CRT_R[*]      ; CLK_PLL1   ; 2.776 ; 2.922 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[4]     ; CLK_PLL1   ; 3.180 ; 3.381 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[5]     ; CLK_PLL1   ; 3.022 ; 3.216 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[6]     ; CLK_PLL1   ; 2.776 ; 2.922 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  CRT_R[7]     ; CLK_PLL1   ; 3.075 ; 3.240 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; DRIVES_BSYn   ; CLK_PLL1   ; 3.895 ; 3.658 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_CEn     ; CLK_PLL1   ; 6.253 ; 6.150 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.760 ; 7.422 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; LED2          ; CLK_PLL1   ; 2.616 ; 2.697 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 2.484 ; 2.377 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 3.016 ; 3.163 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 2.589 ; 2.691 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 2.702 ; 2.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 2.787 ; 2.868 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 2.883 ; 3.001 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 2.681 ; 2.774 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 2.893 ; 3.024 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 3.121 ; 3.275 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 4.096 ; 3.953 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 2.894 ; 2.904 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 2.898 ; 2.914 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 2.484 ; 2.377 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 2.627 ; 2.557 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_BA[*]     ; CLK_PLL1   ; 2.628 ; 2.663 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 2.628 ; 2.663 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 2.737 ; 2.844 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CASn      ; CLK_PLL1   ; 3.262 ; 3.202 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ; 1.107 ;       ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 2.309 ; 2.331 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 2.389 ; 2.400 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 2.526 ; 2.487 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 2.495 ; 2.592 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 2.724 ; 2.739 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 2.309 ; 2.331 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 3.826 ; 3.645 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 2.445 ; 2.474 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 2.513 ; 2.551 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 2.739 ; 2.812 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 2.669 ; 2.756 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 2.515 ; 2.599 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 2.600 ; 2.632 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 2.801 ; 2.801 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 2.689 ; 2.684 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 2.708 ; 2.808 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 2.990 ; 3.037 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQMH      ; CLK_PLL1   ; 2.592 ; 2.530 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_DQML      ; CLK_PLL1   ; 2.717 ; 2.676 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_RASn      ; CLK_PLL1   ; 2.743 ; 2.721 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_WEn       ; CLK_PLL1   ; 2.606 ; 2.575 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RESETn        ; CLK_PLL1   ; 4.626 ; 5.001 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ; 1.074 ;       ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; RAM_CLK       ; CLK_PLL1   ;       ; 1.081 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; VDAC_CLK      ; CLK_PLL1   ;       ; 1.048 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ;
; ADR[*]        ; CLK_PLL1   ; 3.551 ; 3.672 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[1]       ; CLK_PLL1   ; 4.315 ; 4.556 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[2]       ; CLK_PLL1   ; 3.991 ; 4.206 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[3]       ; CLK_PLL1   ; 3.617 ; 3.775 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[4]       ; CLK_PLL1   ; 3.661 ; 3.837 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[5]       ; CLK_PLL1   ; 3.827 ; 3.997 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[6]       ; CLK_PLL1   ; 4.089 ; 4.283 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[7]       ; CLK_PLL1   ; 3.966 ; 4.158 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[8]       ; CLK_PLL1   ; 3.623 ; 3.788 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[9]       ; CLK_PLL1   ; 3.551 ; 3.672 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[10]      ; CLK_PLL1   ; 3.971 ; 4.159 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[11]      ; CLK_PLL1   ; 4.205 ; 4.349 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[12]      ; CLK_PLL1   ; 5.743 ; 5.713 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[13]      ; CLK_PLL1   ; 3.788 ; 3.942 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[14]      ; CLK_PLL1   ; 3.891 ; 4.054 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[15]      ; CLK_PLL1   ; 4.406 ; 4.599 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 4.736 ; 4.910 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 4.265 ; 4.465 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 5.060 ; 5.311 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 5.574 ; 5.566 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.081 ; 6.838 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_ADR[*]    ; CLK_PLL1   ; 4.189 ; 4.249 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[0]   ; CLK_PLL1   ; 4.438 ; 4.498 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[1]   ; CLK_PLL1   ; 4.506 ; 4.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[2]   ; CLK_PLL1   ; 4.189 ; 4.249 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[3]   ; CLK_PLL1   ; 4.377 ; 4.445 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[4]   ; CLK_PLL1   ; 4.523 ; 4.582 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[5]   ; CLK_PLL1   ; 4.794 ; 4.884 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[6]   ; CLK_PLL1   ; 4.786 ; 4.841 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[7]   ; CLK_PLL1   ; 4.524 ; 4.651 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[8]   ; CLK_PLL1   ; 6.053 ; 5.848 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[9]   ; CLK_PLL1   ; 4.344 ; 4.382 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[10]  ; CLK_PLL1   ; 5.042 ; 5.089 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[11]  ; CLK_PLL1   ; 4.588 ; 4.594 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_ADR[12]  ; CLK_PLL1   ; 5.255 ; 5.294 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 4.343 ; 4.526 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[0]    ; CLK_PLL1   ; 4.343 ; 4.526 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 4.790 ; 4.975 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 5.135 ; 5.452 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 3.900 ; 4.120 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 4.279 ; 4.538 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.274 ; 4.551 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 4.849 ; 4.813 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 4.838 ; 4.877 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 4.545 ; 4.563 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 6.061 ; 5.876 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 4.623 ; 4.705 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 4.492 ; 4.786 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 4.719 ; 4.806 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 4.684 ; 4.768 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 4.223 ; 4.446 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.270 ; 4.536 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 4.635 ; 4.939 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 3.900 ; 4.120 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 4.571 ; 4.875 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 4.438 ; 4.647 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 4.188 ; 4.368 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 4.158 ; 4.379 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_WEn       ; CLK_PLL1   ; 4.821 ; 4.790 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RESETn        ; CLK_PLL1   ; 4.274 ; 4.239 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; ADR[*]        ; CLK_PLL1   ; 4.589 ; 4.879 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[16]      ; CLK_PLL1   ; 5.060 ; 5.234 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[17]      ; CLK_PLL1   ; 4.589 ; 4.879 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  ADR[18]      ; CLK_PLL1   ; 5.418 ; 5.544 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_CEn     ; CLK_PLL1   ; 5.988 ; 5.890 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; FLASH_OEn     ; CLK_PLL1   ; 7.495 ; 7.162 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_BA[*]     ; CLK_PLL1   ; 5.543 ; 5.925 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_BA[1]    ; CLK_PLL1   ; 5.543 ; 5.925 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_CASn      ; CLK_PLL1   ; 5.948 ; 6.212 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DATA[*]   ; CLK_PLL1   ; 4.737 ; 4.889 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[0]  ; CLK_PLL1   ; 5.351 ; 5.684 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[1]  ; CLK_PLL1   ; 4.874 ; 5.160 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[2]  ; CLK_PLL1   ; 5.451 ; 5.765 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[3]  ; CLK_PLL1   ; 5.326 ; 5.671 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[4]  ; CLK_PLL1   ; 6.110 ; 6.449 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[5]  ; CLK_PLL1   ; 7.129 ; 7.176 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[6]  ; CLK_PLL1   ; 5.539 ; 5.894 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[7]  ; CLK_PLL1   ; 5.523 ; 5.897 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[8]  ; CLK_PLL1   ; 6.180 ; 6.560 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[9]  ; CLK_PLL1   ; 5.899 ; 6.290 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[10] ; CLK_PLL1   ; 5.742 ; 6.066 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[11] ; CLK_PLL1   ; 4.973 ; 5.203 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[12] ; CLK_PLL1   ; 5.685 ; 6.028 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[13] ; CLK_PLL1   ; 4.737 ; 4.889 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[14] ; CLK_PLL1   ; 5.638 ; 5.859 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
;  RAM_DATA[15] ; CLK_PLL1   ; 5.564 ; 5.790 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQMH      ; CLK_PLL1   ; 5.001 ; 5.128 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; RAM_DQML      ; CLK_PLL1   ; 4.953 ; 5.142 ; Fall       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ;
; JOY_DIS       ; CLK_PLL1   ; 1.934 ; 1.957 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED1          ; CLK_PLL1   ; 4.195 ; 4.113 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; LED2          ; CLK_PLL1   ; 3.407 ; 3.603 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; MOSI          ; CLK_PLL1   ; 1.919 ; 1.924 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_D[*]      ; CLK_PLL1   ; 2.929 ; 2.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
;  SDC_D[3]     ; CLK_PLL1   ; 2.929 ; 2.938 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_PWRn      ; CLK_PLL1   ; 3.148 ; 3.274 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
; SDC_SPI_CLK   ; CLK_PLL1   ; 1.995 ; 2.003 ; Rise       ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------+
; Propagation Delay                                               ;
+--------------+--------------+--------+--------+--------+--------+
; Input Port   ; Output Port  ; RR     ; RF     ; FR     ; FF     ;
+--------------+--------------+--------+--------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 21.372 ; 20.452 ; 21.740 ; 20.701 ;
; CONFIG[1]    ; RAM_DATA[12] ; 11.883 ; 11.850 ; 12.521 ; 11.694 ;
; CONFIG[1]    ; RAM_DATA[13] ; 11.542 ; 11.543 ; 12.070 ; 11.500 ;
; CONFIG[1]    ; RAM_DATA[14] ; 11.083 ; 10.865 ; 11.408 ; 11.046 ;
; CONFIG[1]    ; RAM_DATA[15] ; 11.257 ; 12.448 ; 13.041 ; 11.155 ;
; CONFIG[2]    ; RAM_DATA[7]  ; 21.013 ; 20.097 ; 21.370 ; 20.330 ;
; CONFIG[2]    ; RAM_DATA[12] ; 11.530 ; 11.497 ; 12.222 ; 11.395 ;
; CONFIG[2]    ; RAM_DATA[13] ; 11.189 ; 11.190 ; 11.771 ; 11.201 ;
; CONFIG[2]    ; RAM_DATA[14] ; 10.730 ; 10.512 ; 11.109 ; 10.747 ;
; CONFIG[2]    ; RAM_DATA[15] ; 10.904 ; 12.095 ; 12.742 ; 10.856 ;
; CONFIG[3]    ; ADR[16]      ; 21.898 ; 21.486 ; 21.807 ; 21.438 ;
; CONFIG[3]    ; ADR[17]      ; 21.715 ; 21.235 ; 21.418 ; 21.264 ;
; CONFIG[3]    ; ADR[18]      ; 23.426 ; 23.343 ; 23.455 ; 23.046 ;
; CONFIG[3]    ; ADR[22]      ; 11.136 ;        ;        ; 11.170 ;
; CONFIG[3]    ; FLASH_CEn    ; 23.606 ; 23.468 ; 23.309 ; 23.497 ;
; CONFIG[3]    ; FLASH_OEn    ; 25.746 ; 25.314 ; 25.449 ; 25.343 ;
; CONFIG[3]    ; RAM_BA[1]    ; 19.690 ; 19.252 ; 19.790 ; 18.993 ;
; CONFIG[3]    ; RAM_CASn     ; 23.571 ; 22.895 ; 23.671 ; 22.636 ;
; CONFIG[3]    ; RAM_DATA[0]  ; 28.448 ; 27.462 ; 28.151 ; 27.491 ;
; CONFIG[3]    ; RAM_DATA[1]  ; 28.516 ; 27.717 ; 28.530 ; 27.731 ;
; CONFIG[3]    ; RAM_DATA[2]  ; 28.490 ; 27.592 ; 28.467 ; 27.621 ;
; CONFIG[3]    ; RAM_DATA[3]  ; 29.146 ; 28.315 ; 28.849 ; 28.344 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 28.836 ; 28.029 ; 28.582 ; 28.058 ;
; CONFIG[3]    ; RAM_DATA[5]  ; 29.642 ; 28.637 ; 29.345 ; 28.666 ;
; CONFIG[3]    ; RAM_DATA[6]  ; 28.201 ; 27.405 ; 27.999 ; 27.434 ;
; CONFIG[3]    ; RAM_DATA[7]  ; 27.841 ; 27.140 ; 27.870 ; 27.169 ;
; CONFIG[3]    ; RAM_DATA[8]  ; 29.586 ; 28.414 ; 29.289 ; 28.443 ;
; CONFIG[3]    ; RAM_DATA[9]  ; 28.541 ; 27.854 ; 28.315 ; 27.883 ;
; CONFIG[3]    ; RAM_DATA[10] ; 26.852 ; 26.494 ; 26.636 ; 26.523 ;
; CONFIG[3]    ; RAM_DATA[11] ; 27.929 ; 27.428 ; 27.958 ; 27.457 ;
; CONFIG[3]    ; RAM_DATA[12] ; 28.554 ; 27.804 ; 28.583 ; 27.833 ;
; CONFIG[3]    ; RAM_DATA[13] ; 27.878 ; 27.214 ; 27.618 ; 26.976 ;
; CONFIG[3]    ; RAM_DATA[14] ; 29.791 ; 29.240 ; 29.645 ; 29.094 ;
; CONFIG[3]    ; RAM_DATA[15] ; 29.066 ; 28.602 ; 28.927 ; 28.463 ;
; CONFIG[4]    ; ADR[16]      ; 21.776 ; 21.364 ; 21.500 ; 21.131 ;
; CONFIG[4]    ; ADR[17]      ; 21.593 ; 21.113 ; 21.111 ; 20.957 ;
; CONFIG[4]    ; ADR[18]      ; 23.304 ; 23.221 ; 23.148 ; 22.739 ;
; CONFIG[4]    ; ADR[21]      ; 11.655 ;        ;        ; 11.583 ;
; CONFIG[4]    ; FLASH_CEn    ; 23.484 ; 23.346 ; 23.002 ; 23.190 ;
; CONFIG[4]    ; FLASH_OEn    ; 25.624 ; 25.192 ; 25.142 ; 25.036 ;
; CONFIG[4]    ; RAM_BA[1]    ; 19.568 ; 19.130 ; 19.483 ; 18.686 ;
; CONFIG[4]    ; RAM_CASn     ; 23.449 ; 22.773 ; 23.364 ; 22.329 ;
; CONFIG[4]    ; RAM_DATA[0]  ; 28.326 ; 27.340 ; 27.844 ; 27.184 ;
; CONFIG[4]    ; RAM_DATA[1]  ; 28.394 ; 27.595 ; 28.223 ; 27.424 ;
; CONFIG[4]    ; RAM_DATA[2]  ; 28.368 ; 27.470 ; 28.160 ; 27.314 ;
; CONFIG[4]    ; RAM_DATA[3]  ; 29.024 ; 28.193 ; 28.542 ; 28.037 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 28.714 ; 27.907 ; 28.275 ; 27.751 ;
; CONFIG[4]    ; RAM_DATA[5]  ; 29.520 ; 28.515 ; 29.038 ; 28.359 ;
; CONFIG[4]    ; RAM_DATA[6]  ; 28.079 ; 27.283 ; 27.692 ; 27.127 ;
; CONFIG[4]    ; RAM_DATA[7]  ; 27.719 ; 27.018 ; 27.563 ; 26.862 ;
; CONFIG[4]    ; RAM_DATA[8]  ; 29.464 ; 28.292 ; 28.982 ; 28.136 ;
; CONFIG[4]    ; RAM_DATA[9]  ; 28.419 ; 27.732 ; 28.008 ; 27.576 ;
; CONFIG[4]    ; RAM_DATA[10] ; 26.730 ; 26.372 ; 26.329 ; 26.216 ;
; CONFIG[4]    ; RAM_DATA[11] ; 27.807 ; 27.306 ; 27.651 ; 27.150 ;
; CONFIG[4]    ; RAM_DATA[12] ; 28.432 ; 27.682 ; 28.276 ; 27.526 ;
; CONFIG[4]    ; RAM_DATA[13] ; 27.756 ; 27.092 ; 27.311 ; 26.669 ;
; CONFIG[4]    ; RAM_DATA[14] ; 29.669 ; 29.118 ; 29.338 ; 28.787 ;
; CONFIG[4]    ; RAM_DATA[15] ; 28.944 ; 28.480 ; 28.620 ; 28.156 ;
; CONFIG[5]    ; ADR[16]      ; 22.037 ; 21.625 ; 21.750 ; 21.381 ;
; CONFIG[5]    ; ADR[17]      ; 21.854 ; 21.374 ; 21.361 ; 21.207 ;
; CONFIG[5]    ; ADR[18]      ; 23.565 ; 23.482 ; 23.398 ; 22.989 ;
; CONFIG[5]    ; ADR[20]      ; 10.065 ;        ;        ; 10.069 ;
; CONFIG[5]    ; FLASH_CEn    ; 23.745 ; 23.607 ; 23.252 ; 23.440 ;
; CONFIG[5]    ; FLASH_OEn    ; 25.885 ; 25.453 ; 25.392 ; 25.286 ;
; CONFIG[5]    ; RAM_BA[1]    ; 19.829 ; 19.391 ; 19.733 ; 18.936 ;
; CONFIG[5]    ; RAM_CASn     ; 23.710 ; 23.034 ; 23.614 ; 22.579 ;
; CONFIG[5]    ; RAM_DATA[0]  ; 28.587 ; 27.601 ; 28.094 ; 27.434 ;
; CONFIG[5]    ; RAM_DATA[1]  ; 28.655 ; 27.856 ; 28.473 ; 27.674 ;
; CONFIG[5]    ; RAM_DATA[2]  ; 28.629 ; 27.731 ; 28.410 ; 27.564 ;
; CONFIG[5]    ; RAM_DATA[3]  ; 29.285 ; 28.454 ; 28.792 ; 28.287 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 28.975 ; 28.168 ; 28.525 ; 28.001 ;
; CONFIG[5]    ; RAM_DATA[5]  ; 29.781 ; 28.776 ; 29.288 ; 28.609 ;
; CONFIG[5]    ; RAM_DATA[6]  ; 28.340 ; 27.544 ; 27.942 ; 27.377 ;
; CONFIG[5]    ; RAM_DATA[7]  ; 27.980 ; 27.279 ; 27.813 ; 27.112 ;
; CONFIG[5]    ; RAM_DATA[8]  ; 29.725 ; 28.553 ; 29.232 ; 28.386 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 28.680 ; 27.993 ; 28.258 ; 27.826 ;
; CONFIG[5]    ; RAM_DATA[10] ; 26.991 ; 26.633 ; 26.579 ; 26.466 ;
; CONFIG[5]    ; RAM_DATA[11] ; 28.068 ; 27.567 ; 27.901 ; 27.400 ;
; CONFIG[5]    ; RAM_DATA[12] ; 28.693 ; 27.943 ; 28.526 ; 27.776 ;
; CONFIG[5]    ; RAM_DATA[13] ; 28.017 ; 27.353 ; 27.561 ; 26.919 ;
; CONFIG[5]    ; RAM_DATA[14] ; 29.930 ; 29.379 ; 29.588 ; 29.037 ;
; CONFIG[5]    ; RAM_DATA[15] ; 29.205 ; 28.741 ; 28.870 ; 28.406 ;
; CONFIG[6]    ; ADR[19]      ; 10.474 ;        ;        ; 10.370 ;
; DATA[0]      ; RAM_DATA[0]  ; 14.981 ;        ;        ; 14.908 ;
; DATA[1]      ; RAM_DATA[1]  ; 15.530 ;        ;        ; 15.205 ;
; DATA[2]      ; RAM_DATA[2]  ; 16.625 ;        ;        ; 16.218 ;
; DATA[3]      ; RAM_DATA[3]  ; 17.985 ;        ;        ; 17.746 ;
; DATA[4]      ; RAM_DATA[4]  ; 16.174 ;        ;        ; 15.865 ;
; DATA[5]      ; RAM_DATA[5]  ; 16.513 ;        ;        ; 15.980 ;
; DATA[6]      ; RAM_DATA[6]  ; 16.337 ;        ;        ; 16.119 ;
; DATA[7]      ; RAM_DATA[7]  ; 16.842 ;        ;        ; 16.558 ;
; DATA[8]      ; RAM_DATA[8]  ; 17.177 ;        ;        ; 16.879 ;
; DATA[9]      ; RAM_DATA[9]  ; 18.819 ;        ;        ; 18.212 ;
; DATA[10]     ; RAM_DATA[10] ; 15.877 ;        ;        ; 15.657 ;
; DATA[11]     ; RAM_DATA[11] ; 17.199 ;        ;        ; 16.655 ;
; DATA[12]     ; RAM_DATA[12] ; 18.176 ;        ;        ; 17.589 ;
; DATA[13]     ; RAM_DATA[13] ; 13.850 ;        ;        ; 13.620 ;
; DATA[14]     ; RAM_DATA[14] ; 14.126 ;        ;        ; 13.859 ;
; DATA[15]     ; RAM_DATA[15] ; 13.141 ;        ;        ; 13.030 ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 17.609 ;        ;        ; 17.253 ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 17.855 ;        ;        ; 17.196 ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 20.054 ;        ;        ; 19.098 ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 20.119 ;        ;        ; 19.455 ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 17.730 ;        ;        ; 17.117 ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 18.531 ;        ;        ; 17.644 ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 17.350 ;        ;        ; 16.912 ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 17.620 ;        ;        ; 17.081 ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 19.132 ;        ;        ; 18.487 ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 20.951 ;        ;        ; 20.030 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 16.685 ;        ;        ; 16.110 ;
; RAM_DATA[11] ; RAM_DATA[11] ; 17.030 ;        ;        ; 16.403 ;
; RAM_DATA[12] ; RAM_DATA[12] ; 15.718 ;        ;        ; 15.349 ;
; RAM_DATA[13] ; RAM_DATA[13] ; 14.584 ; 13.920 ; 14.780 ; 14.109 ;
; RAM_DATA[14] ; RAM_DATA[14] ; 17.134 ; 16.583 ; 17.346 ; 16.795 ;
; RAM_DATA[15] ; RAM_DATA[15] ; 20.269 ; 19.805 ; 20.203 ; 19.739 ;
; RESET_COREn  ; RAM_CKE      ; 4.787  ;        ;        ; 4.983  ;
; RESETn       ; KEYB_TxD     ; 10.422 ; 10.422 ; 10.638 ; 10.378 ;
+--------------+--------------+--------+--------+--------+--------+


+---------------------------------------------------------------+
; Minimum Propagation Delay                                     ;
+--------------+--------------+-------+-------+--------+--------+
; Input Port   ; Output Port  ; RR    ; RF    ; FR     ; FF     ;
+--------------+--------------+-------+-------+--------+--------+
; CONFIG[1]    ; RAM_DATA[7]  ; 8.882 ; 9.375 ; 9.709  ; 10.173 ;
; CONFIG[1]    ; RAM_DATA[12] ; 5.255 ; 5.451 ; 6.232  ; 6.150  ;
; CONFIG[1]    ; RAM_DATA[13] ; 5.110 ; 5.268 ; 6.046  ; 6.002  ;
; CONFIG[1]    ; RAM_DATA[14] ; 4.976 ; 5.014 ; 5.836  ; 5.830  ;
; CONFIG[1]    ; RAM_DATA[15] ; 5.037 ; 5.649 ; 6.423  ; 5.882  ;
; CONFIG[2]    ; RAM_DATA[7]  ; 8.728 ; 9.225 ; 9.539  ; 10.003 ;
; CONFIG[2]    ; RAM_DATA[12] ; 5.111 ; 5.307 ; 6.088  ; 6.006  ;
; CONFIG[2]    ; RAM_DATA[13] ; 4.966 ; 5.124 ; 5.902  ; 5.858  ;
; CONFIG[2]    ; RAM_DATA[14] ; 4.832 ; 4.870 ; 5.692  ; 5.686  ;
; CONFIG[2]    ; RAM_DATA[15] ; 4.893 ; 5.505 ; 6.279  ; 5.738  ;
; CONFIG[3]    ; ADR[16]      ; 7.706 ; 7.843 ; 8.758  ; 8.919  ;
; CONFIG[3]    ; ADR[17]      ; 7.405 ; 7.521 ; 8.355  ; 8.619  ;
; CONFIG[3]    ; ADR[18]      ; 6.095 ; 9.180 ; 10.153 ; 7.127  ;
; CONFIG[3]    ; ADR[22]      ; 5.060 ;       ;        ; 6.011  ;
; CONFIG[3]    ; FLASH_CEn    ; 7.426 ; 8.226 ; 9.026  ; 8.410  ;
; CONFIG[3]    ; FLASH_OEn    ; 8.933 ; 9.498 ; 10.533 ; 9.682  ;
; CONFIG[3]    ; RAM_BA[1]    ; 7.441 ; 6.936 ; 7.819  ; 8.650  ;
; CONFIG[3]    ; RAM_CASn     ; 7.997 ; 8.108 ; 9.099  ; 9.010  ;
; CONFIG[3]    ; RAM_DATA[0]  ; 8.112 ; 8.093 ; 8.809  ; 9.275  ;
; CONFIG[3]    ; RAM_DATA[1]  ; 8.133 ; 8.225 ; 9.007  ; 9.276  ;
; CONFIG[3]    ; RAM_DATA[2]  ; 8.614 ; 8.615 ; 9.304  ; 9.770  ;
; CONFIG[3]    ; RAM_DATA[3]  ; 8.962 ; 8.815 ; 9.449  ; 10.230 ;
; CONFIG[3]    ; RAM_DATA[4]  ; 8.483 ; 8.398 ; 9.118  ; 9.638  ;
; CONFIG[3]    ; RAM_DATA[5]  ; 9.200 ; 8.968 ; 9.962  ; 9.980  ;
; CONFIG[3]    ; RAM_DATA[6]  ; 8.577 ; 8.606 ; 9.276  ; 9.616  ;
; CONFIG[3]    ; RAM_DATA[7]  ; 8.289 ; 8.239 ; 8.982  ; 9.304  ;
; CONFIG[3]    ; RAM_DATA[8]  ; 8.692 ; 8.697 ; 9.377  ; 9.798  ;
; CONFIG[3]    ; RAM_DATA[9]  ; 8.476 ; 8.675 ; 9.432  ; 9.757  ;
; CONFIG[3]    ; RAM_DATA[10] ; 8.023 ; 8.075 ; 8.826  ; 9.131  ;
; CONFIG[3]    ; RAM_DATA[11] ; 8.192 ; 8.089 ; 8.847  ; 9.145  ;
; CONFIG[3]    ; RAM_DATA[12] ; 8.236 ; 8.151 ; 8.866  ; 9.401  ;
; CONFIG[3]    ; RAM_DATA[13] ; 7.308 ; 7.378 ; 8.159  ; 8.170  ;
; CONFIG[3]    ; RAM_DATA[14] ; 8.225 ; 8.343 ; 9.043  ; 9.142  ;
; CONFIG[3]    ; RAM_DATA[15] ; 7.653 ; 7.738 ; 8.496  ; 8.558  ;
; CONFIG[4]    ; ADR[16]      ; 7.578 ; 7.715 ; 8.582  ; 8.743  ;
; CONFIG[4]    ; ADR[17]      ; 7.277 ; 7.393 ; 8.179  ; 8.443  ;
; CONFIG[4]    ; ADR[18]      ; 6.022 ; 9.060 ; 9.978  ; 7.024  ;
; CONFIG[4]    ; ADR[21]      ; 5.321 ;       ;        ; 6.278  ;
; CONFIG[4]    ; FLASH_CEn    ; 7.353 ; 8.153 ; 8.923  ; 8.307  ;
; CONFIG[4]    ; FLASH_OEn    ; 8.860 ; 9.425 ; 10.430 ; 9.579  ;
; CONFIG[4]    ; RAM_BA[1]    ; 7.321 ; 6.808 ; 7.643  ; 8.475  ;
; CONFIG[4]    ; RAM_CASn     ; 7.869 ; 7.986 ; 8.923  ; 8.834  ;
; CONFIG[4]    ; RAM_DATA[0]  ; 7.984 ; 7.965 ; 8.633  ; 9.099  ;
; CONFIG[4]    ; RAM_DATA[1]  ; 8.060 ; 8.097 ; 8.831  ; 9.173  ;
; CONFIG[4]    ; RAM_DATA[2]  ; 8.541 ; 8.487 ; 9.128  ; 9.617  ;
; CONFIG[4]    ; RAM_DATA[3]  ; 8.889 ; 8.687 ; 9.273  ; 10.084 ;
; CONFIG[4]    ; RAM_DATA[4]  ; 8.410 ; 8.270 ; 8.942  ; 9.503  ;
; CONFIG[4]    ; RAM_DATA[5]  ; 9.072 ; 8.840 ; 9.786  ; 9.804  ;
; CONFIG[4]    ; RAM_DATA[6]  ; 8.449 ; 8.478 ; 9.100  ; 9.440  ;
; CONFIG[4]    ; RAM_DATA[7]  ; 8.161 ; 8.111 ; 8.806  ; 9.128  ;
; CONFIG[4]    ; RAM_DATA[8]  ; 8.619 ; 8.569 ; 9.201  ; 9.695  ;
; CONFIG[4]    ; RAM_DATA[9]  ; 8.403 ; 8.547 ; 9.256  ; 9.654  ;
; CONFIG[4]    ; RAM_DATA[10] ; 7.895 ; 7.947 ; 8.650  ; 9.018  ;
; CONFIG[4]    ; RAM_DATA[11] ; 8.064 ; 7.961 ; 8.671  ; 8.969  ;
; CONFIG[4]    ; RAM_DATA[12] ; 8.163 ; 8.023 ; 8.690  ; 9.298  ;
; CONFIG[4]    ; RAM_DATA[13] ; 7.235 ; 7.305 ; 8.056  ; 8.067  ;
; CONFIG[4]    ; RAM_DATA[14] ; 8.152 ; 8.270 ; 8.940  ; 9.039  ;
; CONFIG[4]    ; RAM_DATA[15] ; 7.580 ; 7.665 ; 8.393  ; 8.455  ;
; CONFIG[5]    ; ADR[16]      ; 7.656 ; 7.793 ; 8.704  ; 8.865  ;
; CONFIG[5]    ; ADR[17]      ; 7.355 ; 7.471 ; 8.301  ; 8.565  ;
; CONFIG[5]    ; ADR[18]      ; 8.212 ; 9.159 ; 10.120 ; 9.221  ;
; CONFIG[5]    ; ADR[20]      ; 4.593 ;       ;        ; 5.439  ;
; CONFIG[5]    ; FLASH_CEn    ; 8.125 ; 8.478 ; 9.510  ; 9.058  ;
; CONFIG[5]    ; FLASH_OEn    ; 9.632 ; 9.750 ; 11.017 ; 10.330 ;
; CONFIG[5]    ; RAM_BA[1]    ; 7.420 ; 6.886 ; 7.765  ; 8.617  ;
; CONFIG[5]    ; RAM_CASn     ; 7.947 ; 8.087 ; 9.067  ; 8.956  ;
; CONFIG[5]    ; RAM_DATA[0]  ; 8.062 ; 8.043 ; 8.755  ; 9.221  ;
; CONFIG[5]    ; RAM_DATA[1]  ; 8.564 ; 8.175 ; 8.953  ; 9.586  ;
; CONFIG[5]    ; RAM_DATA[2]  ; 8.627 ; 8.565 ; 9.250  ; 9.739  ;
; CONFIG[5]    ; RAM_DATA[3]  ; 9.118 ; 8.765 ; 9.395  ; 10.206 ;
; CONFIG[5]    ; RAM_DATA[4]  ; 8.557 ; 8.348 ; 9.064  ; 9.625  ;
; CONFIG[5]    ; RAM_DATA[5]  ; 9.150 ; 8.918 ; 9.908  ; 9.926  ;
; CONFIG[5]    ; RAM_DATA[6]  ; 8.527 ; 8.556 ; 9.222  ; 9.562  ;
; CONFIG[5]    ; RAM_DATA[7]  ; 8.239 ; 8.189 ; 8.928  ; 9.250  ;
; CONFIG[5]    ; RAM_DATA[8]  ; 8.946 ; 8.647 ; 9.323  ; 10.142 ;
; CONFIG[5]    ; RAM_DATA[9]  ; 8.598 ; 8.625 ; 9.378  ; 9.856  ;
; CONFIG[5]    ; RAM_DATA[10] ; 7.973 ; 8.025 ; 8.772  ; 9.140  ;
; CONFIG[5]    ; RAM_DATA[11] ; 8.142 ; 8.039 ; 8.793  ; 9.091  ;
; CONFIG[5]    ; RAM_DATA[12] ; 8.407 ; 8.101 ; 8.812  ; 9.497  ;
; CONFIG[5]    ; RAM_DATA[13] ; 7.812 ; 7.831 ; 8.617  ; 8.628  ;
; CONFIG[5]    ; RAM_DATA[14] ; 8.561 ; 8.685 ; 9.447  ; 9.571  ;
; CONFIG[5]    ; RAM_DATA[15] ; 8.157 ; 8.242 ; 8.954  ; 9.016  ;
; CONFIG[6]    ; ADR[19]      ; 4.777 ;       ;        ; 5.625  ;
; DATA[0]      ; RAM_DATA[0]  ; 5.574 ;       ;        ; 6.597  ;
; DATA[1]      ; RAM_DATA[1]  ; 5.467 ;       ;        ; 6.464  ;
; DATA[2]      ; RAM_DATA[2]  ; 6.014 ;       ;        ; 7.046  ;
; DATA[3]      ; RAM_DATA[3]  ; 6.250 ;       ;        ; 7.337  ;
; DATA[4]      ; RAM_DATA[4]  ; 5.864 ;       ;        ; 6.838  ;
; DATA[5]      ; RAM_DATA[5]  ; 6.741 ;       ;        ; 7.489  ;
; DATA[6]      ; RAM_DATA[6]  ; 5.995 ;       ;        ; 7.076  ;
; DATA[7]      ; RAM_DATA[7]  ; 5.628 ;       ;        ; 6.663  ;
; DATA[8]      ; RAM_DATA[8]  ; 5.869 ;       ;        ; 6.882  ;
; DATA[9]      ; RAM_DATA[9]  ; 6.168 ;       ;        ; 7.227  ;
; DATA[10]     ; RAM_DATA[10] ; 5.571 ;       ;        ; 6.554  ;
; DATA[11]     ; RAM_DATA[11] ; 5.618 ;       ;        ; 6.550  ;
; DATA[12]     ; RAM_DATA[12] ; 6.950 ;       ;        ; 8.113  ;
; DATA[13]     ; RAM_DATA[13] ; 5.679 ;       ;        ; 6.675  ;
; DATA[14]     ; RAM_DATA[14] ; 6.203 ;       ;        ; 7.201  ;
; DATA[15]     ; RAM_DATA[15] ; 5.878 ;       ;        ; 6.902  ;
; RAM_DATA[0]  ; RAM_DATA[0]  ; 7.466 ;       ;        ; 8.617  ;
; RAM_DATA[1]  ; RAM_DATA[1]  ; 7.561 ;       ;        ; 8.727  ;
; RAM_DATA[2]  ; RAM_DATA[2]  ; 8.335 ;       ;        ; 9.540  ;
; RAM_DATA[3]  ; RAM_DATA[3]  ; 8.397 ;       ;        ; 9.618  ;
; RAM_DATA[4]  ; RAM_DATA[4]  ; 7.524 ;       ;        ; 8.648  ;
; RAM_DATA[5]  ; RAM_DATA[5]  ; 8.452 ;       ;        ; 9.274  ;
; RAM_DATA[6]  ; RAM_DATA[6]  ; 7.429 ;       ;        ; 8.565  ;
; RAM_DATA[7]  ; RAM_DATA[7]  ; 7.428 ;       ;        ; 8.582  ;
; RAM_DATA[8]  ; RAM_DATA[8]  ; 7.965 ;       ;        ; 9.149  ;
; RAM_DATA[9]  ; RAM_DATA[9]  ; 8.728 ;       ;        ; 10.034 ;
; RAM_DATA[10] ; RAM_DATA[10] ; 7.022 ;       ;        ; 8.072  ;
; RAM_DATA[11] ; RAM_DATA[11] ; 7.126 ;       ;        ; 8.182  ;
; RAM_DATA[12] ; RAM_DATA[12] ; 6.678 ;       ;        ; 7.709  ;
; RAM_DATA[13] ; RAM_DATA[13] ; 6.174 ; 6.286 ; 7.006  ; 7.111  ;
; RAM_DATA[14] ; RAM_DATA[14] ; 7.207 ; 7.331 ; 8.057  ; 8.181  ;
; RAM_DATA[15] ; RAM_DATA[15] ; 8.418 ; 8.518 ; 9.483  ; 9.583  ;
; RESET_COREn  ; RAM_CKE      ; 2.449 ;       ;        ; 2.878  ;
; RESETn       ; KEYB_TxD     ; 4.667 ; 4.667 ; 5.735  ; 5.603  ;
+--------------+--------------+-------+-------+--------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin                ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; ADR[1]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[2]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[3]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[4]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[5]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[6]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[7]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[8]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[9]             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[10]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[11]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[12]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[13]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[14]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[15]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[16]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[17]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[18]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[19]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[20]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[21]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ADR[22]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_CLK            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_CKE            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_RASn           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_CASn           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DQMH           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DQML           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_WEn            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[4]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[5]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[6]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[7]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[8]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[9]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[10]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[11]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_ADR[12]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_BA[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_BA[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VDAC_CLK           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_R[4]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_R[5]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_R[6]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_R[7]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_G[4]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_G[5]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_G[6]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_G[7]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_B[4]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_B[5]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_B[6]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CRT_B[7]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; KEYB_TxD           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DS1392_SCL         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DS1392_CE          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; FLASH_WEn          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; FLASH_OEn          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; FLASH_CEn          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_SCLK           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_SYNCn          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_SDATA          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DAC_LDACn          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED3               ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED2               ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; LED1               ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; JOY_DIS            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDC_PWRn           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DRIVES_BSYn        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; BOOT_REQ           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RESETn             ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[0]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[1]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[2]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[3]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[4]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[5]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[6]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[7]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[8]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[9]            ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[10]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[11]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[12]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[13]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[14]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DATA[15]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; RAM_DATA[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; HSYNC              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VSYNC              ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; DS1392_D           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDC_SPI_CLK        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; MOSI               ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; MISO               ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDC_D[1]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDC_D[2]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDC_D[3]           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_INIT_DONE~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; JOY_A5                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RESETn                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[0]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[1]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[2]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[3]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[4]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[5]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[6]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[7]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[8]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[9]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[10]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[11]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[12]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[13]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[14]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DATA[15]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[0]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[1]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[2]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[3]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[4]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[5]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[6]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[7]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[8]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[9]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[10]            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[11]            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[12]            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[13]            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[14]            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RAM_DATA[15]            ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; HSYNC                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; VSYNC                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; DS1392_D                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDC_SPI_CLK             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; MOSI                    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; MISO                    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDC_D[1]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDC_D[2]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDC_D[3]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONFIG[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONFIG[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONFIG[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONFIG[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; RESET_COREn             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; FLASH_RDY               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLK_PLL1                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONFIG[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CONFIG[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDC_CDn                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; JOY_A2                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; BOOT_ACK                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; CLK_PLL2                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDC_WP                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; KEYB_RxD                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; ADR[1]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[2]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[3]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[4]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[5]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[6]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[7]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[8]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[9]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[10]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[11]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[12]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; ADR[13]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[14]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[15]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[16]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[17]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[18]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[19]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[20]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[21]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ADR[22]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_CLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_CKE            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_RASn           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_CASn           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_DQMH           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_DQML           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_WEn            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[4]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[5]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[6]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[7]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[8]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; RAM_ADR[9]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[10]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[11]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_ADR[12]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_BA[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_BA[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; VDAC_CLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; CRT_R[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_R[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_R[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_R[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_G[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; CRT_G[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_G[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_G[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_B[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; CRT_B[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; CRT_B[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; CRT_B[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; KEYB_TxD           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DS1392_SCL         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DS1392_CE          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; FLASH_WEn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; FLASH_OEn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; FLASH_CEn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DAC_SCLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; DAC_SYNCn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; DAC_SDATA          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; DAC_LDACn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; LED3               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; LED2               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; LED1               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; JOY_DIS            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDC_PWRn           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; DRIVES_BSYn        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; BOOT_REQ           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RESETn             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; DATA[0]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[1]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[2]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[3]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[4]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[5]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.08 V              ; -0.00526 V          ; 0.185 V                              ; 0.249 V                              ; 5.8e-09 s                   ; 4.45e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.47e-07 V                  ; 3.08 V             ; -0.00526 V         ; 0.185 V                             ; 0.249 V                             ; 5.8e-09 s                  ; 4.45e-09 s                 ; Yes                       ; Yes                       ;
; DATA[6]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[7]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[8]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[9]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[10]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[11]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[12]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[13]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[14]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; DATA[15]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; RAM_DATA[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; RAM_DATA[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; RAM_DATA[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.08 V              ; -0.00545 V          ; 0.234 V                              ; 0.291 V                              ; 5.77e-09 s                  ; 4.44e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 5.01e-07 V                  ; 3.08 V             ; -0.00545 V         ; 0.234 V                             ; 0.291 V                             ; 5.77e-09 s                 ; 4.44e-09 s                 ; Yes                       ; Yes                       ;
; RAM_DATA[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; RAM_DATA[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; HSYNC              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; VSYNC              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; DS1392_D           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDC_SPI_CLK        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; MOSI               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
; MISO               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0671 V           ; 0.235 V                              ; 0.176 V                              ; 6.85e-10 s                  ; 6.31e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0671 V          ; 0.235 V                             ; 0.176 V                             ; 6.85e-10 s                 ; 6.31e-10 s                 ; Yes                       ; No                        ;
; SDC_D[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDC_D[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; SDC_D[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.47e-07 V                   ; 3.11 V              ; -0.0527 V           ; 0.256 V                              ; 0.175 V                              ; 7.07e-10 s                  ; 6.42e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 7.47e-07 V                  ; 3.11 V             ; -0.0527 V          ; 0.256 V                             ; 0.175 V                             ; 7.07e-10 s                 ; 6.42e-10 s                 ; Yes                       ; No                        ;
; ~ALTERA_DCLK~      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.58e-07 V                   ; 3.13 V              ; -0.0964 V           ; 0.164 V                              ; 0.127 V                              ; 3.14e-10 s                  ; 3.99e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.58e-07 V                  ; 3.13 V             ; -0.0964 V          ; 0.164 V                             ; 0.127 V                             ; 3.14e-10 s                 ; 3.99e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_INIT_DONE~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.01e-07 V                   ; 3.11 V              ; -0.0488 V           ; 0.191 V                              ; 0.217 V                              ; 1.08e-09 s                  ; 8.59e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 5.01e-07 V                  ; 3.11 V             ; -0.0488 V          ; 0.191 V                             ; 0.217 V                             ; 1.08e-09 s                 ; 8.59e-10 s                 ; No                        ; No                        ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; ADR[1]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[2]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[3]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[4]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[5]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[6]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[7]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[8]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[9]             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[10]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[11]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[12]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; ADR[13]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[14]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[15]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[16]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[17]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[18]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[19]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[20]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[21]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ADR[22]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_CLK            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_CKE            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_RASn           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_CASn           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_DQMH           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_DQML           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_WEn            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[4]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[5]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[6]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[7]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[8]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; RAM_ADR[9]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[10]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[11]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_ADR[12]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_BA[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_BA[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; VDAC_CLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; CRT_R[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_R[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_R[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_R[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_G[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; CRT_G[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_G[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_G[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_B[4]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; CRT_B[5]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; CRT_B[6]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; CRT_B[7]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; KEYB_TxD           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DS1392_SCL         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DS1392_CE          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; FLASH_WEn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; FLASH_OEn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; FLASH_CEn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DAC_SCLK           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DAC_SYNCn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; DAC_SDATA          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DAC_LDACn          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; LED3               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; LED2               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; LED1               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; JOY_DIS            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDC_PWRn           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DRIVES_BSYn        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; BOOT_REQ           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RESETn             ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; DATA[0]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[1]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[2]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[3]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[4]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[5]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.48 V              ; -0.0176 V           ; 0.357 V                              ; 0.323 V                              ; 3.9e-09 s                   ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.48 V             ; -0.0176 V          ; 0.357 V                             ; 0.323 V                             ; 3.9e-09 s                  ; 3.06e-09 s                 ; No                        ; No                        ;
; DATA[6]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[7]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[8]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[9]            ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[10]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[11]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[12]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[13]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[14]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; DATA[15]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; RAM_DATA[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; RAM_DATA[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; RAM_DATA[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.48 V              ; -0.0164 V           ; 0.353 V                              ; 0.315 V                              ; 3.88e-09 s                  ; 3.06e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.48 V             ; -0.0164 V          ; 0.353 V                             ; 0.315 V                             ; 3.88e-09 s                 ; 3.06e-09 s                 ; No                        ; No                        ;
; RAM_DATA[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; RAM_DATA[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; HSYNC              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; VSYNC              ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; DS1392_D           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDC_SPI_CLK        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; MOSI               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
; MISO               ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.6 V               ; -0.129 V            ; 0.303 V                              ; 0.209 V                              ; 4.54e-10 s                  ; 4.11e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.6 V              ; -0.129 V           ; 0.303 V                             ; 0.209 V                             ; 4.54e-10 s                 ; 4.11e-10 s                 ; No                        ; No                        ;
; SDC_D[1]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDC_D[2]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; SDC_D[3]           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.83e-07 V                   ; 3.58 V              ; -0.143 V            ; 0.305 V                              ; 0.24 V                               ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.83e-07 V                  ; 3.58 V             ; -0.143 V           ; 0.305 V                             ; 0.24 V                              ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; No                        ;
; ~ALTERA_DCLK~      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.53e-08 V                   ; 3.65 V              ; -0.246 V            ; 0.406 V                              ; 0.305 V                              ; 1.57e-10 s                  ; 2.13e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.53e-08 V                  ; 3.65 V             ; -0.246 V           ; 0.406 V                             ; 0.305 V                             ; 1.57e-10 s                 ; 2.13e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_INIT_DONE~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.24e-07 V                   ; 3.57 V              ; -0.0876 V           ; 0.318 V                              ; 0.176 V                              ; 6.78e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.24e-07 V                  ; 3.57 V             ; -0.0876 V          ; 0.318 V                             ; 0.176 V                             ; 6.78e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                                                                     ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+----------+--------------+----------+
; From Clock                                                                                             ; To Clock                                                                                               ; RR Paths     ; FR Paths ; RF Paths     ; FF Paths ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+----------+--------------+----------+
; CLK_PLL1                                                                                               ; CLK_PLL1                                                                                               ; 46           ; 0        ; 0            ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; false path   ; 0        ; false path   ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 338785401    ; 12443561 ; 11072317     ; 414632   ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 3510559      ; 11       ; 114551       ; 1        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; > 2147483647 ; 16306464 ; > 2147483647 ; 530679   ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 3088         ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1            ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 80           ; 0        ; 0            ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; false path   ; 0        ; false path   ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 33665616     ; 1249281  ; 10665        ; 466      ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 11909713     ; 3        ; 60           ; 2        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; > 2147483647 ; 1748223  ; 25600102     ; 114      ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 3311         ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 11           ; 0        ; 0            ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; false path   ; 0        ; false path   ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 1729944      ; 58496    ; 50154047     ; 1827446  ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15441        ; 85       ; 513136       ; 294      ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; > 2147483647 ; 63023    ; > 2147483647 ; 2335155  ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; false path   ; 0        ; 0            ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 25449        ; 0        ; 0            ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 15134        ; 0        ; 0            ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 154464       ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 3            ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 10           ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 18           ; 0        ; 0            ; 0        ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+----------+--------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                                                                      ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+----------+--------------+----------+
; From Clock                                                                                             ; To Clock                                                                                               ; RR Paths     ; FR Paths ; RF Paths     ; FF Paths ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+----------+--------------+----------+
; CLK_PLL1                                                                                               ; CLK_PLL1                                                                                               ; 46           ; 0        ; 0            ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; false path   ; 0        ; false path   ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 338785401    ; 12443561 ; 11072317     ; 414632   ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 3510559      ; 11       ; 114551       ; 1        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; > 2147483647 ; 16306464 ; > 2147483647 ; 530679   ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 3088         ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 1            ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 80           ; 0        ; 0            ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; false path   ; 0        ; false path   ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 33665616     ; 1249281  ; 10665        ; 466      ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 11909713     ; 3        ; 60           ; 2        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; > 2147483647 ; 1748223  ; 25600102     ; 114      ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 3311         ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 11           ; 0        ; 0            ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; false path   ; 0        ; false path   ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 1729944      ; 58496    ; 50154047     ; 1827446  ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 15441        ; 85       ; 513136       ; 294      ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; > 2147483647 ; 63023    ; > 2147483647 ; 2335155  ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; false path   ; 0        ; 0            ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 25449        ; 0        ; 0            ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 15134        ; 0        ; 0            ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] ; 154464       ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] ; 3            ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] ; 10           ; 0        ; 0            ; 0        ;
; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] ; 18           ; 0        ; 0            ; 0        ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------+----------+--------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                                                             ; To Clock                                                                                               ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; false path ; 0        ; false path ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 13726      ; 0        ; 612        ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 17808      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; false path ; 0        ; 0          ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 6909       ; 0        ; 0          ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 9192       ; 0        ; 0          ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0          ; 5        ; 0          ; 0        ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                                                               ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                                                             ; To Clock                                                                                               ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; false path ; 0        ; false path ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 13726      ; 0        ; 612        ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; 17808      ; 0        ; 816        ; 0        ;
; CLK_PLL1                                                                                               ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; false path ; 0        ; 0          ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 6909       ; 0        ; 0          ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] ; 9192       ; 0        ; 0          ; 0        ;
; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] ; 0          ; 5        ; 0          ; 0        ;
+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+-------------------------------------------------+
; Unconstrained Paths                             ;
+---------------------------------+-------+-------+
; Property                        ; Setup ; Hold  ;
+---------------------------------+-------+-------+
; Illegal Clocks                  ; 0     ; 0     ;
; Unconstrained Clocks            ; 0     ; 0     ;
; Unconstrained Input Ports       ; 54    ; 54    ;
; Unconstrained Input Port Paths  ; 9065  ; 9065  ;
; Unconstrained Output Ports      ; 114   ; 114   ;
; Unconstrained Output Port Paths ; 13816 ; 13816 ;
+---------------------------------+-------+-------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
    Info: Processing started: Wed Dec 15 10:42:03 2021
Info: Command: quartus_sta SUSKA-III-B -c SUSKA-III-B
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: '../../../rtl/vhdl/SUSKA-III-B/suska_cycloneIII_core_b.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0]} {I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1]} {I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2]} {I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {I_SYSCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 3 -duty_cycle 50.00 -name {cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3]} {I_SYSCLOCKS|altpll_component|auto_generated|pll1|clk[3]}
    Info (332110): create_generated_clock -source {I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50.00 -name {cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0]} {I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 13 -multiply_by 32 -duty_cycle 50.00 -name {cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1]} {I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {I_AUXCLOCKS|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2]} {I_AUXCLOCKS|altpll_component|auto_generated|pll1|clk[2]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.791
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -4.791              -9.171 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    -0.538              -2.526 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.245               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.593               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):    22.763               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    38.089               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    59.852               0.000 CLK_PLL1 
    Info (332119):    60.288               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case hold slack is 0.079
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.079               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.433               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.434               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.434               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):     0.435               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.455               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.467               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.485               0.000 CLK_PLL1 
Info (332146): Worst-case recovery slack is 21.548
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    21.548               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    21.593               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    27.749               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case removal slack is 1.701
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     1.701               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     4.065               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    33.361               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case minimum pulse width slack is 12.384
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    12.384               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    15.295               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    19.218               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    20.498               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):    30.806               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    30.920               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    30.932               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    31.009               0.000 CLK_PLL1 
    Info (332119):    31.107               0.000 CLK_PLL2 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.440
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -3.440              -6.498 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.403               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     1.133               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):     1.209               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    23.009               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    38.178               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    60.067               0.000 CLK_PLL1 
    Info (332119):    60.479               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case hold slack is 0.076
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.076               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.383               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.383               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):     0.384               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.384               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.403               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.417               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.449               0.000 CLK_PLL1 
Info (332146): Worst-case recovery slack is 22.313
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    22.313               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    22.339               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    28.005               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case removal slack is 1.530
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     1.530               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     3.671               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    33.125               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case minimum pulse width slack is 12.386
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    12.386               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    15.268               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    19.223               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    20.480               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):    30.819               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    30.888               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    30.895               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    31.007               0.000 CLK_PLL1 
    Info (332119):    31.082               0.000 CLK_PLL2 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 1.138
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     1.138               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     5.920               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     5.939               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):     9.574               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    24.280               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    38.640               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    61.387               0.000 CLK_PLL1 
    Info (332119):    61.546               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case hold slack is -0.128
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.128              -0.128 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.088               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.179               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.179               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):     0.180               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):     0.188               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     0.195               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):     0.198               0.000 CLK_PLL1 
Info (332146): Worst-case recovery slack is 26.812
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    26.812               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    26.874               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    29.695               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case removal slack is 0.720
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.720               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):     1.791               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    32.179               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
Info (332146): Worst-case minimum pulse width slack is 12.476
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    12.476               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    15.370               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[1] 
    Info (332119):    19.312               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    20.616               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[3] 
    Info (332119):    30.520               0.000 CLK_PLL1 
    Info (332119):    30.656               0.000 CLK_PLL2 
    Info (332119):    30.990               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[2] 
    Info (332119):    30.992               0.000 cyclone_pll_1:I_SYSCLOCKS|altpll:altpll_component|cyclone_pll_1_altpll:auto_generated|wire_pll1_clk[0] 
    Info (332119):    31.032               0.000 cyclone_pll_2:I_AUXCLOCKS|altpll:altpll_component|cyclone_pll_2_altpll:auto_generated|wire_pll1_clk[2] 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 5017 megabytes
    Info: Processing ended: Wed Dec 15 10:42:25 2021
    Info: Elapsed time: 00:00:22
    Info: Total CPU time (on all processors): 00:00:28


