TimeQuest Timing Analyzer report for SUSKA-III-C
Thu Dec 09 18:30:37 2021
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow Model Fmax Summary
  7. Slow Model Setup Summary
  8. Slow Model Hold Summary
  9. Slow Model Recovery Summary
 10. Slow Model Removal Summary
 11. Slow Model Minimum Pulse Width Summary
 12. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 13. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 14. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 15. Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 16. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 17. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 18. Slow Model Setup: 'CLK_PLL1'
 19. Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 20. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 21. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 22. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 23. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 24. Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 25. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 26. Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 27. Slow Model Hold: 'CLK_PLL1'
 28. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 29. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 30. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 31. Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 32. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 33. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 34. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 35. Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 36. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 37. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 38. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 39. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 40. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 41. Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 42. Slow Model Minimum Pulse Width: 'CLK_PLL1'
 43. Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 44. Slow Model Minimum Pulse Width: 'CLK_PLL2'
 45. Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
 46. Slow Model Minimum Pulse Width: 'altera_reserved_tck'
 47. Setup Times
 48. Hold Times
 49. Clock to Output Times
 50. Minimum Clock to Output Times
 51. Propagation Delay
 52. Minimum Propagation Delay
 53. Output Enable Times
 54. Minimum Output Enable Times
 55. Output Disable Times
 56. Minimum Output Disable Times
 57. Fast Model Setup Summary
 58. Fast Model Hold Summary
 59. Fast Model Recovery Summary
 60. Fast Model Removal Summary
 61. Fast Model Minimum Pulse Width Summary
 62. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 63. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 64. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 65. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 66. Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 67. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 68. Fast Model Setup: 'CLK_PLL1'
 69. Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 70. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 71. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 72. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 73. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 74. Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 75. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 76. Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 77. Fast Model Hold: 'CLK_PLL1'
 78. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 79. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 80. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 81. Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 82. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 83. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 84. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 85. Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 86. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'
 87. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'
 88. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'
 89. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'
 90. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'
 91. Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'
 92. Fast Model Minimum Pulse Width: 'CLK_PLL1'
 93. Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'
 94. Fast Model Minimum Pulse Width: 'CLK_PLL2'
 95. Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'
 96. Fast Model Minimum Pulse Width: 'altera_reserved_tck'
 97. Setup Times
 98. Hold Times
 99. Clock to Output Times
100. Minimum Clock to Output Times
101. Propagation Delay
102. Minimum Propagation Delay
103. Output Enable Times
104. Minimum Output Enable Times
105. Output Disable Times
106. Minimum Output Disable Times
107. Multicorner Timing Analysis Summary
108. Setup Times
109. Hold Times
110. Clock to Output Times
111. Minimum Clock to Output Times
112. Progagation Delay
113. Minimum Progagation Delay
114. Setup Transfers
115. Hold Transfers
116. Recovery Transfers
117. Removal Transfers
118. Report TCCS
119. Report RSKM
120. Unconstrained Paths
121. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                    ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition ;
; Revision Name      ; SUSKA-III-C                                                     ;
; Device Family      ; Cyclone II                                                      ;
; Device Name        ; EP2C35F484C7                                                    ;
; Timing Models      ; Final                                                           ;
; Delay Model        ; Combined                                                        ;
; Rise/Fall Delays   ; Unavailable                                                     ;
+--------------------+-----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------+
; SDC File List                                                                                     ;
+---------------------------------------------------------------+--------+--------------------------+
; SDC File Path                                                 ; Status ; Read at                  ;
+---------------------------------------------------------------+--------+--------------------------+
; ../../../rtl/vhdl/Suska-III-C/suska_cycloneII_core_falcon.sdc ; OK     ; Thu Dec 09 18:29:54 2021 ;
+---------------------------------------------------------------+--------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                              ;
+------------------------------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; Clock Name                                                 ; Type      ; Period  ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master        ; Source                                    ; Targets                                     ;
+------------------------------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+
; altera_reserved_tck                                        ; Base      ; 100.000 ; 10.0 MHz  ; 0.000 ; 50.000 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { altera_reserved_tck }                     ;
; CLK_PLL1                                                   ; Base      ; 62.500  ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL1 }                                ;
; CLK_PLL2                                                   ; Base      ; 62.500  ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CLK_PLL2 }                                ;
; CRT_PIN4_CLK1                                              ; Base      ; 62.500  ; 16.0 MHz  ; 0.000 ; 31.250 ;            ;           ;             ;       ;        ;           ;            ;          ;               ;                                           ; { CRT_PIN4_CLK1 }                           ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 62.500  ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Generated ; 62.500  ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 31.250  ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CLK_PLL1      ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Generated ; 31.250  ; 32.0 MHz  ; 0.000 ; 15.625 ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; CRT_PIN4_CLK1 ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ; { I_SYSCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; Generated ; 39.062  ; 25.6 MHz  ; 0.000 ; 19.531 ; 50.00      ; 5         ; 8           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[0] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; Generated ; 25.390  ; 39.39 MHz ; 0.000 ; 12.695 ; 50.00      ; 13        ; 32          ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[1] } ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; Generated ; 62.500  ; 16.0 MHz  ; 0.000 ; 31.250 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLK_PLL2      ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ; { I_AUXCLOCKS|altpll_component|pll|clk[2] } ;
+------------------------------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------+-------------------------------------------+---------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+------------------------------------------------------------+---------------------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                 ; Note                                                          ;
+------------+-----------------+------------------------------------------------------------+---------------------------------------------------------------+
; 11.95 MHz  ; 11.95 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;                                                               ;
; 11.95 MHz  ; 11.95 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;                                                               ;
; 30.88 MHz  ; 30.88 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;                                                               ;
; 30.88 MHz  ; 30.88 MHz       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;                                                               ;
; 81.02 MHz  ; 81.02 MHz       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;                                                               ;
; 108.86 MHz ; 108.86 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ;                                                               ;
; 384.32 MHz ; 380.08 MHz      ; CLK_PLL1                                                   ; limit due to minimum period restriction (max I/O toggle rate) ;
; 796.81 MHz ; 450.05 MHz      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; limit due to high minimum pulse width violation (tch)         ;
+------------+-----------------+------------------------------------------------------------+---------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------+
; Slow Model Setup Summary                                                             ;
+------------------------------------------------------------+---------+---------------+
; Clock                                                      ; Slack   ; End Point TNS ;
+------------------------------------------------------------+---------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -12.133 ; -8599.655     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -12.133 ; -8599.655     ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -11.466 ; -12013.941    ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -11.466 ; -12013.941    ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; -3.911  ; -369.126      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; -1.381  ; -500.405      ;
; CLK_PLL1                                                   ; 59.898  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 61.245  ; 0.000         ;
+------------------------------------------------------------+---------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Hold Summary                                                             ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -3.460 ; -746.183      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -3.460 ; -746.183      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; -3.079 ; -514.643      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -2.006 ; -112.700      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -2.006 ; -112.700      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.445  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.445  ; 0.000         ;
; CLK_PLL1                                                   ; 0.912  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 21.924 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 21.924 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 28.501 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 28.501 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Slow Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 2.146 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 2.146 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 2.912 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 2.912 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10.131 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.061 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.061 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.420 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 28.943 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 28.943 ; 0.000         ;
; CLK_PLL1                                                   ; 30.139 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.139 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; altera_reserved_tck                                        ; 97.531 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                       ;
+---------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -12.133 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.045     ; 15.940     ;
; -12.108 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.034     ; 15.926     ;
; -11.987 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 15.797     ;
; -11.960 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.043     ; 15.769     ;
; -11.959 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.060     ; 15.751     ;
; -11.935 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSCROLL[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.035     ; 15.752     ;
; -11.851 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.022     ; 15.681     ;
; -11.799 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.052     ; 15.599     ;
; -11.654 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[17] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.046     ; 15.460     ;
; -11.567 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.022     ; 15.397     ;
; -11.558 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.051     ; 15.359     ;
; -11.548 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.051     ; 15.349     ;
; -11.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.040     ; 15.357     ;
; -11.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.040     ; 15.357     ;
; -11.536 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHT[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.030     ; 15.358     ;
; -11.535 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[1]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.050     ; 15.337     ;
; -11.522 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_F[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 15.332     ;
; -11.496 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.047     ; 15.301     ;
; -11.473 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|DMA_CONTROL[1]           ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 15.288     ;
; -11.469 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.022     ; 15.299     ;
; -11.465 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.048     ; 15.269     ;
; -11.464 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[25]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.029     ; 15.287     ;
; -11.455 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[25]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.048     ; 15.259     ;
; -11.449 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[0][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.031     ; 15.270     ;
; -11.441 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[15][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.033     ; 15.260     ;
; -11.416 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[8][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.020     ; 15.248     ;
; -11.401 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[1]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.051     ; 15.202     ;
; -11.363 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 15.173     ;
; -11.356 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[17]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.052     ; 15.156     ;
; -11.328 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[1][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.026     ; 15.154     ;
; -11.263 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[9]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.055     ; 15.060     ;
; -11.245 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[9][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.013     ; 15.084     ;
; -11.221 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.034     ; 15.039     ;
; -11.213 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.036     ; 15.029     ;
; -11.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.036     ; 15.027     ;
; -11.204 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.534     ;
; -11.204 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.534     ;
; -11.202 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[7][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.028     ; 15.026     ;
; -11.201 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.531     ;
; -11.201 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.531     ;
; -11.199 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[6][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.028     ; 15.023     ;
; -11.199 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.034     ; 15.017     ;
; -11.197 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[12][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.034     ; 15.015     ;
; -11.176 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[2][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.024     ; 15.004     ;
; -11.172 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[4][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.024     ; 15.000     ;
; -11.164 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[25]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.047     ; 14.969     ;
; -11.152 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.050     ; 14.954     ;
; -11.146 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.476     ;
; -11.146 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.476     ;
; -11.143 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.473     ;
; -11.143 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.473     ;
; -11.136 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_ST[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.023     ; 14.965     ;
; -11.131 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.055     ; 14.928     ;
; -11.125 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 14.940     ;
; -11.124 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 14.939     ;
; -11.121 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.043     ; 14.930     ;
; -11.119 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[241]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.038     ; 14.933     ;
; -11.107 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_MICROWIRE:I_MICROWIRE|GPx_EN_REG[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.043     ; 14.916     ;
; -11.100 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[17]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 14.910     ;
; -11.084 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[11][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.016     ; 14.920     ;
; -11.083 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|FREQ_DIV_INT[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.041     ; 14.894     ;
; -11.082 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 14.892     ;
; -11.079 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[10][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.016     ; 14.915     ;
; -11.078 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.060     ; 14.870     ;
; -11.071 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 14.886     ;
; -11.065 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.060     ; 14.857     ;
; -11.063 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.045     ; 14.870     ;
; -11.061 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|SMODE_CTRL[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.021     ; 14.892     ;
; -11.029 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[17]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.047     ; 14.834     ;
; -11.025 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[3][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.030     ; 14.847     ;
; -11.025 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[5][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.031     ; 14.846     ;
; -11.008 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.027     ; 14.833     ;
; -11.002 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.070     ; 14.784     ;
; -11.000 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 14.815     ;
; -10.981 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.075     ; 14.758     ;
; -10.979 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|BUFF_INT[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.026     ; 14.805     ;
; -10.977 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[9]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.026     ; 14.803     ;
; -10.934 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[4]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.044     ; 14.742     ;
; -10.928 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.080     ; 14.700     ;
; -10.921 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.057     ; 14.716     ;
; -10.912 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|INTERLACED_EN  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.039     ; 14.725     ;
; -10.889 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[11][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.018     ; 14.723     ;
; -10.889 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[12][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.018     ; 14.723     ;
; -10.881 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.015     ; 14.718     ;
; -10.879 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[15][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.015     ; 14.716     ;
; -10.861 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.050     ; 14.663     ;
; -10.860 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.190     ;
; -10.860 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.190     ;
; -10.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.187     ;
; -10.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; 0.042      ; 42.187     ;
; -10.843 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.048     ; 14.647     ;
; -10.840 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.047     ; 14.645     ;
; -10.820 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_DEST[1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.039     ; 14.633     ;
; -10.810 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[8]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 14.620     ;
; -10.809 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[16]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.042     ; 14.619     ;
; -10.799 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[24]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.050     ; 14.601     ;
; -10.799 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[204]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.038     ; 14.613     ;
; -10.795 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[240]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.038     ; 14.609     ;
; -10.789 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[0]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 14.604     ;
; -10.788 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -4.037     ; 14.603     ;
+---------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                                                       ;
+---------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -12.133 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.045     ; 15.940     ;
; -12.108 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.034     ; 15.926     ;
; -11.987 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 15.797     ;
; -11.960 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.043     ; 15.769     ;
; -11.959 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.060     ; 15.751     ;
; -11.935 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSCROLL[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.035     ; 15.752     ;
; -11.851 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.022     ; 15.681     ;
; -11.799 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.052     ; 15.599     ;
; -11.654 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[17] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.046     ; 15.460     ;
; -11.567 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.022     ; 15.397     ;
; -11.558 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.051     ; 15.359     ;
; -11.548 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.051     ; 15.349     ;
; -11.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.040     ; 15.357     ;
; -11.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.040     ; 15.357     ;
; -11.536 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHT[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.030     ; 15.358     ;
; -11.535 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[1]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.050     ; 15.337     ;
; -11.522 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_F[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 15.332     ;
; -11.496 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.047     ; 15.301     ;
; -11.473 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|DMA_CONTROL[1]           ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 15.288     ;
; -11.469 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.022     ; 15.299     ;
; -11.465 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.048     ; 15.269     ;
; -11.464 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[25]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.029     ; 15.287     ;
; -11.455 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[25]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.048     ; 15.259     ;
; -11.449 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[0][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.031     ; 15.270     ;
; -11.441 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[15][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.033     ; 15.260     ;
; -11.416 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[8][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.020     ; 15.248     ;
; -11.401 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[1]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.051     ; 15.202     ;
; -11.363 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 15.173     ;
; -11.356 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[17]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.052     ; 15.156     ;
; -11.328 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[1][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.026     ; 15.154     ;
; -11.263 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[9]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.055     ; 15.060     ;
; -11.245 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[9][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.013     ; 15.084     ;
; -11.221 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.034     ; 15.039     ;
; -11.213 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.036     ; 15.029     ;
; -11.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.036     ; 15.027     ;
; -11.204 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.534     ;
; -11.204 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.534     ;
; -11.202 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[7][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.028     ; 15.026     ;
; -11.201 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.531     ;
; -11.201 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.531     ;
; -11.199 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[6][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.028     ; 15.023     ;
; -11.199 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.034     ; 15.017     ;
; -11.197 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[12][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.034     ; 15.015     ;
; -11.176 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[2][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.024     ; 15.004     ;
; -11.172 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[4][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.024     ; 15.000     ;
; -11.164 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[25]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.047     ; 14.969     ;
; -11.152 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.050     ; 14.954     ;
; -11.146 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.476     ;
; -11.146 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.476     ;
; -11.143 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.473     ;
; -11.143 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.473     ;
; -11.136 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_ST[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.023     ; 14.965     ;
; -11.131 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.055     ; 14.928     ;
; -11.125 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 14.940     ;
; -11.124 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 14.939     ;
; -11.121 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.043     ; 14.930     ;
; -11.119 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[241]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.038     ; 14.933     ;
; -11.107 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_MICROWIRE:I_MICROWIRE|GPx_EN_REG[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.043     ; 14.916     ;
; -11.100 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[17]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 14.910     ;
; -11.084 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[11][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.016     ; 14.920     ;
; -11.083 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|FREQ_DIV_INT[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.041     ; 14.894     ;
; -11.082 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 14.892     ;
; -11.079 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[10][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.016     ; 14.915     ;
; -11.078 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.060     ; 14.870     ;
; -11.071 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 14.886     ;
; -11.065 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.060     ; 14.857     ;
; -11.063 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.045     ; 14.870     ;
; -11.061 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|SMODE_CTRL[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.021     ; 14.892     ;
; -11.029 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[17]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.047     ; 14.834     ;
; -11.025 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[3][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.030     ; 14.847     ;
; -11.025 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[5][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.031     ; 14.846     ;
; -11.008 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.027     ; 14.833     ;
; -11.002 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.070     ; 14.784     ;
; -11.000 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 14.815     ;
; -10.981 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.075     ; 14.758     ;
; -10.979 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|BUFF_INT[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.026     ; 14.805     ;
; -10.977 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[9]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.026     ; 14.803     ;
; -10.934 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[4]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.044     ; 14.742     ;
; -10.928 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.080     ; 14.700     ;
; -10.921 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.057     ; 14.716     ;
; -10.912 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|INTERLACED_EN  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.039     ; 14.725     ;
; -10.889 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[11][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.018     ; 14.723     ;
; -10.889 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[12][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.018     ; 14.723     ;
; -10.881 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.015     ; 14.718     ;
; -10.879 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[15][9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.015     ; 14.716     ;
; -10.861 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.050     ; 14.663     ;
; -10.860 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.190     ;
; -10.860 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.190     ;
; -10.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.187     ;
; -10.857 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[4] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; 0.042      ; 42.187     ;
; -10.843 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.048     ; 14.647     ;
; -10.840 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.047     ; 14.645     ;
; -10.820 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_DEST[1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.039     ; 14.633     ;
; -10.810 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[8]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 14.620     ;
; -10.809 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[16]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.042     ; 14.619     ;
; -10.799 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[24]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.050     ; 14.601     ;
; -10.799 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[204]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.038     ; 14.613     ;
; -10.795 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[240]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.038     ; 14.609     ;
; -10.789 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[0]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 14.604     ;
; -10.788 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -4.037     ; 14.603     ;
+---------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                 ;
+---------+----------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                  ; To Node                                                                              ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -11.466 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.048     ; 15.270     ;
; -11.427 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 15.257     ;
; -11.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.012     ; 15.086     ;
; -11.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 15.076     ;
; -11.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[0][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.011     ; 15.073     ;
; -11.144 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.048     ; 14.948     ;
; -11.127 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.040     ; 14.939     ;
; -11.125 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.040     ; 14.937     ;
; -11.083 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[9][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.019     ; 14.916     ;
; -11.069 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.018     ; 14.903     ;
; -11.067 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.018     ; 14.901     ;
; -11.065 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.026     ; 14.891     ;
; -11.056 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.018     ; 14.890     ;
; -11.046 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.046     ; 14.852     ;
; -11.044 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.046     ; 14.850     ;
; -11.031 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[6][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.036     ; 14.847     ;
; -11.031 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.048     ; 14.835     ;
; -11.030 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[7][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.036     ; 14.846     ;
; -11.026 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.015     ; 14.863     ;
; -11.024 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.015     ; 14.861     ;
; -11.016 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK1[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.020     ; 14.848     ;
; -11.015 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.020     ; 14.849     ;
; -10.999 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.014     ; 14.837     ;
; -10.999 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.014     ; 14.837     ;
; -10.994 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 14.824     ;
; -10.972 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.031     ; 14.793     ;
; -10.971 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.041     ; 14.782     ;
; -10.970 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.041     ; 14.781     ;
; -10.960 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.043     ; 14.769     ;
; -10.934 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 14.764     ;
; -10.923 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[13][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.019     ; 14.756     ;
; -10.923 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.019     ; 14.756     ;
; -10.919 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.021     ; 14.750     ;
; -10.917 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.021     ; 14.748     ;
; -10.899 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.041     ; 14.710     ;
; -10.899 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.041     ; 14.710     ;
; -10.886 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.033     ; 14.705     ;
; -10.885 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.048     ; 14.689     ;
; -10.884 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.048     ; 14.688     ;
; -10.883 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.033     ; 14.702     ;
; -10.882 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.015     ; 14.719     ;
; -10.879 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.043     ; 14.688     ;
; -10.878 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HOP[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.013     ; 14.717     ;
; -10.874 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.043     ; 14.683     ;
; -10.872 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.043     ; 14.681     ;
; -10.849 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[9]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 14.679     ;
; -10.831 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.030     ; 14.653     ;
; -10.809 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[12][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.020     ; 14.641     ;
; -10.804 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.020     ; 14.636     ;
; -10.791 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[7][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.018     ; 14.625     ;
; -10.790 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[6][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.018     ; 14.624     ;
; -10.751 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[4][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.019     ; 14.584     ;
; -10.726 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.018     ; 14.560     ;
; -10.704 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.038     ; 14.518     ;
; -10.703 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.038     ; 14.517     ;
; -10.686 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.028     ; 14.510     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.026     ; 14.508     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.026     ; 14.508     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.027     ; 14.507     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 14.512     ;
; -10.669 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[0]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.014     ; 14.507     ;
; -10.668 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_RELOAD[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.020     ; 14.500     ;
; -10.666 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.014     ; 14.504     ;
; -10.640 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.033     ; 14.459     ;
; -10.640 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.033     ; 14.459     ;
; -10.626 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.032     ; 14.446     ;
; -10.623 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.030     ; 14.445     ;
; -10.622 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.031     ; 14.443     ;
; -10.595 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[9]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 14.425     ;
; -10.588 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[2][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.021     ; 14.419     ;
; -10.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[3][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.021     ; 14.418     ;
; -10.579 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[9]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.016     ; 14.415     ;
; -10.578 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 41.913     ;
; -10.578 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 41.913     ;
; -10.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.015     ; 14.409     ;
; -10.570 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.068     ; 14.354     ;
; -10.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.030     ; 14.385     ;
; -10.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[8][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.034     ; 14.381     ;
; -10.562 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[9][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.034     ; 14.380     ;
; -10.547 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.017     ; 14.382     ;
; -10.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|REPLAY_FIFO_REG[16][1]                          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.027     ; 14.370     ;
; -10.520 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 41.855     ;
; -10.520 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 41.855     ;
; -10.515 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 14.345     ;
; -10.513 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 14.343     ;
; -10.482 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.038     ; 14.296     ;
; -10.477 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 14.307     ;
; -10.476 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.052     ; 14.276     ;
; -10.472 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.051     ; 14.273     ;
; -10.469 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -4.024     ; 14.299     ;
; -10.452 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_COUNT[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.020     ; 14.284     ;
; -10.451 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 14.281     ;
; -10.451 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[6][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.036     ; 14.267     ;
; -10.451 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[7][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.036     ; 14.267     ;
; -10.448 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 14.278     ;
; -10.447 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[8]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.022     ; 14.277     ;
; -10.444 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[11]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.060      ; 41.792     ;
; -10.444 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[11]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.060      ; 41.792     ;
; -10.434 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.026     ; 14.260     ;
; -10.432 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][8]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -4.026     ; 14.258     ;
+---------+----------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                                 ;
+---------+----------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack   ; From Node                                                                  ; To Node                                                                              ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+---------+----------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -11.466 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.048     ; 15.270     ;
; -11.427 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 15.257     ;
; -11.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.012     ; 15.086     ;
; -11.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 15.076     ;
; -11.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[0][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.011     ; 15.073     ;
; -11.144 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.048     ; 14.948     ;
; -11.127 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.040     ; 14.939     ;
; -11.125 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.040     ; 14.937     ;
; -11.083 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[9][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.019     ; 14.916     ;
; -11.069 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.018     ; 14.903     ;
; -11.067 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.018     ; 14.901     ;
; -11.065 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.026     ; 14.891     ;
; -11.056 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.018     ; 14.890     ;
; -11.046 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.046     ; 14.852     ;
; -11.044 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.046     ; 14.850     ;
; -11.031 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[6][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.036     ; 14.847     ;
; -11.031 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.048     ; 14.835     ;
; -11.030 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[7][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.036     ; 14.846     ;
; -11.026 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.015     ; 14.863     ;
; -11.024 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.015     ; 14.861     ;
; -11.016 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK1[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.020     ; 14.848     ;
; -11.015 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.020     ; 14.849     ;
; -10.999 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.014     ; 14.837     ;
; -10.999 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.014     ; 14.837     ;
; -10.994 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 14.824     ;
; -10.972 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.031     ; 14.793     ;
; -10.971 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.041     ; 14.782     ;
; -10.970 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.041     ; 14.781     ;
; -10.960 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.043     ; 14.769     ;
; -10.934 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 14.764     ;
; -10.923 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[13][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.019     ; 14.756     ;
; -10.923 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.019     ; 14.756     ;
; -10.919 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.021     ; 14.750     ;
; -10.917 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.021     ; 14.748     ;
; -10.899 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.041     ; 14.710     ;
; -10.899 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.041     ; 14.710     ;
; -10.886 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.033     ; 14.705     ;
; -10.885 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.048     ; 14.689     ;
; -10.884 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.048     ; 14.688     ;
; -10.883 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.033     ; 14.702     ;
; -10.882 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.015     ; 14.719     ;
; -10.879 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.043     ; 14.688     ;
; -10.878 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HOP[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.013     ; 14.717     ;
; -10.874 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.043     ; 14.683     ;
; -10.872 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.043     ; 14.681     ;
; -10.849 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[9]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 14.679     ;
; -10.831 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.030     ; 14.653     ;
; -10.809 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[12][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.020     ; 14.641     ;
; -10.804 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.020     ; 14.636     ;
; -10.791 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[7][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.018     ; 14.625     ;
; -10.790 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[6][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.018     ; 14.624     ;
; -10.751 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[4][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.019     ; 14.584     ;
; -10.726 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.018     ; 14.560     ;
; -10.704 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.038     ; 14.518     ;
; -10.703 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.038     ; 14.517     ;
; -10.686 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.028     ; 14.510     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.026     ; 14.508     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.026     ; 14.508     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.027     ; 14.507     ;
; -10.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 14.512     ;
; -10.669 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[0]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.014     ; 14.507     ;
; -10.668 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_RELOAD[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.020     ; 14.500     ;
; -10.666 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.014     ; 14.504     ;
; -10.640 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.033     ; 14.459     ;
; -10.640 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.033     ; 14.459     ;
; -10.626 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.032     ; 14.446     ;
; -10.623 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.030     ; 14.445     ;
; -10.622 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.031     ; 14.443     ;
; -10.595 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[9]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 14.425     ;
; -10.588 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[2][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.021     ; 14.419     ;
; -10.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[3][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.021     ; 14.418     ;
; -10.579 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[9]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.016     ; 14.415     ;
; -10.578 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 41.913     ;
; -10.578 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 41.913     ;
; -10.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.015     ; 14.409     ;
; -10.570 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.068     ; 14.354     ;
; -10.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.030     ; 14.385     ;
; -10.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[8][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.034     ; 14.381     ;
; -10.562 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[9][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.034     ; 14.380     ;
; -10.547 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.017     ; 14.382     ;
; -10.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|REPLAY_FIFO_REG[16][1]                          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.027     ; 14.370     ;
; -10.520 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 41.855     ;
; -10.520 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[3] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[3]                     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 41.855     ;
; -10.515 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 14.345     ;
; -10.513 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 14.343     ;
; -10.482 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.038     ; 14.296     ;
; -10.477 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 14.307     ;
; -10.476 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.052     ; 14.276     ;
; -10.472 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.051     ; 14.273     ;
; -10.469 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[17]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -4.024     ; 14.299     ;
; -10.452 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_COUNT[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.020     ; 14.284     ;
; -10.451 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 14.281     ;
; -10.451 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[6][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.036     ; 14.267     ;
; -10.451 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[7][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.036     ; 14.267     ;
; -10.448 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 14.278     ;
; -10.447 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[8]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.022     ; 14.277     ;
; -10.444 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[11]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.060      ; 41.792     ;
; -10.444 ; WF68K30L_TOP:I_CPU|WF68K30L_ADDRESS_REGISTERS:I_ADDRESSREGISTERS|ADR_WB[2] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[11]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.060      ; 41.792     ;
; -10.434 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.026     ; 14.260     ;
; -10.432 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]                         ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][8]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -4.026     ; 14.258     ;
+---------+----------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                        ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                  ; To Node                                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -3.911 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[301] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.437      ;
; -3.911 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[301] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.437      ;
; -3.909 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[301]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.435      ;
; -3.909 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[301]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.435      ;
; -3.895 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[238] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.421      ;
; -3.895 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[238] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.421      ;
; -3.806 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[134] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.330      ;
; -3.806 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[134] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.330      ;
; -3.805 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[136]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.329      ;
; -3.805 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[136]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.329      ;
; -3.804 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[236] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.330      ;
; -3.804 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[236]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.330      ;
; -3.804 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[236] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.330      ;
; -3.804 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[236]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.330      ;
; -3.803 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[135] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.327      ;
; -3.803 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[135] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.327      ;
; -3.798 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[140] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.461     ; 1.325      ;
; -3.798 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[231]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.324      ;
; -3.798 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[140] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.461     ; 1.325      ;
; -3.798 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[231]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.324      ;
; -3.796 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[231] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.322      ;
; -3.796 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[231] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.322      ;
; -3.790 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[232]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.316      ;
; -3.790 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[232]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.316      ;
; -3.789 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[233]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.315      ;
; -3.789 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[233]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.315      ;
; -3.778 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[282]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.304      ;
; -3.778 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[282]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.304      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[282] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[293] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[284]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[294]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[282] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[293] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[284]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.776 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[294]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.302      ;
; -3.775 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[284] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.301      ;
; -3.775 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[5]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[297] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.301      ;
; -3.775 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[284] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.301      ;
; -3.775 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[5]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[297] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.301      ;
; -3.774 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[293]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.300      ;
; -3.774 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[293]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.300      ;
; -3.773 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[294] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.299      ;
; -3.773 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[294] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.299      ;
; -3.768 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[286] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.294      ;
; -3.768 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[286] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.294      ;
; -3.765 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[299] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.291      ;
; -3.765 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[299] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.291      ;
; -3.763 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[288] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.460     ; 1.291      ;
; -3.763 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[288] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.460     ; 1.291      ;
; -3.732 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[298]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.258      ;
; -3.732 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[298]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.258      ;
; -3.731 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[235] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.257      ;
; -3.731 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[235]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.257      ;
; -3.731 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[235] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.257      ;
; -3.731 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[235]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.257      ;
; -3.730 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[298] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.256      ;
; -3.730 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[298] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.256      ;
; -3.683 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[141] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.207      ;
; -3.683 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[141] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.207      ;
; -3.672 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[142] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.196      ;
; -3.672 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[142] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.464     ; 1.196      ;
; -3.671 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[233] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.197      ;
; -3.671 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[233] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.197      ;
; -3.660 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[3]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[295] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.186      ;
; -3.660 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[3]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[295] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.186      ;
; -3.658 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[136] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.461     ; 1.185      ;
; -3.658 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[136] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.461     ; 1.185      ;
; -3.657 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[232] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.183      ;
; -3.657 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[141]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.461     ; 1.184      ;
; -3.657 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[232] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.183      ;
; -3.657 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[141]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.461     ; 1.184      ;
; -3.655 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[281] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.181      ;
; -3.655 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[281] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.181      ;
; -3.654 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[281]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.180      ;
; -3.654 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[281]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.180      ;
; -3.653 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[296]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.179      ;
; -3.653 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[296]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.179      ;
; -3.652 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[278] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.178      ;
; -3.652 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[296] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.178      ;
; -3.652 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[278]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.178      ;
; -3.652 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[278] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.178      ;
; -3.652 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[296] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.178      ;
; -3.652 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[278]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.178      ;
; -3.651 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[290]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.177      ;
; -3.651 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[290]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.177      ;
; -3.648 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[11] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[292] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.174      ;
; -3.648 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[300] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.174      ;
; -3.648 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[11] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[292] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.174      ;
; -3.648 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[300] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.174      ;
; -3.645 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[240] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.171      ;
; -3.645 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[290] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.171      ;
; -3.645 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[240] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.171      ;
; -3.645 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[290] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.171      ;
; -3.642 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[234] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.168      ;
; -3.642 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[287] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.168      ;
; -3.642 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[234] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.168      ;
; -3.642 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[287] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.168      ;
; -3.641 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[300]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.167      ;
; -3.641 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[300]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -4.462     ; 1.167      ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                    ;
+--------+----------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                          ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.381 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.391     ; 8.840      ;
; -1.381 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[1]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.391     ; 8.840      ;
; -1.288 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.415     ; 8.723      ;
; -1.288 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.415     ; 8.723      ;
; -1.288 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.415     ; 8.723      ;
; -1.288 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.415     ; 8.723      ;
; -1.288 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.415     ; 8.723      ;
; -1.288 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.415     ; 8.723      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.284 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.419     ; 8.715      ;
; -1.275 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.399     ; 8.726      ;
; -1.275 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.399     ; 8.726      ;
; -1.275 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.399     ; 8.726      ;
; -1.275 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.399     ; 8.726      ;
; -1.275 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.399     ; 8.726      ;
; -1.275 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.399     ; 8.726      ;
; -1.267 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.397     ; 8.720      ;
; -1.267 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.397     ; 8.720      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.246 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.398     ; 8.698      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.240 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.380     ; 8.710      ;
; -1.236 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.416     ; 8.670      ;
; -1.236 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.416     ; 8.670      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[6]       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.233 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.696      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.382     ; 8.700      ;
; -1.228 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.391     ; 8.687      ;
; -1.228 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.391     ; 8.687      ;
; -1.228 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.391     ; 8.687      ;
; -1.228 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.391     ; 8.687      ;
; -1.227 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.412     ; 8.665      ;
; -1.227 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.412     ; 8.665      ;
; -1.227 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.412     ; 8.665      ;
; -1.227 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.412     ; 8.665      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.387     ; 8.683      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[9][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.410     ; 8.657      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[9][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.217 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.385     ; 8.682      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
; -1.211 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][21]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.386     ; 8.675      ;
+--------+----------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 59.898 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.640      ;
; 59.898 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.640      ;
; 59.898 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.640      ;
; 59.898 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.640      ;
; 59.898 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.640      ;
; 60.058 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.480      ;
; 60.058 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.480      ;
; 60.058 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.480      ;
; 60.058 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.480      ;
; 60.058 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.480      ;
; 60.290 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.248      ;
; 60.290 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.248      ;
; 60.290 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.248      ;
; 60.290 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.248      ;
; 60.290 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.248      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.345 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.193      ;
; 60.355 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.183      ;
; 60.356 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.182      ;
; 60.515 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.023      ;
; 60.516 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 2.022      ;
; 60.571 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.967      ;
; 60.571 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.967      ;
; 60.571 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.967      ;
; 60.571 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.967      ;
; 60.571 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.967      ;
; 60.747 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.791      ;
; 60.748 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.790      ;
; 60.802 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.736      ;
; 60.803 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.735      ;
; 61.028 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.510      ;
; 61.029 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.509      ;
; 61.340 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.198      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 61.245 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 1.293      ;
; 61.629 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.909      ;
; 61.630 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.908      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
; 61.807 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.731      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -3.460 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 1.256      ;
; -3.460 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 1.256      ;
; -3.411 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 1.305      ;
; -3.411 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 1.305      ;
; -3.215 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 1.530      ;
; -3.215 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 1.530      ;
; -3.213 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.462      ; 1.535      ;
; -3.213 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.462      ; 1.535      ;
; -3.198 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.429      ; 1.517      ;
; -3.198 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.429      ; 1.517      ;
; -3.136 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.429      ; 1.579      ;
; -3.136 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.429      ; 1.579      ;
; -2.883 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.850      ;
; -2.883 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.850      ;
; -2.866 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.867      ;
; -2.866 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.867      ;
; -2.860 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.453      ; 1.879      ;
; -2.860 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.453      ; 1.879      ;
; -2.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 1.886      ;
; -2.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 1.886      ;
; -2.857 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.460      ; 1.889      ;
; -2.857 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.460      ; 1.889      ;
; -2.830 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.903      ;
; -2.830 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.903      ;
; -2.819 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.914      ;
; -2.819 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 1.914      ;
; -2.810 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.453      ; 1.929      ;
; -2.810 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.453      ; 1.929      ;
; -2.805 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.462      ; 1.943      ;
; -2.805 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.462      ; 1.943      ;
; -2.795 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.456      ; 1.947      ;
; -2.795 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.456      ; 1.947      ;
; -2.780 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.400      ; 1.906      ;
; -2.780 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.400      ; 1.906      ;
; -2.698 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.442      ; 2.030      ;
; -2.698 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.442      ; 2.030      ;
; -2.637 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.436      ; 2.085      ;
; -2.637 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.436      ; 2.085      ;
; -2.616 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.436      ; 2.106      ;
; -2.616 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.436      ; 2.106      ;
; -2.605 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.128      ;
; -2.605 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.128      ;
; -2.591 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 2.154      ;
; -2.591 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 2.154      ;
; -2.586 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.439      ; 2.139      ;
; -2.586 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.439      ; 2.139      ;
; -2.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.439      ; 2.141      ;
; -2.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.439      ; 2.141      ;
; -2.559 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.445      ; 2.172      ;
; -2.559 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.445      ; 2.172      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.175      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.454      ; 2.182      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.175      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.454      ; 2.182      ;
; -2.554 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.179      ;
; -2.554 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.179      ;
; -2.540 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.460      ; 2.206      ;
; -2.540 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.460      ; 2.206      ;
; -2.538 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.428      ; 2.176      ;
; -2.538 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.428      ; 2.176      ;
; -2.524 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.421      ; 2.183      ;
; -2.524 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.421      ; 2.183      ;
; -2.523 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.421      ; 2.184      ;
; -2.523 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.421      ; 2.184      ;
; -2.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.437      ; 2.220      ;
; -2.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.437      ; 2.220      ;
; -2.494 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 2.222      ;
; -2.494 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 2.222      ;
; -2.476 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 2.240      ;
; -2.476 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 2.240      ;
; -2.469 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.429      ; 2.246      ;
; -2.469 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.429      ; 2.246      ;
; -2.427 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.456      ; 2.315      ;
; -2.427 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.456      ; 2.315      ;
; -2.394 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.339      ;
; -2.394 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.339      ;
; -2.388 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 2.357      ;
; -2.388 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.459      ; 2.357      ;
; -2.362 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 2.354      ;
; -2.362 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.430      ; 2.354      ;
; -2.313 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.420      ;
; -2.313 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.420      ;
; -2.305 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.439      ; 2.420      ;
; -2.305 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.439      ; 2.420      ;
; -2.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.437      ; 2.419      ;
; -2.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.437      ; 2.419      ;
; -2.301 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.445      ; 2.430      ;
; -2.301 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.445      ; 2.430      ;
; -2.297 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.470      ; 2.459      ;
; -2.297 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.470      ; 2.459      ;
; -2.296 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.451      ; 2.441      ;
; -2.296 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.451      ; 2.441      ;
; -2.293 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.463      ; 2.456      ;
; -2.293 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.463      ; 2.456      ;
; -2.292 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.441      ;
; -2.292 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.447      ; 2.441      ;
; -2.283 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.454      ; 2.457      ;
; -2.283 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.454      ; 2.457      ;
; -2.274 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.423      ; 2.435      ;
; -2.274 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 4.423      ; 2.435      ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -3.460 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 1.256      ;
; -3.460 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 1.256      ;
; -3.411 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 1.305      ;
; -3.411 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 1.305      ;
; -3.215 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 1.530      ;
; -3.215 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 1.530      ;
; -3.213 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.462      ; 1.535      ;
; -3.213 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.462      ; 1.535      ;
; -3.198 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.429      ; 1.517      ;
; -3.198 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.429      ; 1.517      ;
; -3.136 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.429      ; 1.579      ;
; -3.136 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.429      ; 1.579      ;
; -2.883 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.850      ;
; -2.883 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.850      ;
; -2.866 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.867      ;
; -2.866 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.867      ;
; -2.860 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.453      ; 1.879      ;
; -2.860 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.453      ; 1.879      ;
; -2.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 1.886      ;
; -2.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 1.886      ;
; -2.857 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.460      ; 1.889      ;
; -2.857 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.460      ; 1.889      ;
; -2.830 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.903      ;
; -2.830 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.903      ;
; -2.819 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.914      ;
; -2.819 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 1.914      ;
; -2.810 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.453      ; 1.929      ;
; -2.810 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.453      ; 1.929      ;
; -2.805 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.462      ; 1.943      ;
; -2.805 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.462      ; 1.943      ;
; -2.795 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.456      ; 1.947      ;
; -2.795 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.456      ; 1.947      ;
; -2.780 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.400      ; 1.906      ;
; -2.780 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.400      ; 1.906      ;
; -2.698 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.442      ; 2.030      ;
; -2.698 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.442      ; 2.030      ;
; -2.637 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.436      ; 2.085      ;
; -2.637 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.436      ; 2.085      ;
; -2.616 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.436      ; 2.106      ;
; -2.616 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.436      ; 2.106      ;
; -2.605 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.128      ;
; -2.605 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.128      ;
; -2.591 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 2.154      ;
; -2.591 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 2.154      ;
; -2.586 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.439      ; 2.139      ;
; -2.586 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.439      ; 2.139      ;
; -2.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.439      ; 2.141      ;
; -2.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.439      ; 2.141      ;
; -2.559 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.445      ; 2.172      ;
; -2.559 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.445      ; 2.172      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.175      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.454      ; 2.182      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.175      ;
; -2.558 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.454      ; 2.182      ;
; -2.554 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.179      ;
; -2.554 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.179      ;
; -2.540 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.460      ; 2.206      ;
; -2.540 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.460      ; 2.206      ;
; -2.538 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.428      ; 2.176      ;
; -2.538 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.428      ; 2.176      ;
; -2.524 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.421      ; 2.183      ;
; -2.524 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.421      ; 2.183      ;
; -2.523 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.421      ; 2.184      ;
; -2.523 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.421      ; 2.184      ;
; -2.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.437      ; 2.220      ;
; -2.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.437      ; 2.220      ;
; -2.494 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 2.222      ;
; -2.494 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 2.222      ;
; -2.476 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 2.240      ;
; -2.476 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 2.240      ;
; -2.469 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.429      ; 2.246      ;
; -2.469 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.429      ; 2.246      ;
; -2.427 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.456      ; 2.315      ;
; -2.427 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.456      ; 2.315      ;
; -2.394 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.339      ;
; -2.394 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.339      ;
; -2.388 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 2.357      ;
; -2.388 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.459      ; 2.357      ;
; -2.362 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 2.354      ;
; -2.362 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.430      ; 2.354      ;
; -2.313 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.420      ;
; -2.313 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.420      ;
; -2.305 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.439      ; 2.420      ;
; -2.305 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.439      ; 2.420      ;
; -2.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.437      ; 2.419      ;
; -2.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.437      ; 2.419      ;
; -2.301 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.445      ; 2.430      ;
; -2.301 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.445      ; 2.430      ;
; -2.297 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.470      ; 2.459      ;
; -2.297 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.470      ; 2.459      ;
; -2.296 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.451      ; 2.441      ;
; -2.296 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.451      ; 2.441      ;
; -2.293 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.463      ; 2.456      ;
; -2.293 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.463      ; 2.456      ;
; -2.292 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.441      ;
; -2.292 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.447      ; 2.441      ;
; -2.283 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.454      ; 2.457      ;
; -2.283 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.454      ; 2.457      ;
; -2.274 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.423      ; 2.435      ;
; -2.274 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 4.423      ; 2.435      ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -3.079 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 1.256      ;
; -3.079 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 1.256      ;
; -3.030 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 1.305      ;
; -3.030 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 1.305      ;
; -2.834 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 1.530      ;
; -2.834 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 1.530      ;
; -2.832 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.083      ; 1.535      ;
; -2.832 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.083      ; 1.535      ;
; -2.817 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.050      ; 1.517      ;
; -2.817 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.050      ; 1.517      ;
; -2.755 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.050      ; 1.579      ;
; -2.755 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.050      ; 1.579      ;
; -2.502 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.850      ;
; -2.502 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.850      ;
; -2.485 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.867      ;
; -2.485 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.867      ;
; -2.479 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.074      ; 1.879      ;
; -2.479 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.074      ; 1.879      ;
; -2.478 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 1.886      ;
; -2.478 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 1.886      ;
; -2.476 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.081      ; 1.889      ;
; -2.476 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.081      ; 1.889      ;
; -2.449 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.903      ;
; -2.449 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.903      ;
; -2.438 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.914      ;
; -2.438 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 1.914      ;
; -2.429 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.074      ; 1.929      ;
; -2.429 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.074      ; 1.929      ;
; -2.424 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.083      ; 1.943      ;
; -2.424 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.083      ; 1.943      ;
; -2.414 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.077      ; 1.947      ;
; -2.414 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.077      ; 1.947      ;
; -2.399 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.021      ; 1.906      ;
; -2.399 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.021      ; 1.906      ;
; -2.317 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.063      ; 2.030      ;
; -2.317 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.063      ; 2.030      ;
; -2.256 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.057      ; 2.085      ;
; -2.256 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.057      ; 2.085      ;
; -2.235 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.057      ; 2.106      ;
; -2.235 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.057      ; 2.106      ;
; -2.224 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.128      ;
; -2.224 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.128      ;
; -2.210 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 2.154      ;
; -2.210 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 2.154      ;
; -2.205 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.060      ; 2.139      ;
; -2.205 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.060      ; 2.139      ;
; -2.203 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.060      ; 2.141      ;
; -2.203 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.060      ; 2.141      ;
; -2.178 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.066      ; 2.172      ;
; -2.178 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.066      ; 2.172      ;
; -2.177 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.175      ;
; -2.177 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.075      ; 2.182      ;
; -2.177 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.175      ;
; -2.177 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.075      ; 2.182      ;
; -2.173 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.179      ;
; -2.173 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.179      ;
; -2.159 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.081      ; 2.206      ;
; -2.159 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.081      ; 2.206      ;
; -2.157 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.049      ; 2.176      ;
; -2.157 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.049      ; 2.176      ;
; -2.143 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.042      ; 2.183      ;
; -2.143 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.042      ; 2.183      ;
; -2.142 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.042      ; 2.184      ;
; -2.142 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.042      ; 2.184      ;
; -2.122 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.058      ; 2.220      ;
; -2.122 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.058      ; 2.220      ;
; -2.113 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 2.222      ;
; -2.113 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 2.222      ;
; -2.095 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 2.240      ;
; -2.095 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 2.240      ;
; -2.088 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.050      ; 2.246      ;
; -2.088 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.050      ; 2.246      ;
; -2.046 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.077      ; 2.315      ;
; -2.046 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.077      ; 2.315      ;
; -2.013 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.339      ;
; -2.013 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.339      ;
; -2.007 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 2.357      ;
; -2.007 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.080      ; 2.357      ;
; -1.981 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 2.354      ;
; -1.981 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.051      ; 2.354      ;
; -1.932 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.420      ;
; -1.932 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.420      ;
; -1.924 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.060      ; 2.420      ;
; -1.924 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.060      ; 2.420      ;
; -1.923 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.058      ; 2.419      ;
; -1.923 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.058      ; 2.419      ;
; -1.920 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.066      ; 2.430      ;
; -1.920 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.066      ; 2.430      ;
; -1.916 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.091      ; 2.459      ;
; -1.916 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.091      ; 2.459      ;
; -1.915 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.072      ; 2.441      ;
; -1.915 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.072      ; 2.441      ;
; -1.912 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.084      ; 2.456      ;
; -1.912 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.084      ; 2.456      ;
; -1.911 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.441      ;
; -1.911 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.068      ; 2.441      ;
; -1.902 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.075      ; 2.457      ;
; -1.902 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.075      ; 2.457      ;
; -1.893 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.044      ; 2.435      ;
; -1.893 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 4.044      ; 2.435      ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -2.006 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 1.256      ;
; -2.006 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 1.256      ;
; -1.957 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 1.305      ;
; -1.957 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 1.305      ;
; -1.761 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 1.530      ;
; -1.761 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 1.530      ;
; -1.759 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.008      ; 1.535      ;
; -1.759 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.008      ; 1.535      ;
; -1.744 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.975      ; 1.517      ;
; -1.744 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.975      ; 1.517      ;
; -1.682 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.975      ; 1.579      ;
; -1.682 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.975      ; 1.579      ;
; -1.429 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.850      ;
; -1.429 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.850      ;
; -1.412 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.867      ;
; -1.412 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.867      ;
; -1.409 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.982      ; 1.859      ;
; -1.409 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.982      ; 1.859      ;
; -1.406 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.999      ; 1.879      ;
; -1.406 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.999      ; 1.879      ;
; -1.405 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 1.886      ;
; -1.405 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 1.886      ;
; -1.403 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.006      ; 1.889      ;
; -1.403 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.006      ; 1.889      ;
; -1.376 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.903      ;
; -1.376 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.903      ;
; -1.365 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.914      ;
; -1.365 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 1.914      ;
; -1.356 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.999      ; 1.929      ;
; -1.356 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.999      ; 1.929      ;
; -1.351 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.008      ; 1.943      ;
; -1.351 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.008      ; 1.943      ;
; -1.341 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.002      ; 1.947      ;
; -1.341 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.002      ; 1.947      ;
; -1.326 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.946      ; 1.906      ;
; -1.326 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.946      ; 1.906      ;
; -1.244 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.988      ; 2.030      ;
; -1.244 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.988      ; 2.030      ;
; -1.183 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.982      ; 2.085      ;
; -1.183 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.982      ; 2.085      ;
; -1.162 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.982      ; 2.106      ;
; -1.162 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.982      ; 2.106      ;
; -1.151 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.128      ;
; -1.151 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.128      ;
; -1.137 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 2.154      ;
; -1.137 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 2.154      ;
; -1.132 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.985      ; 2.139      ;
; -1.132 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.985      ; 2.139      ;
; -1.130 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.985      ; 2.141      ;
; -1.130 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.985      ; 2.141      ;
; -1.105 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.991      ; 2.172      ;
; -1.105 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.991      ; 2.172      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.175      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.000      ; 2.182      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.175      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.000      ; 2.182      ;
; -1.100 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.179      ;
; -1.100 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.179      ;
; -1.086 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.006      ; 2.206      ;
; -1.086 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.006      ; 2.206      ;
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.974      ; 2.176      ;
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.974      ; 2.176      ;
; -1.070 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.967      ; 2.183      ;
; -1.070 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.967      ; 2.183      ;
; -1.069 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.967      ; 2.184      ;
; -1.069 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.967      ; 2.184      ;
; -1.049 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.983      ; 2.220      ;
; -1.049 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.983      ; 2.220      ;
; -1.040 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 2.222      ;
; -1.040 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 2.222      ;
; -1.022 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 2.240      ;
; -1.022 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 2.240      ;
; -1.015 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.975      ; 2.246      ;
; -1.015 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.975      ; 2.246      ;
; -0.973 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.002      ; 2.315      ;
; -0.973 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.002      ; 2.315      ;
; -0.940 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.339      ;
; -0.940 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.339      ;
; -0.934 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 2.357      ;
; -0.934 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.005      ; 2.357      ;
; -0.908 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 2.354      ;
; -0.908 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.976      ; 2.354      ;
; -0.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.420      ;
; -0.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.420      ;
; -0.851 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.985      ; 2.420      ;
; -0.851 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.985      ; 2.420      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.983      ; 2.419      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.983      ; 2.419      ;
; -0.847 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.991      ; 2.430      ;
; -0.847 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.991      ; 2.430      ;
; -0.843 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.016      ; 2.459      ;
; -0.843 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.016      ; 2.459      ;
; -0.842 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.997      ; 2.441      ;
; -0.842 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.997      ; 2.441      ;
; -0.839 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.009      ; 2.456      ;
; -0.839 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.009      ; 2.456      ;
; -0.838 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.441      ;
; -0.838 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 2.993      ; 2.441      ;
; -0.829 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.000      ; 2.457      ;
; -0.829 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 3.000      ; 2.457      ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                         ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -2.006 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 1.256      ;
; -2.006 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 1.256      ;
; -1.957 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 1.305      ;
; -1.957 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 1.305      ;
; -1.761 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 1.530      ;
; -1.761 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 1.530      ;
; -1.759 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.008      ; 1.535      ;
; -1.759 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.008      ; 1.535      ;
; -1.744 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.975      ; 1.517      ;
; -1.744 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.975      ; 1.517      ;
; -1.682 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.975      ; 1.579      ;
; -1.682 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.975      ; 1.579      ;
; -1.429 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.850      ;
; -1.429 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.850      ;
; -1.412 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.867      ;
; -1.412 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.867      ;
; -1.409 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.982      ; 1.859      ;
; -1.409 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.982      ; 1.859      ;
; -1.406 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.999      ; 1.879      ;
; -1.406 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.999      ; 1.879      ;
; -1.405 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 1.886      ;
; -1.405 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 1.886      ;
; -1.403 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.006      ; 1.889      ;
; -1.403 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.006      ; 1.889      ;
; -1.376 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.903      ;
; -1.376 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.903      ;
; -1.365 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.914      ;
; -1.365 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 1.914      ;
; -1.356 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.999      ; 1.929      ;
; -1.356 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.999      ; 1.929      ;
; -1.351 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.008      ; 1.943      ;
; -1.351 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.008      ; 1.943      ;
; -1.341 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.002      ; 1.947      ;
; -1.341 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.002      ; 1.947      ;
; -1.326 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.946      ; 1.906      ;
; -1.326 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.946      ; 1.906      ;
; -1.244 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.988      ; 2.030      ;
; -1.244 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.988      ; 2.030      ;
; -1.183 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.982      ; 2.085      ;
; -1.183 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.982      ; 2.085      ;
; -1.162 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.982      ; 2.106      ;
; -1.162 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.982      ; 2.106      ;
; -1.151 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.128      ;
; -1.151 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.128      ;
; -1.137 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 2.154      ;
; -1.137 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 2.154      ;
; -1.132 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.985      ; 2.139      ;
; -1.132 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.985      ; 2.139      ;
; -1.130 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.985      ; 2.141      ;
; -1.130 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.985      ; 2.141      ;
; -1.105 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.991      ; 2.172      ;
; -1.105 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.991      ; 2.172      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.175      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.000      ; 2.182      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.175      ;
; -1.104 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.000      ; 2.182      ;
; -1.100 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.179      ;
; -1.100 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.179      ;
; -1.086 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.006      ; 2.206      ;
; -1.086 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.006      ; 2.206      ;
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.974      ; 2.176      ;
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.974      ; 2.176      ;
; -1.070 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.967      ; 2.183      ;
; -1.070 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.967      ; 2.183      ;
; -1.069 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.967      ; 2.184      ;
; -1.069 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.967      ; 2.184      ;
; -1.049 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.983      ; 2.220      ;
; -1.049 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.983      ; 2.220      ;
; -1.040 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 2.222      ;
; -1.040 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 2.222      ;
; -1.022 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 2.240      ;
; -1.022 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 2.240      ;
; -1.015 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.975      ; 2.246      ;
; -1.015 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.975      ; 2.246      ;
; -0.973 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.002      ; 2.315      ;
; -0.973 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.002      ; 2.315      ;
; -0.940 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.339      ;
; -0.940 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.339      ;
; -0.934 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 2.357      ;
; -0.934 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.005      ; 2.357      ;
; -0.908 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 2.354      ;
; -0.908 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.976      ; 2.354      ;
; -0.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.420      ;
; -0.859 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.420      ;
; -0.851 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.985      ; 2.420      ;
; -0.851 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.985      ; 2.420      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.983      ; 2.419      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.983      ; 2.419      ;
; -0.847 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.991      ; 2.430      ;
; -0.847 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.991      ; 2.430      ;
; -0.843 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.016      ; 2.459      ;
; -0.843 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.016      ; 2.459      ;
; -0.842 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.997      ; 2.441      ;
; -0.842 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.997      ; 2.441      ;
; -0.839 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.009      ; 2.456      ;
; -0.839 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]            ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.009      ; 2.456      ;
; -0.838 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.441      ;
; -0.838 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 2.993      ; 2.441      ;
; -0.829 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.000      ; 2.457      ;
; -0.829 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]           ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 3.000      ; 2.457      ;
+--------+---------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                                                                                                                 ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; \P_2M4576:TMP_2M54[0]                                                                                                                                                                                                                                                                                 ; \P_2M4576:TMP_2M54[0]                                                                                                                                                                                                                                                                                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig                                                                                                                                                            ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig                                                                                                                                                              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:done                                                                                                                                                                  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:done                                                                                                                                                                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:base_address[0]                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:base_address[0]                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:is_buffer_wrapped                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:is_buffer_wrapped                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|last_level_delayed                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|last_level_delayed                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_out_mode_ff                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_out_mode_ff                                                                                                                                                                                                                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.731      ;
; 0.611 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][7]                                                                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][7]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.897      ;
; 0.611 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][267]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][267]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.897      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|condition_delay_reg[0]                                                                                                                                                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|condition_delay_reg[1]                                                                                                                                                                                                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:147:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:147:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:156:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:156:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][33]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][33]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][25]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][25]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][32]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][32]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][59]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][59]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][76]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][76]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][82]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][82]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][102]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][102]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][81]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][81]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][105]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][105]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][108]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][108]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][141]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][141]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][168]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][168]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][148]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][148]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[155]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][155]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][202]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][202]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][208]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][208]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][212]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][212]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][200]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][200]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[211]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][211]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][224]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][224]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][226]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][226]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][253]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][253]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][265]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][265]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][268]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][268]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][282]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][282]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.612 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][296]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][296]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.898      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:169:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:169:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:167:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:167:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:131:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:131:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][29]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][29]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][2]                                                                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][2]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][105]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][105]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][130]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][130]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][188]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][188]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][218]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][218]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][223]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][223]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[229]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][229]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.613 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][300]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][300]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.899      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:185:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:185:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:220:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:220:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[2]                                                                                                                                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][2]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[51]                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][51]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][78]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][78]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][72]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][72]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][106]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][106]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][152]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][152]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][153]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][153]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][157]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][157]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][165]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][165]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][147]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][147]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[160]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][160]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][205]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][205]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][182]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][182]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][203]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][203]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[182]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][182]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[184]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][184]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][236]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][236]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[231]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][231]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][270]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][270]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][257]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][257]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][258]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][258]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.614 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[300]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][300]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.900      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:173:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:173:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:149:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:149:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:99:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][16]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][16]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][7]                                                                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][7]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[5]                                                                                                                                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][5]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][57]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][57]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][94]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][94]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][73]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][73]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][151]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][151]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][199]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][199]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][203]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][203]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][210]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][210]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][246]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][246]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[227]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][227]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][254]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][254]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][280]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][280]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][285]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][285]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[257]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][257]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[287]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][287]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.615 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[305]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][305]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.901      ;
; 0.616 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|condition_delay_reg[1]                                                                                                                                                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|condition_delay_reg[2]                                                                                                                                                                                                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.902      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.445 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.445 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.731      ;
; 0.622 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.908      ;
; 0.623 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.909      ;
; 1.007 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 1.293      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.912 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.198      ;
; 0.937 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.223      ;
; 0.938 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.224      ;
; 1.019 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.305      ;
; 1.022 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.308      ;
; 1.022 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.308      ;
; 1.223 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.509      ;
; 1.224 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.510      ;
; 1.399 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.685      ;
; 1.449 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.735      ;
; 1.450 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.736      ;
; 1.452 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.738      ;
; 1.452 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.738      ;
; 1.501 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.787      ;
; 1.504 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.790      ;
; 1.505 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.791      ;
; 1.532 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.818      ;
; 1.581 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.867      ;
; 1.626 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.912      ;
; 1.661 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.947      ;
; 1.681 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.967      ;
; 1.681 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.967      ;
; 1.706 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.992      ;
; 1.736 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.022      ;
; 1.737 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.023      ;
; 1.786 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.072      ;
; 1.896 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.182      ;
; 1.897 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.183      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 1.907 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.193      ;
; 1.962 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.248      ;
; 1.962 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.248      ;
; 1.962 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.248      ;
; 1.962 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.248      ;
; 2.194 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 2.480      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                       ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                                                   ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.399      ;
; 21.925 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.050      ; 9.413      ;
; 21.925 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.050      ; 9.413      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 9.071      ;
; 22.253 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.050      ; 9.085      ;
; 22.253 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.050      ; 9.085      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.046      ; 8.856      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.044      ; 8.854      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.042      ; 8.852      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.027      ; 8.837      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[4]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 8.845      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\ENVELOPE_PERIOD:LOCK                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 8.845      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:LOCK                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 8.845      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_B_OUT                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[5]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[7]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[6]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[4]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[2]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[1]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[3]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[0]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[10]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[9]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[8]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[5]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[6]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[4]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[7]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[8]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[9]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[10]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[3]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[2]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[0]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[1]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[1]                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.046      ; 8.856      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.044      ; 8.854      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 8.849      ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                       ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                                                   ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.399      ;
; 21.924 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.399      ;
; 21.925 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.050      ; 9.413      ;
; 21.925 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.050      ; 9.413      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.071      ;
; 22.252 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 9.071      ;
; 22.253 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.050      ; 9.085      ;
; 22.253 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.050      ; 9.085      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.046      ; 8.856      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.044      ; 8.854      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.042      ; 8.852      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.027      ; 8.837      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[4]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB                                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 8.845      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\ENVELOPE_PERIOD:LOCK                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 8.845      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:LOCK                                                                  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 8.845      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_B_OUT                                               ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[5]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[7]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[6]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[4]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[2]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[1]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[3]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[0]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[10]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[9]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[8]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 8.847      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[5]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[6]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[4]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[7]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[8]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[9]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[10]                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[3]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[2]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[0]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[1]                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 8.846      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[1]                                ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.046      ; 8.856      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 8.853      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.044      ; 8.854      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.041      ; 8.851      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 8.850      ;
; 22.478 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 8.849      ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                              ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.034     ; 2.398      ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                              ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.033     ; 2.754      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
; 28.856 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.034     ; 2.398      ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                              ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.033     ; 2.754      ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                              ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.146 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.034     ; 2.398      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.033     ; 2.754      ;
; 2.501 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.033     ; 2.754      ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                              ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.028     ; 3.170      ;
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.028     ; 3.170      ;
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.028     ; 3.170      ;
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.028     ; 3.170      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.538      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.038     ; 3.583      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 3.596      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.027     ; 3.608      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.020     ; 3.618      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.029     ; 3.626      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.036     ; 3.860      ;
; 3.698 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 3.974      ;
; 3.698 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 3.974      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.999      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.999      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.999      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 3.999      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.010     ; 4.204      ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                              ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.028     ; 3.170      ;
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.028     ; 3.170      ;
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.028     ; 3.170      ;
; 2.912 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.028     ; 3.170      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.278 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.538      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.335 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.038     ; 3.583      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.336 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 3.596      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.349 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.027     ; 3.608      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.352 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.020     ; 3.618      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.369 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.029     ; 3.626      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.036     ; 3.860      ;
; 3.610 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.036     ; 3.860      ;
; 3.698 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 3.974      ;
; 3.698 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 3.974      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.999      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.999      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.999      ;
; 3.712 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 3.999      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 4.204      ;
; 3.928 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.010     ; 4.204      ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg0  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg0  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg1  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg1  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg2  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg2  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg3  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg3  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg4  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg4  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg5  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg5  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg6  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg6  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg1   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg1   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg10  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg10  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg11  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg11  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg12  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg12  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg13  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg13  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg14  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg14  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg15  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg15  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg16  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg16  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg17  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg17  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg18  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg18  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg19  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg19  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg2   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg2   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg20  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg20  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg21  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg21  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg22  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg22  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg23  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg23  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg24  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg24  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg25  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg25  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg26  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg26  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg27  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg27  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg28  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg28  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg29  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg29  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg3   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg3   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg30  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg30  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg31  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg31  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg32  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg32  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg33  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg33  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg34  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg34  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg35  ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg35  ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg4   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg4   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg5   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg5   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg6   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg6   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg7   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg7   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg8   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg8   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg9   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg9   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_we_reg        ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_we_reg        ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a100~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a100~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a101~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a101~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a102~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a102~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a103~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a103~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a104~porta_memory_reg0 ;
; 10.131 ; 12.695       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a104~porta_memory_reg0 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.061 ; 15.625       ; 2.564          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.061 ; 15.625       ; 2.564          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------+
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|BIT_CLK_SM               ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|BIT_CLK_SM               ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|SAMPLE_CLK_SM            ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|SAMPLE_CLK_SM            ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[0]  ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[0]  ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[1]  ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[1]  ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[2]  ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[2]  ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[3]  ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[3]  ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[4]  ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[4]  ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[1]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[1]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[2]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[2]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[3]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[3]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[4]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[4]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[5]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[5]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[6]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[6]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[7]       ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[7]       ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|DE_I                ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|DE_I                ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|EVENn_ODD_I         ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|EVENn_ODD_I         ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[3]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[3]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[4]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[4]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[5]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[5]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[0]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[0]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[1]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[1]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[2]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[2]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[3]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[3]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[4]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[4]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[5]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[5]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[6]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[6]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[7]      ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[7]      ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_REQ            ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_REQ            ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_STRB           ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_STRB           ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Fall       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I         ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Fall       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I         ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_REQ_I         ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_REQ_I         ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]             ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]             ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[6]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[6]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]              ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]              ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]  ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]  ;
; 18.420 ; 19.531       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10] ;
; 18.420 ; 19.531       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 28.943 ; 31.250       ; 2.307          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 28.943 ; 31.250       ; 2.307          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.139 ; 31.250       ; 1.111          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.139 ; 31.250       ; 1.111          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 59.869 ; 62.500       ; 2.631          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'altera_reserved_tck'                                                       ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock               ; Clock Edge ; Target              ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; 97.531 ; 100.000      ; 2.469          ; Port Rate ; altera_reserved_tck ; Rise       ; altera_reserved_tck ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.590 ; -0.590 ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]         ; CLK_PLL1      ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 26.366 ; 26.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 25.876 ; 25.876 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 26.482 ; 26.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 26.949 ; 26.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 34.201 ; 34.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.309  ; 7.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 10.936 ; 10.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 17.375 ; 17.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 17.045 ; 17.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 17.228 ; 17.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 17.926 ; 17.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 16.819 ; 16.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 15.419 ; 15.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 18.105 ; 18.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.883 ; 19.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 22.861 ; 22.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 15.990 ; 15.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.932 ; 19.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 19.478 ; 19.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 16.041 ; 16.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 16.251 ; 16.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.542 ; 15.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 13.063 ; 13.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 12.805 ; 12.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 13.670 ; 13.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 12.348 ; 12.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.837 ; 15.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 15.891 ; 15.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.805 ; 14.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 15.141 ; 15.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.877 ; 11.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 12.055 ; 12.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.886  ; 6.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 18.779 ; 18.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 35.084 ; 35.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 35.026 ; 35.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 11.760 ; 11.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 13.358 ; 13.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 10.435 ; 10.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 9.737  ; 9.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 19.843 ; 19.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 7.689  ; 7.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.049 ; 20.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 33.005 ; 33.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 17.665 ; 17.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.703 ; 16.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 16.591 ; 16.591 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 16.399 ; 16.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.209 ; 17.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.257 ; 18.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.177 ; 19.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 5.964  ; 5.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 20.638 ; 20.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.268 ; 19.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 18.199 ; 18.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.445 ; 18.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.888 ; 17.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.288 ; 18.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.836 ; 18.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.956 ; 17.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.205 ; 17.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.962 ; 18.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.867 ; 20.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.250 ; 18.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.689 ; 20.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.054 ; 21.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 3.336  ; 3.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 6.818  ; 6.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 35.013 ; 35.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.398 ; 10.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 8.825  ; 8.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.824 ; 10.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.784  ; 9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 10.267 ; 10.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 10.246 ; 10.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 10.148 ; 10.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.072 ; 10.072 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 10.901 ; 10.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 11.298 ; 11.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 10.547 ; 10.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.261  ; 9.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.901 ; 14.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 8.317  ; 8.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 14.117 ; 14.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 22.095 ; 22.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 8.694  ; 8.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 9.579  ; 9.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 9.424  ; 9.424  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.732  ; 8.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 6.890  ; 6.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 7.403  ; 7.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 34.823 ; 34.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 11.984 ; 11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 26.088 ; 26.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 25.598 ; 25.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 26.204 ; 26.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 26.671 ; 26.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 33.438 ; 33.438 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.308  ; 7.308  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 7.791  ; 7.791  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 7.328  ; 7.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 16.612 ; 16.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 16.596 ; 16.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 16.601 ; 16.601 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 17.648 ; 17.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 15.986 ; 15.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 14.625 ; 14.625 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 17.602 ; 17.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.434 ; 19.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 22.177 ; 22.177 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.116 ; 19.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.794 ; 18.794 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.278 ; 15.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 15.396 ; 15.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.264 ; 15.264 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 12.230 ; 12.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 12.011 ; 12.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 12.737 ; 12.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 11.962 ; 11.962 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.225 ; 15.225 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.167 ; 16.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.117 ; 14.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 14.657 ; 14.657 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.934 ; 15.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.193 ; 11.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 11.239 ; 11.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 17.725 ; 17.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 34.600 ; 34.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 34.542 ; 34.542 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 6.253  ; 6.253  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.394  ; 7.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 19.698 ; 19.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 19.904 ; 19.904 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 32.242 ; 32.242 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 17.053 ; 17.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.091 ; 16.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 16.227 ; 16.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.772 ; 15.772 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.095 ; 17.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 17.463 ; 17.463 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 19.880 ; 19.880 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 18.361 ; 18.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 19.875 ; 19.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 18.819 ; 18.819 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.572 ; 17.572 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.167 ; 18.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.055 ; 17.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.494 ; 17.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 20.843 ; 20.843 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 15.845 ; 15.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.224 ; 18.224 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.232 ; 18.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.517 ; 16.517 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.478 ; 18.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.219 ; 18.219 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.005 ; 20.005 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 20.238 ; 20.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 34.735 ; 34.735 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 15.683 ; 15.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 34.339 ; 34.339 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 26.366 ; 26.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 25.876 ; 25.876 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 26.482 ; 26.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 26.949 ; 26.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 34.201 ; 34.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.309  ; 7.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 10.936 ; 10.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 17.375 ; 17.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 17.045 ; 17.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 17.228 ; 17.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 17.926 ; 17.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 16.819 ; 16.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.419 ; 15.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.105 ; 18.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.883 ; 19.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 22.861 ; 22.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 15.990 ; 15.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.932 ; 19.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 19.478 ; 19.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.041 ; 16.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.251 ; 16.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.542 ; 15.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.063 ; 13.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.805 ; 12.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 13.670 ; 13.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 12.348 ; 12.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.837 ; 15.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.891 ; 15.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.805 ; 14.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.141 ; 15.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.877 ; 11.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 12.055 ; 12.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.886  ; 6.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 18.779 ; 18.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 35.084 ; 35.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 35.026 ; 35.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 11.760 ; 11.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 13.358 ; 13.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 10.435 ; 10.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 9.737  ; 9.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.843 ; 19.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 7.689  ; 7.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.049 ; 20.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 33.005 ; 33.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.665 ; 17.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.703 ; 16.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 16.591 ; 16.591 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 16.399 ; 16.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.209 ; 17.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.257 ; 18.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.177 ; 19.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 5.964  ; 5.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 20.638 ; 20.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.268 ; 19.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 18.199 ; 18.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.445 ; 18.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.888 ; 17.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.288 ; 18.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.836 ; 18.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.956 ; 17.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.205 ; 17.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.962 ; 18.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.867 ; 20.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.250 ; 18.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.689 ; 20.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.054 ; 21.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 3.336  ; 3.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 6.818  ; 6.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 35.013 ; 35.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.398 ; 10.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 8.825  ; 8.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.824 ; 10.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.784  ; 9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 10.267 ; 10.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 10.246 ; 10.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 10.148 ; 10.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.072 ; 10.072 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 10.901 ; 10.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 11.298 ; 11.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 10.547 ; 10.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.261  ; 9.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.901 ; 14.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 8.317  ; 8.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 14.117 ; 14.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 22.095 ; 22.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 8.694  ; 8.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 9.579  ; 9.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 9.424  ; 9.424  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.732  ; 8.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 6.890  ; 6.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 7.403  ; 7.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.823 ; 34.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 11.984 ; 11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 26.088 ; 26.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 25.598 ; 25.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 26.204 ; 26.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 26.671 ; 26.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 33.438 ; 33.438 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.308  ; 7.308  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 7.791  ; 7.791  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 7.328  ; 7.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 16.612 ; 16.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 16.596 ; 16.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 16.601 ; 16.601 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 17.648 ; 17.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 15.986 ; 15.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 14.625 ; 14.625 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 17.602 ; 17.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.434 ; 19.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 22.177 ; 22.177 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.116 ; 19.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.794 ; 18.794 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.278 ; 15.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 15.396 ; 15.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.264 ; 15.264 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.230 ; 12.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.011 ; 12.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 12.737 ; 12.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 11.962 ; 11.962 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.225 ; 15.225 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.167 ; 16.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.117 ; 14.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.657 ; 14.657 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.934 ; 15.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.193 ; 11.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 11.239 ; 11.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 17.725 ; 17.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 34.600 ; 34.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 34.542 ; 34.542 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 6.253  ; 6.253  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.394  ; 7.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.698 ; 19.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 19.904 ; 19.904 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 32.242 ; 32.242 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.053 ; 17.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.091 ; 16.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 16.227 ; 16.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.772 ; 15.772 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.095 ; 17.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 17.463 ; 17.463 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 19.880 ; 19.880 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 18.361 ; 18.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 19.875 ; 19.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 18.819 ; 18.819 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.572 ; 17.572 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.167 ; 18.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.055 ; 17.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.494 ; 17.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 20.843 ; 20.843 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 15.845 ; 15.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.224 ; 18.224 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.232 ; 18.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.517 ; 16.517 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.478 ; 18.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.219 ; 18.219 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.005 ; 20.005 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.238 ; 20.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 34.735 ; 34.735 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 15.683 ; 15.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.339 ; 34.339 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CLK_PLL1      ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[1]        ; CLK_PLL1      ; 27.103 ; 27.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[2]        ; CLK_PLL1      ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[3]        ; CLK_PLL1      ; 26.613 ; 26.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[4]        ; CLK_PLL1      ; 27.219 ; 27.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[5]        ; CLK_PLL1      ; 27.686 ; 27.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 34.278 ; 34.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 17.452 ; 17.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 17.712 ; 17.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 18.059 ; 18.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 18.663 ; 18.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 17.442 ; 17.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 18.747 ; 18.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 20.550 ; 20.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 22.138 ; 22.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 20.044 ; 20.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.755 ; 18.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 16.118 ; 16.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 16.918 ; 16.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 16.854 ; 16.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 16.279 ; 16.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 13.686 ; 13.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 12.990 ; 12.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.363 ; 16.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 16.718 ; 16.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 15.535 ; 15.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 15.283 ; 15.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 11.154 ; 11.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 12.167 ; 12.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 35.226 ; 35.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 35.168 ; 35.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 19.977 ; 19.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.183 ; 20.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 33.082 ; 33.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 18.191 ; 18.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 17.229 ; 17.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.258 ; 17.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; 17.230 ; 17.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.391 ; 18.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; 21.279 ; 21.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.289 ; 19.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Xn         ; CLK_PLL1      ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Yn         ; CLK_PLL1      ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Xn         ; CLK_PLL1      ; 4.471  ; 4.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Yn         ; CLK_PLL1      ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PENn           ; CLK_PLL1      ; 8.010  ; 8.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 20.715 ; 20.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.935 ; 19.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.030 ; 19.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.182 ; 19.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.511 ; 18.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.422 ; 18.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.362 ; 19.362 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.783 ; 18.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.935 ; 17.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 19.104 ; 19.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.942 ; 20.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.308 ; 18.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 19.966 ; 19.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.166 ; 21.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 35.750 ; 35.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 20.035 ; 20.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 34.965 ; 34.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 27.103 ; 27.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 26.613 ; 26.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 27.219 ; 27.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 27.686 ; 27.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 34.278 ; 34.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 17.452 ; 17.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 17.712 ; 17.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 18.059 ; 18.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 18.663 ; 18.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 17.442 ; 17.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.747 ; 18.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 20.550 ; 20.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 22.138 ; 22.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 20.044 ; 20.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.755 ; 18.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.118 ; 16.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.918 ; 16.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.854 ; 16.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 16.279 ; 16.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.686 ; 13.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 12.990 ; 12.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.363 ; 16.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.718 ; 16.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.535 ; 15.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.283 ; 15.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.154 ; 11.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 12.167 ; 12.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 35.226 ; 35.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 35.168 ; 35.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.977 ; 19.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.183 ; 20.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 33.082 ; 33.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.191 ; 18.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 17.229 ; 17.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.258 ; 17.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 17.230 ; 17.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.391 ; 18.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 21.279 ; 21.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.289 ; 19.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 4.471  ; 4.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 8.010  ; 8.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 20.715 ; 20.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.935 ; 19.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.030 ; 19.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.182 ; 19.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.511 ; 18.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.422 ; 18.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.362 ; 19.362 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.783 ; 18.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.935 ; 17.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 19.104 ; 19.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.942 ; 20.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.308 ; 18.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 19.966 ; 19.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.166 ; 21.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 35.750 ; 35.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 20.035 ; 20.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.965 ; 34.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                   ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise    ; Fall    ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.841   ; 0.841   ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]         ; CLK_PLL1      ; -8.978  ; -8.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; -9.054  ; -9.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; -9.848  ; -9.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; -9.234  ; -9.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; -8.978  ; -8.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; -9.154  ; -9.154  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -8.595  ; -8.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -7.061  ; -7.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -7.206  ; -7.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -5.715  ; -5.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -6.948  ; -6.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -6.338  ; -6.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -5.965  ; -5.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -6.520  ; -6.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -6.139  ; -6.139  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -6.112  ; -6.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -5.715  ; -5.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -5.821  ; -5.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -8.625  ; -8.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -8.737  ; -8.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -10.718 ; -10.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -13.082 ; -13.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -15.492 ; -15.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -15.238 ; -15.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -13.082 ; -13.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -7.571  ; -7.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -8.638  ; -8.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -9.443  ; -9.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -8.644  ; -8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -8.896  ; -8.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -8.956  ; -8.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -8.489  ; -8.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -9.331  ; -9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -8.497  ; -8.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -10.167 ; -10.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -8.259  ; -8.259  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -9.594  ; -9.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -7.571  ; -7.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -7.575  ; -7.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -8.521  ; -8.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -7.637  ; -7.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -7.615  ; -7.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -6.638  ; -6.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -9.772  ; -9.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -8.340  ; -8.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -8.340  ; -8.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -8.643  ; -8.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -8.547  ; -8.547  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -5.968  ; -5.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -2.786  ; -2.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -7.394  ; -7.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -8.546  ; -8.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -7.626  ; -7.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -10.252 ; -10.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -10.458 ; -10.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -7.358  ; -7.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -8.249  ; -8.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -6.388  ; -6.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -11.451 ; -11.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -11.919 ; -11.919 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -12.233 ; -12.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -11.451 ; -11.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -12.857 ; -12.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -16.136 ; -16.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -12.439 ; -12.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -15.173 ; -15.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -13.573 ; -13.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -5.716  ; -5.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.858  ; -6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -6.858  ; -6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.380  ; -7.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -7.027  ; -7.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.918  ; -7.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.631  ; -7.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.687  ; -7.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -7.610  ; -7.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.796  ; -7.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.512  ; -7.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -8.142  ; -8.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.700  ; -7.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.991  ; -7.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.556  ; -7.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.795  ; -7.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.232  ; -7.232  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.305  ; -7.305  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -3.088  ; -3.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -6.570  ; -6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -9.055  ; -9.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -8.625  ; -8.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -6.337  ; -6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -6.677  ; -6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -7.248  ; -7.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -6.848  ; -6.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -6.677  ; -6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -6.808  ; -6.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -7.374  ; -7.374  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -7.181  ; -7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -7.340  ; -7.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -7.331  ; -7.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -8.458  ; -8.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -8.855  ; -8.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -8.050  ; -8.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -7.571  ; -7.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -6.772  ; -6.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -8.568  ; -8.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -7.723  ; -7.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -7.784  ; -7.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -8.679  ; -8.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -8.098  ; -8.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -8.976  ; -8.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -7.391  ; -7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -7.692  ; -7.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -7.540  ; -7.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -7.391  ; -7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -6.296  ; -6.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -6.665  ; -6.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -6.800  ; -6.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -12.042 ; -12.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -11.736 ; -11.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; -9.892  ; -9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; -11.252 ; -11.252 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; -12.175 ; -12.175 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; -9.892  ; -9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; -10.705 ; -10.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; -11.370 ; -11.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -8.872  ; -8.872  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -7.060  ; -7.060  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -7.543  ; -7.543  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -6.658  ; -6.658  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -7.080  ; -7.080  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -12.247 ; -12.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -14.072 ; -14.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -14.043 ; -14.043 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -14.199 ; -14.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -15.249 ; -15.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -13.731 ; -13.731 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -12.247 ; -12.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -16.115 ; -16.115 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -16.157 ; -16.157 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -16.771 ; -16.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -18.498 ; -18.498 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -12.323 ; -12.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -16.923 ; -16.923 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -16.857 ; -16.857 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -12.323 ; -12.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -8.852  ; -8.852  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -9.134  ; -9.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -8.852  ; -8.852  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -9.715  ; -9.715  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -9.638  ; -9.638  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -9.975  ; -9.975  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -9.633  ; -9.633  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -11.250 ; -11.250 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -10.400 ; -10.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -12.095 ; -12.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -9.841  ; -9.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -11.221 ; -11.221 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -10.001 ; -10.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -9.147  ; -9.147  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -10.140 ; -10.140 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -9.256  ; -9.256  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -9.046  ; -9.046  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -7.906  ; -7.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -10.477 ; -10.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -11.028 ; -11.028 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -10.538 ; -10.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -10.477 ; -10.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -6.005  ; -6.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -7.146  ; -7.146  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -16.671 ; -16.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -16.877 ; -16.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -11.784 ; -11.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -14.210 ; -14.210 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -13.078 ; -13.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -13.248 ; -13.248 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.815 ; -13.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -13.078 ; -13.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -14.493 ; -14.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -17.708 ; -17.708 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -14.058 ; -14.058 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -16.792 ; -16.792 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -15.476 ; -15.476 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -14.283 ; -14.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -16.994 ; -16.994 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -16.850 ; -16.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -15.170 ; -15.170 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -15.768 ; -15.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -14.800 ; -14.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -15.116 ; -15.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -19.238 ; -19.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -14.283 ; -14.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -16.281 ; -16.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -16.013 ; -16.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -14.988 ; -14.988 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -16.311 ; -16.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -18.766 ; -18.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -16.083 ; -16.083 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -18.068 ; -18.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -18.045 ; -18.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -9.532  ; -9.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -11.495 ; -11.495 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -14.402 ; -14.402 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -8.978  ; -8.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -9.054  ; -9.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -9.848  ; -9.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -9.234  ; -9.234  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -8.978  ; -8.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -9.154  ; -9.154  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -8.595  ; -8.595  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -7.061  ; -7.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -7.206  ; -7.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -5.715  ; -5.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.948  ; -6.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.338  ; -6.338  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -5.965  ; -5.965  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.520  ; -6.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.139  ; -6.139  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -6.112  ; -6.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -5.715  ; -5.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -5.821  ; -5.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -8.625  ; -8.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -8.737  ; -8.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -10.718 ; -10.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -13.082 ; -13.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -15.492 ; -15.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -15.238 ; -15.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -13.082 ; -13.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -7.571  ; -7.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -8.638  ; -8.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -9.443  ; -9.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -8.644  ; -8.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -8.896  ; -8.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -8.956  ; -8.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -8.489  ; -8.489  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -9.331  ; -9.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -8.497  ; -8.497  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -10.167 ; -10.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -8.259  ; -8.259  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -9.594  ; -9.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -7.571  ; -7.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -7.575  ; -7.575  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -8.521  ; -8.521  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -7.637  ; -7.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -7.615  ; -7.615  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -6.638  ; -6.638  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -9.772  ; -9.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -8.340  ; -8.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -8.340  ; -8.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -8.643  ; -8.643  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -8.547  ; -8.547  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -5.968  ; -5.968  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -2.786  ; -2.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -7.394  ; -7.394  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -8.546  ; -8.546  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -7.626  ; -7.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -10.252 ; -10.252 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -7.441  ; -7.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -10.458 ; -10.458 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -7.358  ; -7.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -8.249  ; -8.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.388  ; -6.388  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -11.451 ; -11.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -11.919 ; -11.919 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -12.233 ; -12.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -11.451 ; -11.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -12.857 ; -12.857 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -16.136 ; -16.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -12.439 ; -12.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -15.173 ; -15.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -13.573 ; -13.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -5.716  ; -5.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.858  ; -6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -6.858  ; -6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.380  ; -7.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -7.027  ; -7.027  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.918  ; -7.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.631  ; -7.631  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.687  ; -7.687  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -7.610  ; -7.610  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.796  ; -7.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.512  ; -7.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -8.142  ; -8.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.700  ; -7.700  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.991  ; -7.991  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.556  ; -7.556  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.795  ; -7.795  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.232  ; -7.232  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.305  ; -7.305  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -3.088  ; -3.088  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -6.570  ; -6.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -9.055  ; -9.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -8.625  ; -8.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -6.337  ; -6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -6.677  ; -6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -7.248  ; -7.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -6.848  ; -6.848  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -6.677  ; -6.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -6.808  ; -6.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -7.374  ; -7.374  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -7.181  ; -7.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -7.340  ; -7.340  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -7.331  ; -7.331  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -8.458  ; -8.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -8.855  ; -8.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -8.050  ; -8.050  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -7.571  ; -7.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -6.772  ; -6.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -8.568  ; -8.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -7.723  ; -7.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -7.784  ; -7.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -8.679  ; -8.679  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -8.098  ; -8.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -8.976  ; -8.976  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -7.391  ; -7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -7.692  ; -7.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -7.540  ; -7.540  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -7.391  ; -7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -6.296  ; -6.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -6.665  ; -6.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -6.800  ; -6.800  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -12.042 ; -12.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -11.736 ; -11.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -9.892  ; -9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -11.252 ; -11.252 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -12.175 ; -12.175 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -9.892  ; -9.892  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -10.705 ; -10.705 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -11.370 ; -11.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -8.872  ; -8.872  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -7.060  ; -7.060  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -7.543  ; -7.543  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -6.658  ; -6.658  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -7.080  ; -7.080  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -12.247 ; -12.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -14.072 ; -14.072 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -14.043 ; -14.043 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -14.199 ; -14.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -15.249 ; -15.249 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -13.731 ; -13.731 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -12.247 ; -12.247 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -16.115 ; -16.115 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -16.157 ; -16.157 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -16.771 ; -16.771 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -18.498 ; -18.498 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -12.323 ; -12.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -16.923 ; -16.923 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -16.857 ; -16.857 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -12.323 ; -12.323 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -8.852  ; -8.852  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -9.134  ; -9.134  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -8.852  ; -8.852  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -9.715  ; -9.715  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -9.638  ; -9.638  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -9.975  ; -9.975  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -9.633  ; -9.633  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -11.250 ; -11.250 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -10.400 ; -10.400 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -12.095 ; -12.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -9.841  ; -9.841  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -11.221 ; -11.221 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -10.001 ; -10.001 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -9.147  ; -9.147  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -10.140 ; -10.140 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -9.256  ; -9.256  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -9.046  ; -9.046  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -7.906  ; -7.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -10.477 ; -10.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -11.028 ; -11.028 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -10.538 ; -10.538 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -10.477 ; -10.477 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -6.005  ; -6.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -7.146  ; -7.146  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -16.671 ; -16.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -16.877 ; -16.877 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -11.784 ; -11.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -14.210 ; -14.210 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -13.078 ; -13.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -13.248 ; -13.248 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.815 ; -13.815 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -13.078 ; -13.078 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -14.493 ; -14.493 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -17.708 ; -17.708 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -14.058 ; -14.058 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -16.792 ; -16.792 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -15.476 ; -15.476 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -14.283 ; -14.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -16.994 ; -16.994 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -16.850 ; -16.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -15.170 ; -15.170 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -15.768 ; -15.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -14.800 ; -14.800 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -15.116 ; -15.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -19.238 ; -19.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -14.283 ; -14.283 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -16.281 ; -16.281 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -16.013 ; -16.013 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -14.988 ; -14.988 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -16.311 ; -16.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -18.766 ; -18.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -16.083 ; -16.083 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -18.068 ; -18.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -18.045 ; -18.045 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -9.532  ; -9.532  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -11.495 ; -11.495 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -14.402 ; -14.402 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CLK_PLL1      ; -13.781 ; -13.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[1]        ; CLK_PLL1      ; -14.470 ; -14.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[2]        ; CLK_PLL1      ; -13.781 ; -13.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[3]        ; CLK_PLL1      ; -14.173 ; -14.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[4]        ; CLK_PLL1      ; -14.126 ; -14.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[5]        ; CLK_PLL1      ; -14.182 ; -14.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -9.115  ; -9.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; -12.329 ; -12.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; -13.803 ; -13.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; -13.668 ; -13.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; -14.298 ; -14.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; -15.132 ; -15.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; -13.856 ; -13.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; -12.329 ; -12.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; -14.666 ; -14.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; -15.241 ; -15.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -16.326 ; -16.326 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -17.049 ; -17.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -13.570 ; -13.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -16.151 ; -16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -16.214 ; -16.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -13.570 ; -13.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -8.274  ; -8.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -9.698  ; -9.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -10.560 ; -10.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -9.815  ; -9.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -9.518  ; -9.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -10.100 ; -10.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -9.715  ; -9.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -9.801  ; -9.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -9.484  ; -9.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -11.561 ; -11.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; -9.396  ; -9.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; -10.584 ; -10.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; -9.592  ; -9.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; -8.689  ; -8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; -9.178  ; -9.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; -8.613  ; -8.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; -8.274  ; -8.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -8.815  ; -8.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -9.102  ; -9.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -9.222  ; -9.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -8.815  ; -8.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -16.600 ; -16.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -16.806 ; -16.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -9.078  ; -9.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -13.941 ; -13.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -12.441 ; -12.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -12.979 ; -12.979 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; -13.370 ; -13.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; -12.441 ; -12.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; -14.006 ; -14.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; -17.250 ; -17.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; -13.096 ; -13.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; -16.149 ; -16.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; -14.560 ; -14.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Xn         ; CLK_PLL1      ; -3.511  ; -3.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Yn         ; CLK_PLL1      ; -3.772  ; -3.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Xn         ; CLK_PLL1      ; -3.218  ; -3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Yn         ; CLK_PLL1      ; -5.550  ; -5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PENn           ; CLK_PLL1      ; -5.107  ; -5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -7.053  ; -7.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.557  ; -7.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.152  ; -7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -7.356  ; -7.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.542  ; -7.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -7.255  ; -7.255  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -7.391  ; -7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.146  ; -8.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -7.783  ; -7.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.053  ; -7.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.527  ; -7.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -7.608  ; -7.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.061  ; -7.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -7.899  ; -7.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.500  ; -7.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.186  ; -7.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.261  ; -7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -9.222  ; -9.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -9.802  ; -9.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -10.409 ; -10.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -13.781 ; -13.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -14.470 ; -14.470 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -13.781 ; -13.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -14.173 ; -14.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -14.126 ; -14.126 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -14.182 ; -14.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -9.115  ; -9.115  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -12.329 ; -12.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -13.803 ; -13.803 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -13.668 ; -13.668 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -14.298 ; -14.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -15.132 ; -15.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -13.856 ; -13.856 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -12.329 ; -12.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -14.666 ; -14.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -15.241 ; -15.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -16.326 ; -16.326 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -17.049 ; -17.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -13.570 ; -13.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -16.151 ; -16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -16.214 ; -16.214 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -13.570 ; -13.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -8.274  ; -8.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -9.698  ; -9.698  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -10.560 ; -10.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -9.815  ; -9.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -9.518  ; -9.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -10.100 ; -10.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -9.715  ; -9.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -9.801  ; -9.801  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -9.484  ; -9.484  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -11.561 ; -11.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -9.396  ; -9.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -10.584 ; -10.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -9.592  ; -9.592  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -8.689  ; -8.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -9.178  ; -9.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -8.613  ; -8.613  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -8.274  ; -8.274  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -8.815  ; -8.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -9.102  ; -9.102  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -9.222  ; -9.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -8.815  ; -8.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -16.600 ; -16.600 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -16.806 ; -16.806 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -9.078  ; -9.078  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -13.941 ; -13.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -12.441 ; -12.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -12.979 ; -12.979 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -13.370 ; -13.370 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -12.441 ; -12.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -14.006 ; -14.006 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -17.250 ; -17.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -13.096 ; -13.096 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -16.149 ; -16.149 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -14.560 ; -14.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -3.511  ; -3.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -3.772  ; -3.772  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -3.218  ; -3.218  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -5.550  ; -5.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -5.107  ; -5.107  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -7.053  ; -7.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.557  ; -7.557  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.152  ; -7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -7.356  ; -7.356  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.542  ; -7.542  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -7.255  ; -7.255  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -7.391  ; -7.391  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.146  ; -8.146  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -7.783  ; -7.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.053  ; -7.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.527  ; -7.527  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -7.608  ; -7.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.061  ; -7.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -7.899  ; -7.899  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.500  ; -7.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.186  ; -7.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.261  ; -7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -9.222  ; -9.222  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -9.802  ; -9.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -10.409 ; -10.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+----------------+---------------+---------+---------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; PLL_FAULT      ; CLK_PLL1      ; 7.683  ; 7.683  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 8.490  ; 8.490  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_RDn       ; CLK_PLL1      ; 29.742 ; 29.742 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 29.732 ; 29.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 21.137 ; 21.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 19.051 ; 19.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 20.040 ; 20.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 19.492 ; 19.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 19.830 ; 19.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 20.099 ; 20.099 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 20.660 ; 20.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 20.319 ; 20.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 21.379 ; 21.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 20.459 ; 20.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 21.707 ; 21.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 21.306 ; 21.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 20.066 ; 20.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 21.746 ; 21.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 22.336 ; 22.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 22.097 ; 22.097 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 22.021 ; 22.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 23.085 ; 23.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 22.447 ; 22.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 23.607 ; 23.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 22.322 ; 22.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 14.257 ; 14.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 10.752 ; 10.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 10.491 ; 10.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 5.081  ; 5.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 28.301 ; 28.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 27.606 ; 27.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 35.573 ; 35.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 35.058 ; 35.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 34.499 ; 34.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 36.038 ; 36.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 34.980 ; 34.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 34.144 ; 34.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 8.031  ; 8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 8.097  ; 8.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL1      ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL1      ; 22.569 ; 22.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL1      ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL1      ; 20.363 ; 20.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL1      ; 22.247 ; 22.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL1      ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL1      ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL1      ; 24.273 ; 24.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL1      ; 23.461 ; 23.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL1      ; 23.780 ; 23.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL1      ; 18.589 ; 18.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL1      ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL1      ; 21.425 ; 21.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL1      ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL1      ; 21.038 ; 21.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL1      ; 21.754 ; 21.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 47.313 ; 47.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 46.506 ; 46.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 45.421 ; 45.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 45.631 ; 45.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 43.988 ; 43.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 47.908 ; 47.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 44.841 ; 44.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 45.197 ; 45.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 44.778 ; 44.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 46.618 ; 46.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 46.953 ; 46.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 45.238 ; 45.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 47.648 ; 47.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 45.313 ; 45.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 6.409  ; 6.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 5.042  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 6.173  ; 6.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 6.195  ; 6.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 20.241 ; 20.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 20.350 ; 20.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.086  ; 6.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 5.808  ; 5.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 5.539  ; 5.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 4.925  ; 4.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 4.626  ; 4.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 22.444 ; 22.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 22.363 ; 22.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 30.190 ; 30.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 31.409 ; 31.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 6.916  ; 6.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 8.827  ; 8.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 8.971  ; 8.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 20.164 ; 20.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 28.926 ; 28.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 27.999 ; 27.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 28.293 ; 28.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 28.124 ; 28.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 27.173 ; 27.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 30.310 ; 30.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 28.108 ; 28.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 30.128 ; 30.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 30.098 ; 30.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 27.352 ; 27.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 9.342  ; 9.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 8.640  ; 8.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 8.905  ; 8.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 8.089  ; 8.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 20.476 ; 20.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.933  ; 6.933  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.371  ; 7.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.732  ; 6.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.475  ; 7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.955  ; 7.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 27.061 ; 27.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 27.129 ; 27.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 28.450 ; 28.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 27.185 ; 27.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 26.596 ; 26.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 25.993 ; 25.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 28.222 ; 28.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 25.880 ; 25.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 22.002 ; 22.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 21.182 ; 21.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 21.291 ; 21.291 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 22.590 ; 22.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 24.707 ; 24.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 23.891 ; 23.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 42.702 ; 42.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 44.563 ; 44.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 43.133 ; 43.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 43.155 ; 43.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 44.544 ; 44.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 44.546 ; 44.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 44.365 ; 44.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 44.132 ; 44.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 43.417 ; 43.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 44.752 ; 44.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 45.057 ; 45.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 44.338 ; 44.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 42.737 ; 42.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 42.443 ; 42.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 26.233 ; 26.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 24.982 ; 24.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 26.426 ; 26.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 24.972 ; 24.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 26.642 ; 26.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 26.365 ; 26.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_WEn        ; CLK_PLL1      ; 12.429 ; 12.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.358  ; 8.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 27.779 ; 27.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 29.416 ; 29.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 28.228 ; 28.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 31.282 ; 31.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 30.650 ; 30.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 29.102 ; 29.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 31.614 ; 31.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 11.488 ; 11.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.076  ; 8.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 7.144  ; 7.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 5.904  ; 5.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 6.239  ; 6.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 6.178  ; 6.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 6.180  ; 6.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 6.067  ; 6.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 7.472  ; 7.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 5.238  ; 5.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.561  ; 9.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 8.626  ; 8.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 7.002  ; 7.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 7.531  ; 7.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 7.538  ; 7.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 20.101 ; 20.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 5.992  ; 5.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 13.744 ; 13.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 17.947 ; 17.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 16.995 ; 16.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 18.781 ; 18.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 18.480 ; 18.480 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 18.470 ; 18.470 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 12.315 ; 12.315 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 17.039 ; 17.039 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 24.311 ; 24.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 23.796 ; 23.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 23.237 ; 23.237 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 24.776 ; 24.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 23.718 ; 23.718 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 22.882 ; 22.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 23.235 ; 23.235 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 36.051 ; 36.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 35.131 ; 35.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 34.153 ; 34.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 34.244 ; 34.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 33.169 ; 33.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 36.521 ; 36.521 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 34.022 ; 34.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 34.304 ; 34.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 33.910 ; 33.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 35.231 ; 35.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 35.566 ; 35.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 33.851 ; 33.851 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 36.386 ; 36.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 33.885 ; 33.885 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 34.509 ; 34.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 10.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 9.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 20.355 ; 20.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 21.574 ; 21.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 18.118 ; 18.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 17.191 ; 17.191 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 17.485 ; 17.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 17.316 ; 17.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 16.365 ; 16.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 19.502 ; 19.502 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 16.846 ; 16.846 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 18.866 ; 18.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 18.836 ; 18.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 16.090 ; 16.090 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 17.019 ; 17.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 18.231 ; 18.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 18.692 ; 18.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 18.479 ; 18.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 17.882 ; 17.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 19.929 ; 19.929 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 17.352 ; 17.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 19.329 ; 19.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 16.301 ; 16.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 12.704 ; 12.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 11.510 ; 11.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 10.327 ; 10.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 10.199 ; 10.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.375 ; 11.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 17.543 ; 17.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 16.725 ; 16.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 31.440 ; 31.440 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 33.188 ; 33.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 31.865 ; 31.865 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 31.768 ; 31.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 33.725 ; 33.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.159 ; 33.159 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 33.546 ; 33.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 33.239 ; 33.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 32.549 ; 32.549 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 33.365 ; 33.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 34.080 ; 34.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 33.670 ; 33.670 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 33.076 ; 33.076 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 31.309 ; 31.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 31.485 ; 31.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 22.455 ; 22.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 20.774 ; 20.774 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 22.648 ; 22.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 20.764 ; 20.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 15.535 ; 15.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 15.399 ; 15.258 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 16.516 ; 16.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 18.153 ; 18.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 18.393 ; 18.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 20.176 ; 20.035 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 19.544 ; 19.403 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 17.839 ; 17.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 20.508 ; 20.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 16.637 ; 16.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 29.742 ; 29.742 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 29.732 ; 29.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 21.137 ; 21.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 19.051 ; 19.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 20.040 ; 20.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 19.492 ; 19.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 19.830 ; 19.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 20.099 ; 20.099 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 20.660 ; 20.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 20.319 ; 20.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 21.379 ; 21.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 20.459 ; 20.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 21.707 ; 21.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 21.306 ; 21.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 20.066 ; 20.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 21.746 ; 21.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 22.336 ; 22.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 22.097 ; 22.097 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 22.021 ; 22.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 23.085 ; 23.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 22.447 ; 22.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 23.607 ; 23.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 22.322 ; 22.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.257 ; 14.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 10.752 ; 10.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 10.491 ; 10.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 5.081  ; 5.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 28.301 ; 28.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 27.606 ; 27.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 35.573 ; 35.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 35.058 ; 35.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 34.499 ; 34.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 36.038 ; 36.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 34.980 ; 34.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 34.144 ; 34.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 8.031  ; 8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 8.097  ; 8.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 22.569 ; 22.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 20.363 ; 20.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 22.247 ; 22.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 24.273 ; 24.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 23.461 ; 23.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 23.780 ; 23.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 18.589 ; 18.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 21.425 ; 21.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 21.038 ; 21.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 21.754 ; 21.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 47.313 ; 47.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 46.506 ; 46.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 45.421 ; 45.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 45.631 ; 45.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 43.988 ; 43.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 47.908 ; 47.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 44.841 ; 44.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 45.197 ; 45.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 44.778 ; 44.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 46.618 ; 46.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 46.953 ; 46.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 45.238 ; 45.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 47.648 ; 47.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 45.313 ; 45.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 6.409  ; 6.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 5.042  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 6.173  ; 6.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 6.195  ; 6.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 20.241 ; 20.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 20.350 ; 20.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.086  ; 6.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 5.808  ; 5.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 5.539  ; 5.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 4.925  ; 4.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 4.626  ; 4.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 22.444 ; 22.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 22.363 ; 22.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 30.190 ; 30.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 31.409 ; 31.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 6.916  ; 6.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 8.827  ; 8.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 8.971  ; 8.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 20.164 ; 20.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 28.926 ; 28.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 27.999 ; 27.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 28.293 ; 28.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 28.124 ; 28.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 27.173 ; 27.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 30.310 ; 30.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 28.108 ; 28.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 30.128 ; 30.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 30.098 ; 30.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 27.352 ; 27.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 9.342  ; 9.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 8.640  ; 8.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 8.905  ; 8.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 8.089  ; 8.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 20.476 ; 20.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.933  ; 6.933  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.371  ; 7.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.732  ; 6.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.475  ; 7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.955  ; 7.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 27.061 ; 27.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 27.129 ; 27.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 28.450 ; 28.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 27.185 ; 27.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 26.596 ; 26.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 25.993 ; 25.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 28.222 ; 28.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 25.880 ; 25.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 22.002 ; 22.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 21.182 ; 21.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 21.291 ; 21.291 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 22.590 ; 22.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 24.707 ; 24.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 23.891 ; 23.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 42.702 ; 42.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 44.563 ; 44.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 43.133 ; 43.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 43.155 ; 43.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 44.544 ; 44.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 44.546 ; 44.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 44.365 ; 44.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 44.132 ; 44.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 43.417 ; 43.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 44.752 ; 44.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 45.057 ; 45.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 44.338 ; 44.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 42.737 ; 42.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 42.443 ; 42.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 26.233 ; 26.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 24.982 ; 24.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 26.426 ; 26.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 24.972 ; 24.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 26.642 ; 26.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 26.365 ; 26.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 12.429 ; 12.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.358  ; 8.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 27.779 ; 27.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 29.416 ; 29.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 28.228 ; 28.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 31.282 ; 31.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 30.650 ; 30.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 29.102 ; 29.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 31.614 ; 31.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.488 ; 11.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.076  ; 8.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 7.144  ; 7.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 5.904  ; 5.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 6.239  ; 6.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 6.178  ; 6.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 6.180  ; 6.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 6.067  ; 6.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 7.472  ; 7.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 5.238  ; 5.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.561  ; 9.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 8.626  ; 8.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 7.002  ; 7.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 7.531  ; 7.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 20.101 ; 20.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 5.992  ; 5.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 13.744 ; 13.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 17.947 ; 17.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 16.995 ; 16.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 18.781 ; 18.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 18.480 ; 18.480 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 18.470 ; 18.470 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 12.315 ; 12.315 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 17.039 ; 17.039 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 24.311 ; 24.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 23.796 ; 23.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 23.237 ; 23.237 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 24.776 ; 24.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 23.718 ; 23.718 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 22.882 ; 22.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 23.235 ; 23.235 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 36.051 ; 36.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 35.131 ; 35.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 34.153 ; 34.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 34.244 ; 34.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 33.169 ; 33.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 36.521 ; 36.521 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 34.022 ; 34.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 34.304 ; 34.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 33.910 ; 33.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 35.231 ; 35.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 35.566 ; 35.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 33.851 ; 33.851 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 36.386 ; 36.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 33.885 ; 33.885 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 34.509 ; 34.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 10.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 9.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 20.355 ; 20.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 21.574 ; 21.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 18.118 ; 18.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 17.191 ; 17.191 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 17.485 ; 17.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 17.316 ; 17.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 16.365 ; 16.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 19.502 ; 19.502 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 16.846 ; 16.846 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 18.866 ; 18.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 18.836 ; 18.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 16.090 ; 16.090 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 17.019 ; 17.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 18.231 ; 18.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 18.692 ; 18.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 18.479 ; 18.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 17.882 ; 17.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 19.929 ; 19.929 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 17.352 ; 17.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 19.329 ; 19.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 16.301 ; 16.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 12.704 ; 12.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 11.510 ; 11.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 10.327 ; 10.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 10.199 ; 10.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.375 ; 11.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 17.543 ; 17.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 16.725 ; 16.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 31.440 ; 31.440 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 33.188 ; 33.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 31.865 ; 31.865 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 31.768 ; 31.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 33.725 ; 33.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.159 ; 33.159 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 33.546 ; 33.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 33.239 ; 33.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 32.549 ; 32.549 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 33.365 ; 33.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 34.080 ; 34.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 33.670 ; 33.670 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 33.076 ; 33.076 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 31.309 ; 31.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 31.485 ; 31.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 22.455 ; 22.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 20.774 ; 20.774 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 22.648 ; 22.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 20.764 ; 20.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 15.535 ; 15.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 15.399 ; 15.258 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 16.516 ; 16.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 18.153 ; 18.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 18.393 ; 18.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 20.176 ; 20.035 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 19.544 ; 19.403 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 17.839 ; 17.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 20.508 ; 20.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 16.637 ; 16.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 19.958 ; 19.958 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 12.495 ; 12.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BERRn          ; CLK_PLL1      ; 6.590  ; 6.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BUTTONn        ; CLK_PLL1      ; 18.517 ; 18.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 17.822 ; 17.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 25.789 ; 25.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 25.274 ; 25.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 24.715 ; 24.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 26.254 ; 26.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 25.196 ; 25.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 24.360 ; 24.360 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 24.713 ; 24.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 24.023 ; 24.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 21.817 ; 21.817 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 23.701 ; 23.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 25.727 ; 25.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 24.915 ; 24.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 25.234 ; 25.234 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 20.043 ; 20.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 22.879 ; 22.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 22.492 ; 22.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 23.208 ; 23.208 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_LDACn      ; CLK_PLL1      ; 8.106  ; 8.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SCLK       ; CLK_PLL1      ; 9.220  ; 9.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SYNCn      ; CLK_PLL1      ; 5.743  ; 5.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 37.529 ; 37.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 36.440 ; 36.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 35.355 ; 35.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 35.565 ; 35.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 34.204 ; 34.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 37.842 ; 37.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 35.057 ; 35.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 35.339 ; 35.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 34.945 ; 34.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 36.552 ; 36.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 36.887 ; 36.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 35.172 ; 35.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 37.864 ; 37.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 35.247 ; 35.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 35.544 ; 35.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 5.776  ; 5.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_CEn      ; CLK_PLL1      ; 20.610 ; 20.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_OEn      ; CLK_PLL1      ; 21.829 ; 21.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC          ; CLK_PLL1      ; 21.618 ; 21.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS0n       ; CLK_PLL1      ; 19.346 ; 19.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS1n       ; CLK_PLL1      ; 18.419 ; 18.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 18.713 ; 18.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 18.544 ; 18.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IORDn      ; CLK_PLL1      ; 17.593 ; 17.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IOWRn      ; CLK_PLL1      ; 20.730 ; 20.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RHn        ; CLK_PLL1      ; 18.324 ; 18.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RLn        ; CLK_PLL1      ; 20.344 ; 20.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WEn        ; CLK_PLL1      ; 20.314 ; 20.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WL         ; CLK_PLL1      ; 17.568 ; 17.568 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 13.230 ; 13.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 4.955  ; 4.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 6.837  ; 6.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PADRSTn        ; CLK_PLL1      ; 6.651  ; 6.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 16.838 ; 16.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 16.787 ; 16.787 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 17.785 ; 17.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 16.151 ; 16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 17.798 ; 17.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 15.800 ; 15.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 17.081 ; 17.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 15.027 ; 15.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 15.392 ; 15.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 15.271 ; 15.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 14.804 ; 14.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.952 ; 11.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 17.723 ; 17.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 16.905 ; 16.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 32.918 ; 32.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 33.067 ; 33.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 33.089 ; 33.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 34.760 ; 34.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 34.480 ; 34.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 34.581 ; 34.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 34.274 ; 34.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 33.584 ; 33.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 34.686 ; 34.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 35.401 ; 35.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 34.991 ; 34.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 34.554 ; 34.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 32.671 ; 32.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 32.520 ; 32.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 22.635 ; 22.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 20.954 ; 20.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 22.828 ; 22.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 20.944 ; 20.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 17.202 ; 17.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 16.925 ; 16.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 13.555 ; 13.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 9.316  ; 9.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM0n          ; CLK_PLL1      ; 18.042 ; 18.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM1n          ; CLK_PLL1      ; 19.679 ; 19.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM2n          ; CLK_PLL1      ; 18.648 ; 18.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM3n          ; CLK_PLL1      ; 21.702 ; 21.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM4n          ; CLK_PLL1      ; 21.070 ; 21.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM5n          ; CLK_PLL1      ; 19.365 ; 19.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM6n          ; CLK_PLL1      ; 22.034 ; 22.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 13.095 ; 13.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC          ; CLK_PLL1      ; 15.198 ; 15.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 19.958 ; 19.958 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 12.495 ; 12.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.590  ; 6.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 18.517 ; 18.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 17.822 ; 17.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 25.789 ; 25.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 25.274 ; 25.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 24.715 ; 24.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 26.254 ; 26.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 25.196 ; 25.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 24.360 ; 24.360 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 24.713 ; 24.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 24.023 ; 24.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 21.817 ; 21.817 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 23.701 ; 23.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 25.727 ; 25.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 24.915 ; 24.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 25.234 ; 25.234 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 20.043 ; 20.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 22.879 ; 22.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 22.492 ; 22.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 23.208 ; 23.208 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 8.106  ; 8.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 9.220  ; 9.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 5.743  ; 5.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 37.529 ; 37.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 36.440 ; 36.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 35.355 ; 35.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 35.565 ; 35.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 34.204 ; 34.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 37.842 ; 37.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 35.057 ; 35.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 35.339 ; 35.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 34.945 ; 34.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 36.552 ; 36.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 36.887 ; 36.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 35.172 ; 35.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 37.864 ; 37.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 35.247 ; 35.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 35.544 ; 35.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 5.776  ; 5.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 20.610 ; 20.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 21.829 ; 21.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 21.618 ; 21.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 19.346 ; 19.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 18.419 ; 18.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 18.713 ; 18.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 18.544 ; 18.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 17.593 ; 17.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 20.730 ; 20.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 18.324 ; 18.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 20.344 ; 20.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 20.314 ; 20.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 17.568 ; 17.568 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.230 ; 13.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 4.955  ; 4.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 6.837  ; 6.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 6.651  ; 6.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 16.838 ; 16.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 16.787 ; 16.787 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 17.785 ; 17.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 16.151 ; 16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 17.798 ; 17.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 15.800 ; 15.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 17.081 ; 17.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 15.027 ; 15.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 15.392 ; 15.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 15.271 ; 15.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 14.804 ; 14.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.952 ; 11.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 17.723 ; 17.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 16.905 ; 16.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 32.918 ; 32.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 33.067 ; 33.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 33.089 ; 33.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 34.760 ; 34.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 34.480 ; 34.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 34.581 ; 34.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 34.274 ; 34.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 33.584 ; 33.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 34.686 ; 34.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 35.401 ; 35.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 34.991 ; 34.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 34.554 ; 34.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 32.671 ; 32.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 32.520 ; 32.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 22.635 ; 22.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 20.954 ; 20.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 22.828 ; 22.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 20.944 ; 20.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 17.202 ; 17.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 16.925 ; 16.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 13.555 ; 13.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 9.316  ; 9.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 18.042 ; 18.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 19.679 ; 19.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 18.648 ; 18.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 21.702 ; 21.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 21.070 ; 21.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 19.365 ; 19.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 22.034 ; 22.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 13.095 ; 13.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 15.198 ; 15.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CLK_AUX        ; CLK_PLL2      ; 2.896  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL2      ; 24.605 ; 24.605 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL2      ; 23.644 ; 23.644 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL2      ; 24.605 ; 24.605 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL2      ; 21.438 ; 21.438 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL2      ; 23.322 ; 23.322 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL2      ; 28.686 ; 28.686 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL2      ; 28.686 ; 28.686 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL2      ; 25.348 ; 25.348 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL2      ; 24.536 ; 24.536 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL2      ; 24.855 ; 24.855 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL2      ; 19.664 ; 19.664 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL2      ; 27.056 ; 27.056 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL2      ; 22.500 ; 22.500 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL2      ; 27.056 ; 27.056 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL2      ; 22.113 ; 22.113 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL2      ; 22.829 ; 22.829 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL2      ; 6.475  ; 6.475  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ; 6.553  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL2      ; 25.204 ; 25.204 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL2      ; 25.204 ; 25.204 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL2      ; 24.818 ; 24.818 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL2      ; 23.247 ; 23.247 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL2      ; 23.280 ; 23.280 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL2      ; 21.739 ; 21.739 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL2      ; 24.593 ; 24.593 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL2      ; 21.736 ; 21.736 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL2      ; 23.742 ; 23.742 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL2      ; 22.758 ; 22.758 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL2      ; 24.691 ; 24.691 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL2      ; 23.832 ; 23.832 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL2      ; 21.239 ; 21.239 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL2      ; 23.561 ; 23.561 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL2      ; 20.593 ; 20.593 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL2      ; 22.875 ; 22.875 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL2      ; 20.959 ; 20.959 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL2      ; 20.804 ; 20.804 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL2      ; 22.295 ; 22.295 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL2      ; 21.231 ; 21.231 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL2      ; 21.260 ; 21.260 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL2      ; 22.677 ; 22.677 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL2      ; 21.397 ; 21.397 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL2      ; 22.825 ; 22.825 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL2      ; 23.561 ; 23.561 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL2      ; 14.819 ; 14.819 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ; 8.302  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ; 8.302  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL2      ;        ; 2.896  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ;        ; 6.553  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ;        ; 8.302  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ;        ; 8.302  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; PLL_FAULT      ; CLK_PLL1      ; 7.683  ; 7.683  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 8.490  ; 8.490  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_RDn       ; CLK_PLL1      ; 8.412  ; 8.412  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 8.402  ; 8.402  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 9.251  ; 9.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 11.353 ; 11.353 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 9.740  ; 9.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 10.032 ; 10.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 9.746  ; 9.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 9.975  ; 9.975  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 10.105 ; 10.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 10.518 ; 10.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 10.821 ; 10.821 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 10.009 ; 10.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 10.270 ; 10.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 11.076 ; 11.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 9.251  ; 9.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 9.756  ; 9.756  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 9.418  ; 9.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 10.769 ; 10.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 9.690  ; 9.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 9.465  ; 9.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 10.902 ; 10.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 10.219 ; 10.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 10.017 ; 10.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 10.714 ; 10.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 12.141 ; 12.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 10.069 ; 10.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 8.245  ; 8.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 8.118  ; 8.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 5.081  ; 5.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 9.754  ; 9.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 6.438  ; 6.438  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 6.288  ; 6.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 8.029  ; 8.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 7.910  ; 7.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 7.684  ; 7.684  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 8.958  ; 8.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 6.596  ; 6.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.288  ; 6.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 7.558  ; 7.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 7.811  ; 7.811  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 8.031  ; 8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 8.097  ; 8.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL1      ; 11.507 ; 11.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL1      ; 11.799 ; 11.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL1      ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL1      ; 11.507 ; 11.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL1      ; 14.116 ; 14.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL1      ; 10.938 ; 10.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL1      ; 12.433 ; 12.433 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL1      ; 12.859 ; 12.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL1      ; 11.263 ; 11.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL1      ; 10.938 ; 10.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL1      ; 12.875 ; 12.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL1      ; 12.425 ; 12.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL1      ; 12.425 ; 12.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL1      ; 12.832 ; 12.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL1      ; 13.133 ; 13.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL1      ; 13.585 ; 13.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 10.187 ; 10.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 10.955 ; 10.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 9.094  ; 9.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 10.518 ; 10.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 9.708  ; 9.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 9.828  ; 9.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 9.059  ; 9.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 10.976 ; 10.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 9.174  ; 9.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 7.085  ; 7.085  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 9.537  ; 9.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 6.452  ; 6.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.277  ; 7.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 6.240  ; 6.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 6.514  ; 6.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 5.942  ; 5.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 5.042  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 5.654  ; 5.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 6.195  ; 6.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 7.924  ; 7.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 8.548  ; 8.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.086  ; 6.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 5.808  ; 5.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 5.539  ; 5.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 4.925  ; 4.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 4.626  ; 4.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 10.386 ; 10.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 9.542  ; 9.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 9.070  ; 9.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 10.105 ; 10.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 7.783  ; 7.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 6.916  ; 6.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 13.775 ; 13.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 9.148  ; 9.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 8.840  ; 9.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 9.489  ; 9.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 8.843  ; 9.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 8.933  ; 9.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 8.840  ; 9.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 8.750  ; 9.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 10.736 ; 11.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 11.291 ; 10.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 8.472  ; 7.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 7.304  ; 7.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 6.883  ; 6.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 8.334  ; 8.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 7.239  ; 7.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 7.907  ; 7.907  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 6.883  ; 6.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 8.089  ; 8.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.933  ; 6.933  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.371  ; 7.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.732  ; 6.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.475  ; 7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.955  ; 7.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 6.122  ; 6.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 8.734  ; 8.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 15.309 ; 15.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 14.868 ; 14.868 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 14.659 ; 14.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 15.720 ; 15.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 14.653 ; 14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 16.141 ; 16.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 13.729 ; 13.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 13.139 ; 13.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 10.784 ; 10.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.894  ; 9.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 8.734  ; 8.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 8.982  ; 8.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 9.150  ; 9.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.253 ; 10.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 9.150  ; 9.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 11.545 ; 10.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 9.735  ; 10.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.836  ; 9.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 10.183 ; 10.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 11.476 ; 11.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.037 ; 11.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.061 ; 11.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 11.716 ; 11.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 11.900 ; 11.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 11.187 ; 11.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.200 ; 12.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 9.836  ; 9.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 10.728 ; 10.728 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 12.976 ; 12.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 10.028 ; 10.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 11.444 ; 11.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 10.294 ; 10.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 9.888  ; 9.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.938 ; 10.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 11.342 ; 12.052 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 9.830  ; 9.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 11.535 ; 12.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 9.820  ; 9.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 13.610 ; 12.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 12.339 ; 13.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_WEn        ; CLK_PLL1      ; 11.650 ; 11.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 7.504  ; 7.504  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 11.118 ; 11.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 11.155 ; 11.773 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 9.718  ; 9.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 11.112 ; 11.112 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 10.911 ; 10.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 8.413  ; 8.413  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 6.989  ; 6.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 5.855  ; 5.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 6.411  ; 6.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 5.904  ; 5.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 6.239  ; 6.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 6.178  ; 6.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 6.180  ; 6.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 6.067  ; 6.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 6.414  ; 6.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 5.462  ; 5.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 5.238  ; 5.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 6.389  ; 6.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 8.448  ; 8.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 8.626  ; 8.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 5.924  ; 5.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 6.263  ; 6.263  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 7.152  ; 7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 6.112  ; 6.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 7.118  ; 7.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 7.954  ; 7.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 5.992  ; 5.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 11.748 ; 11.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 8.878  ; 8.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 9.245  ; 9.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 11.552 ; 11.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 13.648 ; 13.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 13.638 ; 13.638 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 8.245  ; 8.245  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 10.563 ; 10.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 11.512 ; 11.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 15.107 ; 15.107 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 15.959 ; 15.959 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 15.107 ; 15.107 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 15.230 ; 15.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 16.009 ; 16.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 15.610 ; 15.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 15.652 ; 15.652 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 15.530 ; 15.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 15.209 ; 15.209 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 14.848 ; 14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 18.913 ; 18.913 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 17.636 ; 17.464 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 17.435 ; 17.435 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 17.425 ; 17.425 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 16.007 ; 16.007 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 18.499 ; 18.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 15.586 ; 15.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 16.010 ; 16.010 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 16.503 ; 16.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 17.496 ; 17.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 17.371 ; 17.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 19.610 ; 19.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 16.130 ; 16.130 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 19.586 ; 19.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 14.848 ; 14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 15.238 ; 15.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 10.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 9.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 13.741 ; 13.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 14.960 ; 14.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 9.320  ; 9.148  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 9.012  ; 8.840  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 9.661  ; 9.489  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 9.015  ; 8.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 9.136  ; 8.933  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 9.012  ; 8.840  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 9.301  ; 8.750  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 11.321 ; 10.736 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 10.706 ; 11.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 7.759  ; 8.472  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 8.089  ; 8.089  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 8.734  ; 8.734  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 16.232 ; 16.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 15.980 ; 15.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 15.468 ; 15.468 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 16.034 ; 16.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 16.080 ; 16.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 17.191 ; 17.191 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 14.665 ; 14.665 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 16.009 ; 16.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 14.390 ; 14.390 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 10.784 ; 10.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.894  ; 9.894  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 8.734  ; 8.734  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 9.367  ; 9.322  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 10.376 ; 10.419 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 10.419 ; 10.419 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 10.376 ; 11.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 10.551 ; 11.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 10.729 ; 9.735  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 12.214 ; 12.214 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 14.302 ; 14.302 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 15.693 ; 15.521 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 15.147 ; 15.147 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 14.949 ; 14.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 16.563 ; 16.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 15.137 ; 15.137 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 15.110 ; 15.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 14.945 ; 14.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 15.142 ; 14.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 15.630 ; 15.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.100 ; 16.944 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 15.398 ; 15.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 15.949 ; 15.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 16.276 ; 16.276 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.272 ; 12.272 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 12.214 ; 12.214 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.052 ; 11.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 9.630  ; 9.830  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 12.245 ; 11.535 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 9.620  ; 9.820  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 12.616 ; 13.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 13.333 ; 12.339 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 10.106 ; 10.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 11.738 ; 11.709 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 11.779 ; 11.155 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 10.969 ; 10.886 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 10.085 ; 10.085 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 12.051 ; 11.911 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 10.911 ; 10.911 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 7.954  ; 7.954  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 8.412  ; 8.412  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 8.402  ; 8.402  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 9.251  ; 9.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 11.353 ; 11.353 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 9.740  ; 9.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 10.032 ; 10.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 9.746  ; 9.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 9.975  ; 9.975  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 10.105 ; 10.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 10.518 ; 10.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 10.821 ; 10.821 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 10.009 ; 10.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 10.270 ; 10.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 11.076 ; 11.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 9.251  ; 9.251  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 9.756  ; 9.756  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 9.418  ; 9.418  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 10.769 ; 10.769 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 9.690  ; 9.690  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 9.465  ; 9.465  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 10.902 ; 10.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 10.219 ; 10.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 10.017 ; 10.017 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 10.714 ; 10.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 12.141 ; 12.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 10.069 ; 10.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.245  ; 8.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 8.118  ; 8.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 5.081  ; 5.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 9.754  ; 9.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 6.438  ; 6.438  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 6.288  ; 6.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 8.029  ; 8.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.910  ; 7.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.684  ; 7.684  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 8.958  ; 8.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.596  ; 6.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.288  ; 6.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 7.558  ; 7.558  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.811  ; 7.811  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 8.031  ; 8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 8.097  ; 8.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 11.507 ; 11.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 11.799 ; 11.799 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 11.507 ; 11.507 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 14.116 ; 14.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 10.938 ; 10.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 12.433 ; 12.433 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 12.859 ; 12.859 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 11.263 ; 11.263 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 10.938 ; 10.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 12.875 ; 12.875 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 12.425 ; 12.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 12.425 ; 12.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 12.832 ; 12.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 13.133 ; 13.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 13.585 ; 13.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 10.187 ; 10.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 10.955 ; 10.955 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 9.094  ; 9.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 10.518 ; 10.518 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 9.708  ; 9.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 9.828  ; 9.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 9.059  ; 9.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 10.976 ; 10.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 9.174  ; 9.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.085  ; 7.085  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 9.537  ; 9.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.452  ; 6.452  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.277  ; 7.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 6.240  ; 6.240  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.514  ; 6.514  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 5.942  ; 5.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 5.042  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 5.654  ; 5.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 6.195  ; 6.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 7.924  ; 7.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 8.548  ; 8.548  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 7.920  ; 7.920  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.086  ; 6.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 5.808  ; 5.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 5.539  ; 5.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 4.925  ; 4.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 4.626  ; 4.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 10.386 ; 10.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 9.542  ; 9.993  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 9.070  ; 9.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 10.105 ; 10.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 7.783  ; 7.783  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 6.916  ; 6.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 7.748  ; 7.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 13.775 ; 13.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 9.148  ; 9.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 8.840  ; 9.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 9.489  ; 9.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 8.843  ; 9.015  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 8.933  ; 9.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 8.840  ; 9.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 8.750  ; 9.301  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 10.736 ; 11.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.291 ; 10.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 8.472  ; 7.759  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 7.304  ; 7.304  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 6.883  ; 6.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 8.334  ; 8.334  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 7.239  ; 7.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 7.907  ; 7.907  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 6.883  ; 6.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.089  ; 8.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.933  ; 6.933  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.371  ; 7.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.732  ; 6.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.475  ; 7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.955  ; 7.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 6.122  ; 6.122  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 8.734  ; 8.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 15.309 ; 15.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 14.868 ; 14.868 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 14.659 ; 14.659 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 15.720 ; 15.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 14.653 ; 14.653 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 16.141 ; 16.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 13.729 ; 13.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 15.070 ; 15.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 13.139 ; 13.139 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 10.784 ; 10.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.894  ; 9.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 8.734  ; 8.734  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 8.982  ; 8.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 9.150  ; 9.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.253 ; 10.253 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 9.150  ; 9.150  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 11.545 ; 10.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 9.735  ; 10.729 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.836  ; 9.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 10.183 ; 10.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 11.476 ; 11.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 11.037 ; 11.037 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 11.061 ; 11.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 11.716 ; 11.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 11.900 ; 11.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 11.187 ; 11.187 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.200 ; 12.200 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 9.836  ; 9.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 10.728 ; 10.728 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 12.976 ; 12.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 10.028 ; 10.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 11.444 ; 11.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 10.294 ; 10.294 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 9.888  ; 9.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.938 ; 10.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 11.342 ; 12.052 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 9.830  ; 9.630  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 11.535 ; 12.245 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 9.820  ; 9.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 13.610 ; 12.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 12.339 ; 13.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 11.650 ; 11.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 7.504  ; 7.504  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 11.118 ; 11.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 11.155 ; 11.773 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 9.718  ; 9.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 9.090  ; 9.090  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 11.112 ; 11.112 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 10.911 ; 10.911 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 8.413  ; 8.413  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 6.989  ; 6.989  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 5.855  ; 5.855  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 6.411  ; 6.411  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 5.904  ; 5.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 6.239  ; 6.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 6.178  ; 6.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 6.180  ; 6.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 6.067  ; 6.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 6.414  ; 6.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 5.462  ; 5.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 5.238  ; 5.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 6.389  ; 6.389  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 8.448  ; 8.448  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 8.626  ; 8.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 5.924  ; 5.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 6.263  ; 6.263  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 5.851  ; 5.851  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 7.152  ; 7.152  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 6.112  ; 6.112  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 7.118  ; 7.118  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 7.954  ; 7.954  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 5.992  ; 5.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 11.748 ; 11.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 8.878  ; 8.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 9.245  ; 9.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 11.552 ; 11.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 13.648 ; 13.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 13.638 ; 13.638 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 8.245  ; 8.245  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 10.563 ; 10.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 11.512 ; 11.512 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 15.107 ; 15.107 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 15.959 ; 15.959 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 15.107 ; 15.107 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 15.230 ; 15.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 16.009 ; 16.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 15.610 ; 15.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.652 ; 15.652 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 15.530 ; 15.530 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 15.209 ; 15.209 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 14.848 ; 14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 18.913 ; 18.913 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 17.636 ; 17.464 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 17.435 ; 17.435 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 17.425 ; 17.425 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 16.007 ; 16.007 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 18.499 ; 18.499 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 15.586 ; 15.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 16.010 ; 16.010 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.503 ; 16.222 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 17.496 ; 17.245 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 17.371 ; 17.215 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 19.610 ; 19.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 16.130 ; 16.130 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 19.586 ; 19.586 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 14.848 ; 14.848 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 15.238 ; 15.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 10.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 9.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 13.741 ; 13.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 14.960 ; 14.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 9.320  ; 9.148  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 9.012  ; 8.840  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 9.661  ; 9.489  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 9.015  ; 8.843  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 9.136  ; 8.933  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 9.012  ; 8.840  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 9.301  ; 8.750  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 11.321 ; 10.736 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 10.706 ; 11.291 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 7.759  ; 8.472  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.089  ; 8.089  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 8.734  ; 8.734  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 16.232 ; 16.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 15.980 ; 15.980 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 15.468 ; 15.468 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 16.034 ; 16.034 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 16.080 ; 16.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 17.191 ; 17.191 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 14.665 ; 14.665 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 16.009 ; 16.009 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 14.390 ; 14.390 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 10.784 ; 10.784 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.894  ; 9.894  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 8.734  ; 8.734  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 9.367  ; 9.322  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 10.376 ; 10.419 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 10.419 ; 10.419 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 10.376 ; 11.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 10.551 ; 11.545 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 10.729 ; 9.735  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 12.214 ; 12.214 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 14.302 ; 14.302 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 15.693 ; 15.521 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 15.147 ; 15.147 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 14.949 ; 14.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 16.563 ; 16.563 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 15.137 ; 15.137 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 15.110 ; 15.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 14.945 ; 14.945 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 15.142 ; 14.861 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 15.630 ; 15.379 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.100 ; 16.944 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 15.398 ; 15.398 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 15.949 ; 15.949 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 16.276 ; 16.276 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.272 ; 12.272 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.214 ; 12.214 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.052 ; 11.342 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 9.630  ; 9.830  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 12.245 ; 11.535 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 9.620  ; 9.820  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 12.616 ; 13.610 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 13.333 ; 12.339 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 10.106 ; 10.077 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 11.738 ; 11.709 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 11.779 ; 11.155 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 10.969 ; 10.886 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 10.085 ; 10.085 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 12.051 ; 11.911 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 10.911 ; 10.911 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 7.954  ; 7.954  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 12.515 ; 12.515 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 12.505 ; 12.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 10.903 ; 10.903 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BERRn          ; CLK_PLL1      ; 6.590  ; 6.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BUTTONn        ; CLK_PLL1      ; 9.637  ; 9.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 10.379 ; 10.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 13.974 ; 13.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 14.826 ; 14.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 13.974 ; 13.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 14.097 ; 14.097 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 14.876 ; 14.876 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 14.477 ; 14.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 14.519 ; 14.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 14.397 ; 14.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 14.076 ; 14.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 8.635  ; 8.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 8.925  ; 8.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 8.987  ; 8.987  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 8.635  ; 8.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 8.884  ; 8.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 8.332  ; 8.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 8.995  ; 8.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 9.323  ; 9.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 8.332  ; 8.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 8.665  ; 8.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 9.821  ; 9.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 7.913  ; 7.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 7.913  ; 7.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 9.467  ; 9.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 8.230  ; 8.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_LDACn      ; CLK_PLL1      ; 8.106  ; 8.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SCLK       ; CLK_PLL1      ; 9.220  ; 9.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SYNCn      ; CLK_PLL1      ; 5.743  ; 5.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 11.897 ; 11.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 16.009 ; 16.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 12.734 ; 12.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 13.874 ; 13.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 14.242 ; 14.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 12.622 ; 12.622 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 15.646 ; 15.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 11.897 ; 11.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 13.673 ; 13.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 13.048 ; 13.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 14.748 ; 14.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 14.441 ; 14.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 15.873 ; 15.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 13.060 ; 13.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 15.532 ; 15.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 12.773 ; 12.773 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 13.826 ; 13.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 5.776  ; 5.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_CEn      ; CLK_PLL1      ; 13.990 ; 13.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_OEn      ; CLK_PLL1      ; 15.209 ; 15.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC          ; CLK_PLL1      ; 7.077  ; 7.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS0n       ; CLK_PLL1      ; 9.079  ; 9.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS1n       ; CLK_PLL1      ; 9.226  ; 9.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 10.183 ; 10.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 9.537  ; 9.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IORDn      ; CLK_PLL1      ; 9.658  ; 9.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IOWRn      ; CLK_PLL1      ; 9.534  ; 9.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RHn        ; CLK_PLL1      ; 9.151  ; 9.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RLn        ; CLK_PLL1      ; 11.180 ; 11.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WEn        ; CLK_PLL1      ; 11.150 ; 11.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WL         ; CLK_PLL1      ; 8.194  ; 8.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 11.643 ; 11.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 4.955  ; 4.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 5.128  ; 5.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PADRSTn        ; CLK_PLL1      ; 5.892  ; 5.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 8.104  ; 8.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 9.347  ; 9.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 8.104  ; 8.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 9.295  ; 9.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 8.359  ; 8.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 10.869 ; 10.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 9.667  ; 9.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 9.799  ; 9.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 10.233 ; 10.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 9.761  ; 9.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 9.868  ; 9.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 9.133  ; 9.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 9.377  ; 9.377  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 9.094  ; 9.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 10.157 ; 10.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 8.370  ; 8.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 7.552  ; 7.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 10.197 ; 10.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 11.398 ; 11.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 10.791 ; 10.791 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 11.586 ; 11.586 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 11.766 ; 11.766 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 13.178 ; 13.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.284 ; 12.284 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 11.421 ; 11.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.608 ; 12.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 11.687 ; 11.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.882 ; 12.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.170 ; 14.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 11.661 ; 11.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 12.879 ; 12.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 12.222 ; 12.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 10.197 ; 10.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 10.802 ; 10.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 12.582 ; 12.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 10.870 ; 10.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 12.775 ; 12.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 10.860 ; 10.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 8.119  ; 8.119  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 7.845  ; 7.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 8.677  ; 8.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 6.823  ; 6.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM0n          ; CLK_PLL1      ; 8.886  ; 8.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM1n          ; CLK_PLL1      ; 10.461 ; 10.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM2n          ; CLK_PLL1      ; 12.028 ; 12.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM3n          ; CLK_PLL1      ; 10.077 ; 10.077 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM4n          ; CLK_PLL1      ; 9.193  ; 9.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM5n          ; CLK_PLL1      ; 10.455 ; 10.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM6n          ; CLK_PLL1      ; 10.019 ; 10.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 11.508 ; 11.508 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC          ; CLK_PLL1      ; 7.604  ; 7.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 12.515 ; 12.515 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 12.505 ; 12.505 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 10.903 ; 10.903 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.590  ; 6.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 9.637  ; 9.637  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 10.379 ; 10.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 13.974 ; 13.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 14.826 ; 14.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 13.974 ; 13.974 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 14.097 ; 14.097 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 14.876 ; 14.876 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 14.477 ; 14.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 14.519 ; 14.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 14.397 ; 14.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 14.076 ; 14.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 8.635  ; 8.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 8.925  ; 8.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 8.987  ; 8.987  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 8.635  ; 8.635  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 8.884  ; 8.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 8.332  ; 8.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 8.995  ; 8.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 9.323  ; 9.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 8.332  ; 8.332  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 8.665  ; 8.665  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 9.821  ; 9.821  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 7.913  ; 7.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 7.913  ; 7.913  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 9.467  ; 9.467  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 8.230  ; 8.230  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 8.836  ; 8.836  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 8.106  ; 8.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 9.220  ; 9.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 5.743  ; 5.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 11.897 ; 11.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.009 ; 16.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 12.734 ; 12.734 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 13.874 ; 13.874 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 14.242 ; 14.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.622 ; 12.622 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 15.646 ; 15.646 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 11.897 ; 11.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.673 ; 13.673 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 13.048 ; 13.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.748 ; 14.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.441 ; 14.441 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.873 ; 15.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.060 ; 13.060 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.532 ; 15.532 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 12.773 ; 12.773 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 13.826 ; 13.826 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 5.776  ; 5.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 13.990 ; 13.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 15.209 ; 15.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 7.077  ; 7.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 9.079  ; 9.079  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 9.226  ; 9.226  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 10.183 ; 10.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 9.537  ; 9.537  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 9.658  ; 9.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 9.534  ; 9.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 9.151  ; 9.151  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 11.180 ; 11.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 11.150 ; 11.150 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 8.194  ; 8.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 11.643 ; 11.643 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 4.955  ; 4.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 5.128  ; 5.128  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 5.892  ; 5.892  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 8.104  ; 8.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 9.347  ; 9.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 8.104  ; 8.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 9.295  ; 9.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 8.359  ; 8.359  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 10.869 ; 10.869 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 9.667  ; 9.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 9.799  ; 9.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 10.233 ; 10.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 9.761  ; 9.761  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 9.868  ; 9.868  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 9.133  ; 9.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 9.377  ; 9.377  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 9.094  ; 9.094  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 8.397  ; 8.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 10.157 ; 10.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 8.370  ; 8.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 7.552  ; 7.552  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 10.197 ; 10.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 11.398 ; 11.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 10.791 ; 10.791 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 11.586 ; 11.586 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 11.766 ; 11.766 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 13.178 ; 13.178 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 12.284 ; 12.284 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 11.421 ; 11.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.608 ; 12.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 11.687 ; 11.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.882 ; 12.882 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.170 ; 14.170 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 11.661 ; 11.661 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 12.879 ; 12.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.222 ; 12.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 10.197 ; 10.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 10.802 ; 10.802 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 12.582 ; 12.582 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 10.870 ; 10.870 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 12.775 ; 12.775 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 10.860 ; 10.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 8.119  ; 8.119  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 7.845  ; 7.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 8.677  ; 8.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 6.823  ; 6.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 8.886  ; 8.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 10.461 ; 10.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 12.028 ; 12.028 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 10.077 ; 10.077 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 9.193  ; 9.193  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 10.455 ; 10.455 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 10.019 ; 10.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 11.508 ; 11.508 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 7.604  ; 7.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 8.271  ; 8.271  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CLK_AUX        ; CLK_PLL2      ; 2.896  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL2      ; 12.582 ; 12.582 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL2      ; 12.874 ; 12.874 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL2      ; 14.453 ; 14.453 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL2      ; 12.582 ; 12.582 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL2      ; 15.191 ; 15.191 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL2      ; 12.013 ; 12.013 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL2      ; 13.508 ; 13.508 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL2      ; 13.934 ; 13.934 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL2      ; 12.338 ; 12.338 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL2      ; 12.013 ; 12.013 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL2      ; 13.950 ; 13.950 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL2      ; 13.500 ; 13.500 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL2      ; 13.500 ; 13.500 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL2      ; 13.907 ; 13.907 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL2      ; 14.208 ; 14.208 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL2      ; 14.660 ; 14.660 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL2      ; 6.475  ; 6.475  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ; 6.553  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL2      ; 21.440 ; 21.440 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL2      ; 24.630 ; 24.630 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL2      ; 23.455 ; 23.455 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL2      ; 21.509 ; 21.509 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL2      ; 22.341 ; 22.341 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL2      ; 21.440 ; 21.440 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL2      ; 24.216 ; 24.216 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL2      ; 21.735 ; 21.735 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL2      ; 22.863 ; 22.863 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL2      ; 22.608 ; 22.608 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL2      ; 24.691 ; 24.691 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL2      ; 23.832 ; 23.832 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL2      ; 14.850 ; 14.850 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL2      ; 19.221 ; 19.221 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL2      ; 20.019 ; 20.019 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL2      ; 21.512 ; 21.512 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL2      ; 19.221 ; 19.221 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL2      ; 19.865 ; 19.865 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL2      ; 21.996 ; 21.996 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL2      ; 20.854 ; 20.854 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL2      ; 21.259 ; 21.259 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL2      ; 21.798 ; 21.798 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL2      ; 21.247 ; 21.247 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL2      ; 22.825 ; 22.825 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL2      ; 23.561 ; 23.561 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL2      ; 12.823 ; 12.823 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ; 8.302  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ; 8.302  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL2      ;        ; 2.896  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ;        ; 6.553  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ;        ; 8.302  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ;        ; 8.302  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ADR[1]       ; DATA[0]       ; 31.407 ; 31.407 ; 31.407 ; 31.407 ;
; ADR[1]       ; DATA[1]       ; 30.877 ; 30.877 ; 30.877 ; 30.877 ;
; ADR[1]       ; DATA[2]       ; 29.779 ; 29.779 ; 29.779 ; 29.779 ;
; ADR[1]       ; DATA[3]       ; 32.365 ; 32.365 ; 32.365 ; 32.365 ;
; ADR[1]       ; DATA[4]       ; 28.591 ; 28.591 ; 28.591 ; 28.591 ;
; ADR[1]       ; DATA[5]       ; 30.699 ; 30.699 ; 30.699 ; 30.699 ;
; ADR[1]       ; DATA[6]       ; 28.327 ; 28.327 ; 28.327 ; 28.327 ;
; ADR[1]       ; DATA[7]       ; 30.772 ; 30.772 ; 30.772 ; 30.772 ;
; ADR[1]       ; DATA[8]       ; 29.631 ; 29.631 ; 29.631 ; 29.631 ;
; ADR[1]       ; DATA[9]       ; 30.410 ; 30.410 ; 30.410 ; 30.410 ;
; ADR[1]       ; DATA[10]      ; 30.492 ; 30.492 ; 30.492 ; 30.492 ;
; ADR[1]       ; DATA[11]      ; 32.288 ; 32.288 ; 32.288 ; 32.288 ;
; ADR[1]       ; DATA[12]      ; 30.877 ; 30.877 ; 30.877 ; 30.877 ;
; ADR[1]       ; DATA[13]      ; 31.352 ; 31.352 ; 31.352 ; 31.352 ;
; ADR[1]       ; DATA[14]      ; 30.772 ; 30.772 ; 30.772 ; 30.772 ;
; ADR[1]       ; DATA[15]      ; 31.497 ; 31.497 ; 31.497 ; 31.497 ;
; ADR[1]       ; RAM_DATA[0]   ; 26.796 ; 26.796 ; 26.796 ; 26.796 ;
; ADR[1]       ; RAM_DATA[1]   ; 28.934 ; 28.934 ; 28.934 ; 28.934 ;
; ADR[1]       ; RAM_DATA[2]   ; 27.491 ; 27.491 ; 27.491 ; 27.491 ;
; ADR[1]       ; RAM_DATA[3]   ; 29.889 ; 29.889 ; 29.889 ; 29.889 ;
; ADR[1]       ; RAM_DATA[4]   ; 29.147 ; 29.147 ; 29.147 ; 29.147 ;
; ADR[1]       ; RAM_DATA[5]   ; 27.337 ; 27.337 ; 27.337 ; 27.337 ;
; ADR[1]       ; RAM_DATA[6]   ; 27.851 ; 27.851 ; 27.851 ; 27.851 ;
; ADR[1]       ; RAM_DATA[7]   ; 29.707 ; 29.707 ; 29.707 ; 29.707 ;
; ADR[1]       ; RAM_DATA[8]   ; 28.270 ; 28.270 ; 28.270 ; 28.270 ;
; ADR[1]       ; RAM_DATA[9]   ; 28.544 ; 28.544 ; 28.544 ; 28.544 ;
; ADR[1]       ; RAM_DATA[10]  ; 30.221 ; 30.221 ; 30.221 ; 30.221 ;
; ADR[1]       ; RAM_DATA[11]  ; 28.076 ; 28.076 ; 28.076 ; 28.076 ;
; ADR[1]       ; RAM_DATA[12]  ; 30.696 ; 30.696 ; 30.696 ; 30.696 ;
; ADR[1]       ; RAM_DATA[13]  ; 28.042 ; 28.042 ; 28.042 ; 28.042 ;
; ADR[1]       ; RAM_DATA[14]  ; 28.196 ; 28.196 ; 28.196 ; 28.196 ;
; ADR[1]       ; RAM_DATA[15]  ; 28.473 ; 28.473 ; 28.473 ; 28.473 ;
; ADR[2]       ; DATA[0]       ; 32.342 ; 32.366 ; 32.366 ; 32.342 ;
; ADR[2]       ; DATA[1]       ; 31.812 ; 31.835 ; 31.835 ; 31.812 ;
; ADR[2]       ; DATA[2]       ; 30.714 ; 30.753 ; 30.753 ; 30.714 ;
; ADR[2]       ; DATA[3]       ; 33.595 ; 33.595 ; 33.595 ; 33.595 ;
; ADR[2]       ; DATA[4]       ; 29.821 ; 29.821 ; 29.821 ; 29.821 ;
; ADR[2]       ; DATA[5]       ; 31.929 ; 31.929 ; 31.929 ; 31.929 ;
; ADR[2]       ; DATA[6]       ; 29.462 ; 29.462 ; 29.462 ; 29.462 ;
; ADR[2]       ; DATA[7]       ; 32.002 ; 32.002 ; 32.002 ; 32.002 ;
; ADR[2]       ; DATA[8]       ; 30.566 ; 30.590 ; 30.590 ; 30.566 ;
; ADR[2]       ; DATA[9]       ; 31.345 ; 31.368 ; 31.368 ; 31.345 ;
; ADR[2]       ; DATA[10]      ; 31.427 ; 31.466 ; 31.466 ; 31.427 ;
; ADR[2]       ; DATA[11]      ; 33.518 ; 33.518 ; 33.518 ; 33.518 ;
; ADR[2]       ; DATA[12]      ; 32.107 ; 32.107 ; 32.107 ; 32.107 ;
; ADR[2]       ; DATA[13]      ; 32.582 ; 32.582 ; 32.582 ; 32.582 ;
; ADR[2]       ; DATA[14]      ; 32.002 ; 32.002 ; 32.002 ; 32.002 ;
; ADR[2]       ; DATA[15]      ; 32.727 ; 32.727 ; 32.727 ; 32.727 ;
; ADR[2]       ; RAM_DATA[0]   ; 27.731 ; 27.755 ; 27.755 ; 27.731 ;
; ADR[2]       ; RAM_DATA[1]   ; 29.869 ; 29.892 ; 29.892 ; 29.869 ;
; ADR[2]       ; RAM_DATA[2]   ; 28.426 ; 28.465 ; 28.465 ; 28.426 ;
; ADR[2]       ; RAM_DATA[3]   ; 31.119 ; 31.119 ; 31.119 ; 31.119 ;
; ADR[2]       ; RAM_DATA[4]   ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; ADR[2]       ; RAM_DATA[5]   ; 28.567 ; 28.567 ; 28.567 ; 28.567 ;
; ADR[2]       ; RAM_DATA[6]   ; 28.986 ; 28.986 ; 28.986 ; 28.986 ;
; ADR[2]       ; RAM_DATA[7]   ; 30.937 ; 30.937 ; 30.937 ; 30.937 ;
; ADR[2]       ; RAM_DATA[8]   ; 29.205 ; 29.229 ; 29.229 ; 29.205 ;
; ADR[2]       ; RAM_DATA[9]   ; 29.479 ; 29.502 ; 29.502 ; 29.479 ;
; ADR[2]       ; RAM_DATA[10]  ; 31.156 ; 31.195 ; 31.195 ; 31.156 ;
; ADR[2]       ; RAM_DATA[11]  ; 29.306 ; 29.306 ; 29.306 ; 29.306 ;
; ADR[2]       ; RAM_DATA[12]  ; 31.926 ; 31.926 ; 31.926 ; 31.926 ;
; ADR[2]       ; RAM_DATA[13]  ; 29.272 ; 29.272 ; 29.272 ; 29.272 ;
; ADR[2]       ; RAM_DATA[14]  ; 29.426 ; 29.426 ; 29.426 ; 29.426 ;
; ADR[2]       ; RAM_DATA[15]  ; 29.703 ; 29.703 ; 29.703 ; 29.703 ;
; ADR[3]       ; DATA[0]       ; 31.248 ; 30.977 ; 30.977 ; 31.248 ;
; ADR[3]       ; DATA[1]       ; 30.717 ; 30.447 ; 30.447 ; 30.717 ;
; ADR[3]       ; DATA[2]       ; 29.620 ; 29.349 ; 29.349 ; 29.620 ;
; ADR[3]       ; DATA[3]       ; 31.875 ; 31.875 ; 31.875 ; 31.875 ;
; ADR[3]       ; DATA[4]       ; 28.101 ; 28.101 ; 28.101 ; 28.101 ;
; ADR[3]       ; DATA[5]       ; 30.321 ; 30.321 ; 30.321 ; 30.321 ;
; ADR[3]       ; DATA[6]       ; 28.284 ; 28.284 ; 28.284 ; 28.284 ;
; ADR[3]       ; DATA[7]       ; 30.282 ; 30.282 ; 30.282 ; 30.282 ;
; ADR[3]       ; DATA[8]       ; 29.472 ; 29.201 ; 29.201 ; 29.472 ;
; ADR[3]       ; DATA[9]       ; 30.250 ; 29.980 ; 29.980 ; 30.250 ;
; ADR[3]       ; DATA[10]      ; 30.333 ; 30.062 ; 30.062 ; 30.333 ;
; ADR[3]       ; DATA[11]      ; 31.798 ; 31.798 ; 31.798 ; 31.798 ;
; ADR[3]       ; DATA[12]      ; 30.387 ; 30.387 ; 30.387 ; 30.387 ;
; ADR[3]       ; DATA[13]      ; 30.862 ; 30.862 ; 30.862 ; 30.862 ;
; ADR[3]       ; DATA[14]      ; 30.282 ; 30.282 ; 30.282 ; 30.282 ;
; ADR[3]       ; DATA[15]      ; 31.007 ; 31.007 ; 31.007 ; 31.007 ;
; ADR[3]       ; RAM_DATA[0]   ; 26.637 ; 26.366 ; 26.366 ; 26.637 ;
; ADR[3]       ; RAM_DATA[1]   ; 28.774 ; 28.504 ; 28.504 ; 28.774 ;
; ADR[3]       ; RAM_DATA[2]   ; 27.332 ; 27.061 ; 27.061 ; 27.332 ;
; ADR[3]       ; RAM_DATA[3]   ; 29.399 ; 29.399 ; 29.399 ; 29.399 ;
; ADR[3]       ; RAM_DATA[4]   ; 28.657 ; 28.657 ; 28.657 ; 28.657 ;
; ADR[3]       ; RAM_DATA[5]   ; 26.959 ; 26.959 ; 26.959 ; 26.959 ;
; ADR[3]       ; RAM_DATA[6]   ; 27.808 ; 27.808 ; 27.808 ; 27.808 ;
; ADR[3]       ; RAM_DATA[7]   ; 29.217 ; 29.217 ; 29.217 ; 29.217 ;
; ADR[3]       ; RAM_DATA[8]   ; 28.111 ; 27.840 ; 27.840 ; 28.111 ;
; ADR[3]       ; RAM_DATA[9]   ; 28.384 ; 28.114 ; 28.114 ; 28.384 ;
; ADR[3]       ; RAM_DATA[10]  ; 30.062 ; 29.791 ; 29.791 ; 30.062 ;
; ADR[3]       ; RAM_DATA[11]  ; 27.586 ; 27.586 ; 27.586 ; 27.586 ;
; ADR[3]       ; RAM_DATA[12]  ; 30.206 ; 30.206 ; 30.206 ; 30.206 ;
; ADR[3]       ; RAM_DATA[13]  ; 27.552 ; 27.552 ; 27.552 ; 27.552 ;
; ADR[3]       ; RAM_DATA[14]  ; 27.706 ; 27.706 ; 27.706 ; 27.706 ;
; ADR[3]       ; RAM_DATA[15]  ; 27.983 ; 27.983 ; 27.983 ; 27.983 ;
; ADR[4]       ; DATA[0]       ; 31.400 ; 31.400 ; 31.400 ; 31.400 ;
; ADR[4]       ; DATA[1]       ; 30.870 ; 30.870 ; 30.870 ; 30.870 ;
; ADR[4]       ; DATA[2]       ; 29.772 ; 29.772 ; 29.772 ; 29.772 ;
; ADR[4]       ; DATA[3]       ; 32.481 ; 32.481 ; 32.481 ; 32.481 ;
; ADR[4]       ; DATA[4]       ; 28.707 ; 28.707 ; 28.707 ; 28.707 ;
; ADR[4]       ; DATA[5]       ; 30.815 ; 30.815 ; 30.815 ; 30.815 ;
; ADR[4]       ; DATA[6]       ; 28.348 ; 28.348 ; 28.348 ; 28.348 ;
; ADR[4]       ; DATA[7]       ; 30.888 ; 30.888 ; 30.888 ; 30.888 ;
; ADR[4]       ; DATA[8]       ; 29.624 ; 29.624 ; 29.624 ; 29.624 ;
; ADR[4]       ; DATA[9]       ; 30.403 ; 30.403 ; 30.403 ; 30.403 ;
; ADR[4]       ; DATA[10]      ; 30.485 ; 30.485 ; 30.485 ; 30.485 ;
; ADR[4]       ; DATA[11]      ; 32.404 ; 32.404 ; 32.404 ; 32.404 ;
; ADR[4]       ; DATA[12]      ; 30.993 ; 30.993 ; 30.993 ; 30.993 ;
; ADR[4]       ; DATA[13]      ; 31.468 ; 31.468 ; 31.468 ; 31.468 ;
; ADR[4]       ; DATA[14]      ; 30.888 ; 30.888 ; 30.888 ; 30.888 ;
; ADR[4]       ; DATA[15]      ; 31.613 ; 31.613 ; 31.613 ; 31.613 ;
; ADR[4]       ; RAM_DATA[0]   ; 26.789 ; 26.789 ; 26.789 ; 26.789 ;
; ADR[4]       ; RAM_DATA[1]   ; 28.927 ; 28.927 ; 28.927 ; 28.927 ;
; ADR[4]       ; RAM_DATA[2]   ; 27.484 ; 27.484 ; 27.484 ; 27.484 ;
; ADR[4]       ; RAM_DATA[3]   ; 30.005 ; 30.005 ; 30.005 ; 30.005 ;
; ADR[4]       ; RAM_DATA[4]   ; 29.263 ; 29.263 ; 29.263 ; 29.263 ;
; ADR[4]       ; RAM_DATA[5]   ; 27.453 ; 27.453 ; 27.453 ; 27.453 ;
; ADR[4]       ; RAM_DATA[6]   ; 27.872 ; 27.872 ; 27.872 ; 27.872 ;
; ADR[4]       ; RAM_DATA[7]   ; 29.823 ; 29.823 ; 29.823 ; 29.823 ;
; ADR[4]       ; RAM_DATA[8]   ; 28.263 ; 28.263 ; 28.263 ; 28.263 ;
; ADR[4]       ; RAM_DATA[9]   ; 28.537 ; 28.537 ; 28.537 ; 28.537 ;
; ADR[4]       ; RAM_DATA[10]  ; 30.214 ; 30.214 ; 30.214 ; 30.214 ;
; ADR[4]       ; RAM_DATA[11]  ; 28.192 ; 28.192 ; 28.192 ; 28.192 ;
; ADR[4]       ; RAM_DATA[12]  ; 30.812 ; 30.812 ; 30.812 ; 30.812 ;
; ADR[4]       ; RAM_DATA[13]  ; 28.158 ; 28.158 ; 28.158 ; 28.158 ;
; ADR[4]       ; RAM_DATA[14]  ; 28.312 ; 28.312 ; 28.312 ; 28.312 ;
; ADR[4]       ; RAM_DATA[15]  ; 28.589 ; 28.589 ; 28.589 ; 28.589 ;
; ADR[5]       ; DATA[0]       ; 31.719 ; 31.505 ; 31.505 ; 31.719 ;
; ADR[5]       ; DATA[1]       ; 31.188 ; 30.975 ; 30.975 ; 31.188 ;
; ADR[5]       ; DATA[2]       ; 30.310 ; 29.877 ; 29.877 ; 30.310 ;
; ADR[5]       ; DATA[3]       ; 32.948 ; 32.948 ; 32.948 ; 32.948 ;
; ADR[5]       ; DATA[4]       ; 29.174 ; 29.174 ; 29.174 ; 29.174 ;
; ADR[5]       ; DATA[5]       ; 31.282 ; 31.282 ; 31.282 ; 31.282 ;
; ADR[5]       ; DATA[6]       ; 28.815 ; 28.815 ; 28.815 ; 28.815 ;
; ADR[5]       ; DATA[7]       ; 31.355 ; 31.355 ; 31.355 ; 31.355 ;
; ADR[5]       ; DATA[8]       ; 29.943 ; 29.729 ; 29.729 ; 29.943 ;
; ADR[5]       ; DATA[9]       ; 30.721 ; 30.508 ; 30.508 ; 30.721 ;
; ADR[5]       ; DATA[10]      ; 31.023 ; 30.590 ; 30.590 ; 31.023 ;
; ADR[5]       ; DATA[11]      ; 32.871 ; 32.871 ; 32.871 ; 32.871 ;
; ADR[5]       ; DATA[12]      ; 31.460 ; 31.460 ; 31.460 ; 31.460 ;
; ADR[5]       ; DATA[13]      ; 31.935 ; 31.935 ; 31.935 ; 31.935 ;
; ADR[5]       ; DATA[14]      ; 31.355 ; 31.355 ; 31.355 ; 31.355 ;
; ADR[5]       ; DATA[15]      ; 32.080 ; 32.080 ; 32.080 ; 32.080 ;
; ADR[5]       ; RAM_DATA[0]   ; 27.108 ; 26.894 ; 26.894 ; 27.108 ;
; ADR[5]       ; RAM_DATA[1]   ; 29.245 ; 29.032 ; 29.032 ; 29.245 ;
; ADR[5]       ; RAM_DATA[2]   ; 28.022 ; 27.589 ; 27.589 ; 28.022 ;
; ADR[5]       ; RAM_DATA[3]   ; 30.472 ; 30.472 ; 30.472 ; 30.472 ;
; ADR[5]       ; RAM_DATA[4]   ; 29.730 ; 29.730 ; 29.730 ; 29.730 ;
; ADR[5]       ; RAM_DATA[5]   ; 27.920 ; 27.920 ; 27.920 ; 27.920 ;
; ADR[5]       ; RAM_DATA[6]   ; 28.339 ; 28.339 ; 28.339 ; 28.339 ;
; ADR[5]       ; RAM_DATA[7]   ; 30.290 ; 30.290 ; 30.290 ; 30.290 ;
; ADR[5]       ; RAM_DATA[8]   ; 28.582 ; 28.368 ; 28.368 ; 28.582 ;
; ADR[5]       ; RAM_DATA[9]   ; 28.855 ; 28.642 ; 28.642 ; 28.855 ;
; ADR[5]       ; RAM_DATA[10]  ; 30.752 ; 30.319 ; 30.319 ; 30.752 ;
; ADR[5]       ; RAM_DATA[11]  ; 28.659 ; 28.659 ; 28.659 ; 28.659 ;
; ADR[5]       ; RAM_DATA[12]  ; 31.279 ; 31.279 ; 31.279 ; 31.279 ;
; ADR[5]       ; RAM_DATA[13]  ; 28.625 ; 28.625 ; 28.625 ; 28.625 ;
; ADR[5]       ; RAM_DATA[14]  ; 28.779 ; 28.779 ; 28.779 ; 28.779 ;
; ADR[5]       ; RAM_DATA[15]  ; 29.056 ; 29.056 ; 29.056 ; 29.056 ;
; ASn          ; ACSI_RDn      ; 22.214 ; 22.214 ; 22.214 ; 22.214 ;
; ASn          ; ACSI_WRn      ; 22.204 ; 22.204 ; 22.204 ; 22.204 ;
; ASn          ; ASn           ; 29.424 ; 29.424 ; 29.424 ; 29.424 ;
; ASn          ; BUTTONn       ; 17.200 ;        ;        ; 17.200 ;
; ASn          ; CA1_OUT       ; 20.078 ;        ;        ; 20.078 ;
; ASn          ; CD[0]         ; 28.045 ; 28.045 ; 28.045 ; 28.045 ;
; ASn          ; CD[1]         ; 27.530 ; 27.530 ; 27.530 ; 27.530 ;
; ASn          ; CD[2]         ; 26.971 ; 26.971 ; 26.971 ; 26.971 ;
; ASn          ; CD[3]         ; 28.510 ; 28.510 ; 28.510 ; 28.510 ;
; ASn          ; CD[4]         ; 27.452 ; 27.452 ; 27.452 ; 27.452 ;
; ASn          ; CD[5]         ; 26.616 ; 26.616 ; 26.616 ; 26.616 ;
; ASn          ; CD[6]         ; 29.290 ; 29.290 ; 29.290 ; 29.290 ;
; ASn          ; CD[7]         ; 26.969 ; 26.969 ; 26.969 ; 26.969 ;
; ASn          ; DATA[0]       ; 40.447 ; 40.447 ; 40.447 ; 40.447 ;
; ASn          ; DATA[1]       ; 37.848 ; 37.848 ; 37.848 ; 37.848 ;
; ASn          ; DATA[2]       ; 38.373 ; 38.686 ; 38.686 ; 38.373 ;
; ASn          ; DATA[3]       ; 39.042 ; 39.042 ; 39.042 ; 39.042 ;
; ASn          ; DATA[4]       ; 37.178 ; 37.178 ; 37.178 ; 37.178 ;
; ASn          ; DATA[5]       ; 39.074 ; 39.074 ; 39.074 ; 39.074 ;
; ASn          ; DATA[6]       ; 36.656 ; 36.656 ; 36.656 ; 36.656 ;
; ASn          ; DATA[7]       ; 38.590 ; 38.590 ; 38.590 ; 38.590 ;
; ASn          ; DATA[8]       ; 37.611 ; 37.611 ; 37.611 ; 37.611 ;
; ASn          ; DATA[9]       ; 38.091 ; 38.670 ; 38.670 ; 38.091 ;
; ASn          ; DATA[10]      ; 38.119 ; 38.119 ; 38.119 ; 38.119 ;
; ASn          ; DATA[11]      ; 40.845 ; 40.126 ; 40.126 ; 40.845 ;
; ASn          ; DATA[12]      ; 37.673 ; 38.113 ; 38.113 ; 37.673 ;
; ASn          ; DATA[13]      ; 38.817 ; 39.496 ; 39.496 ; 38.817 ;
; ASn          ; DATA[14]      ; 36.378 ; 36.378 ; 36.378 ; 36.378 ;
; ASn          ; DATA[15]      ; 37.127 ; 37.127 ; 37.127 ; 37.127 ;
; ASn          ; DTACKn        ; 30.192 ; 30.192 ; 30.192 ; 30.192 ;
; ASn          ; FC[0]         ; 30.303 ; 30.303 ; 30.303 ; 30.303 ;
; ASn          ; FC[1]         ; 29.763 ; 29.763 ; 29.763 ; 29.763 ;
; ASn          ; FC[2]         ; 29.763 ; 29.763 ; 29.763 ; 29.763 ;
; ASn          ; FLASH_CEn     ; 20.062 ;        ;        ; 20.062 ;
; ASn          ; FLASH_OEn     ; 21.281 ;        ;        ; 21.281 ;
; ASn          ; IDE_CS0n      ; 15.332 ;        ;        ; 15.332 ;
; ASn          ; IDE_CS1n      ; 15.024 ;        ;        ; 15.024 ;
; ASn          ; IDE_D_EN_INn  ; 15.673 ;        ;        ; 15.673 ;
; ASn          ; IDE_D_EN_OUTn ; 15.027 ;        ;        ; 15.027 ;
; ASn          ; IDE_IORDn     ; 15.148 ;        ;        ; 15.148 ;
; ASn          ; IDE_IOWRn     ; 15.024 ;        ;        ; 15.024 ;
; ASn          ; JOY_RHn       ; 15.313 ;        ;        ; 15.313 ;
; ASn          ; JOY_RLn       ; 17.333 ;        ;        ; 17.333 ;
; ASn          ; JOY_WEn       ;        ; 17.303 ; 17.303 ;        ;
; ASn          ; JOY_WL        ;        ; 14.557 ; 14.557 ;        ;
; ASn          ; LDSn          ; 30.727 ; 30.727 ; 30.727 ; 30.727 ;
; ASn          ; RAM_DATA[0]   ; 35.836 ; 35.836 ; 35.836 ; 35.836 ;
; ASn          ; RAM_DATA[1]   ; 35.905 ; 35.905 ; 35.905 ; 35.905 ;
; ASn          ; RAM_DATA[2]   ; 36.085 ; 36.398 ; 36.398 ; 36.085 ;
; ASn          ; RAM_DATA[3]   ; 36.566 ; 36.566 ; 36.566 ; 36.566 ;
; ASn          ; RAM_DATA[4]   ; 37.734 ; 37.734 ; 37.734 ; 37.734 ;
; ASn          ; RAM_DATA[5]   ; 35.712 ; 35.712 ; 35.712 ; 35.712 ;
; ASn          ; RAM_DATA[6]   ; 36.180 ; 36.180 ; 36.180 ; 36.180 ;
; ASn          ; RAM_DATA[7]   ; 37.525 ; 37.525 ; 37.525 ; 37.525 ;
; ASn          ; RAM_DATA[8]   ; 36.250 ; 36.250 ; 36.250 ; 36.250 ;
; ASn          ; RAM_DATA[9]   ; 36.225 ; 36.804 ; 36.804 ; 36.225 ;
; ASn          ; RAM_DATA[10]  ; 37.848 ; 37.848 ; 37.848 ; 37.848 ;
; ASn          ; RAM_DATA[11]  ; 36.633 ; 35.914 ; 35.914 ; 36.633 ;
; ASn          ; RAM_DATA[12]  ; 37.492 ; 37.932 ; 37.932 ; 37.492 ;
; ASn          ; RAM_DATA[13]  ; 35.507 ; 36.186 ; 36.186 ; 35.507 ;
; ASn          ; RAM_DATA[14]  ; 33.802 ; 33.802 ; 33.802 ; 33.802 ;
; ASn          ; RAM_DATA[15]  ; 34.103 ; 34.103 ; 34.103 ; 34.103 ;
; ASn          ; ROM0n         ; 17.866 ;        ;        ; 17.866 ;
; ASn          ; ROM1n         ; 19.503 ;        ;        ; 19.503 ;
; ASn          ; ROM2n         ; 18.100 ;        ;        ; 18.100 ;
; ASn          ; ROM3n         ; 17.070 ;        ;        ; 17.070 ;
; ASn          ; ROM4n         ; 16.435 ;        ;        ; 16.435 ;
; ASn          ; ROM5n         ; 19.189 ;        ;        ; 19.189 ;
; ASn          ; ROM6n         ; 17.402 ;        ;        ; 17.402 ;
; ASn          ; RWn           ; 31.019 ; 31.019 ; 31.019 ; 31.019 ;
; ASn          ; UDSn          ; 30.727 ; 30.727 ; 30.727 ; 30.727 ;
; CD[0]        ; DATA[0]       ; 23.621 ;        ;        ; 23.621 ;
; CD[0]        ; RAM_DATA[0]   ; 19.010 ;        ;        ; 19.010 ;
; CD[1]        ; DATA[1]       ; 22.583 ;        ;        ; 22.583 ;
; CD[1]        ; RAM_DATA[1]   ; 20.640 ;        ;        ; 20.640 ;
; CD[2]        ; DATA[2]       ; 22.712 ;        ;        ; 22.712 ;
; CD[2]        ; RAM_DATA[2]   ; 20.424 ;        ;        ; 20.424 ;
; CD[3]        ; DATA[3]       ; 23.925 ;        ;        ; 23.925 ;
; CD[3]        ; RAM_DATA[3]   ; 21.449 ;        ;        ; 21.449 ;
; CD[4]        ; DATA[4]       ; 20.506 ; 20.506 ; 20.506 ; 20.506 ;
; CD[4]        ; RAM_DATA[4]   ; 21.062 ; 21.062 ; 21.062 ; 21.062 ;
; CD[5]        ; DATA[5]       ; 22.302 ; 22.302 ; 22.302 ; 22.302 ;
; CD[5]        ; RAM_DATA[5]   ; 18.940 ; 18.940 ; 18.940 ; 18.940 ;
; CD[6]        ; DATA[6]       ; 22.900 ; 22.900 ; 22.900 ; 22.900 ;
; CD[6]        ; RAM_DATA[6]   ; 22.424 ; 22.424 ; 22.424 ; 22.424 ;
; CD[7]        ; DATA[7]       ; 24.199 ; 24.199 ; 24.199 ; 24.199 ;
; CD[7]        ; RAM_DATA[7]   ; 23.134 ; 23.134 ; 23.134 ; 23.134 ;
; COM_DCD      ; DATA[1]       ;        ; 25.421 ; 25.421 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 24.954 ; 24.954 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 23.478 ; 23.478 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 23.088 ; 23.088 ;        ;
; COM_RI       ; DATA[6]       ; 25.283 ; 25.283 ; 25.283 ; 25.283 ;
; COM_RI       ; DATA[14]      ; 27.823 ; 27.823 ; 27.823 ; 27.823 ;
; COM_RI       ; RAM_DATA[6]   ; 24.807 ; 24.807 ; 24.807 ; 24.807 ;
; COM_RI       ; RAM_DATA[14]  ; 25.247 ; 25.247 ; 25.247 ; 25.247 ;
; CONFIG[1]    ; DATA[15]      ; 25.288 ; 25.288 ; 25.288 ; 25.288 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 22.264 ; 22.264 ; 22.264 ; 22.264 ;
; CONFIG[2]    ; DATA[14]      ; 24.440 ; 24.440 ; 24.440 ; 24.440 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 21.864 ; 21.864 ; 21.864 ; 21.864 ;
; CONFIG[5]    ; ACSI_RDn      ; 24.981 ; 24.981 ; 24.981 ; 24.981 ;
; CONFIG[5]    ; ACSI_WRn      ; 24.971 ; 24.971 ; 24.971 ; 24.971 ;
; CONFIG[5]    ; ASn           ; 31.407 ; 31.407 ; 31.407 ; 31.407 ;
; CONFIG[5]    ; BUTTONn       ; 23.540 ; 20.931 ; 20.931 ; 23.540 ;
; CONFIG[5]    ; CA1_OUT       ; 22.845 ; 20.236 ; 20.236 ; 22.845 ;
; CONFIG[5]    ; CD[0]         ; 30.812 ; 30.812 ; 30.812 ; 30.812 ;
; CONFIG[5]    ; CD[1]         ; 30.297 ; 30.297 ; 30.297 ; 30.297 ;
; CONFIG[5]    ; CD[2]         ; 29.738 ; 29.738 ; 29.738 ; 29.738 ;
; CONFIG[5]    ; CD[3]         ; 31.277 ; 31.277 ; 31.277 ; 31.277 ;
; CONFIG[5]    ; CD[4]         ; 30.219 ; 30.219 ; 30.219 ; 30.219 ;
; CONFIG[5]    ; CD[5]         ; 29.383 ; 29.383 ; 29.383 ; 29.383 ;
; CONFIG[5]    ; CD[6]         ; 32.057 ; 32.057 ; 32.057 ; 32.057 ;
; CONFIG[5]    ; CD[7]         ; 29.736 ; 29.736 ; 29.736 ; 29.736 ;
; CONFIG[5]    ; DATA[0]       ; 42.552 ; 42.552 ; 42.552 ; 42.552 ;
; CONFIG[5]    ; DATA[1]       ; 41.600 ; 41.600 ; 41.600 ; 41.600 ;
; CONFIG[5]    ; DATA[2]       ; 40.515 ; 40.370 ; 40.370 ; 40.515 ;
; CONFIG[5]    ; DATA[3]       ; 40.367 ; 40.725 ; 40.725 ; 40.367 ;
; CONFIG[5]    ; DATA[4]       ; 39.227 ; 39.227 ; 39.227 ; 39.227 ;
; CONFIG[5]    ; DATA[5]       ; 43.002 ; 43.002 ; 43.002 ; 43.002 ;
; CONFIG[5]    ; DATA[6]       ; 40.080 ; 40.080 ; 40.080 ; 40.080 ;
; CONFIG[5]    ; DATA[7]       ; 40.362 ; 40.362 ; 40.362 ; 40.362 ;
; CONFIG[5]    ; DATA[8]       ; 39.968 ; 39.968 ; 39.968 ; 39.968 ;
; CONFIG[5]    ; DATA[9]       ; 41.712 ; 41.056 ; 41.056 ; 41.712 ;
; CONFIG[5]    ; DATA[10]      ; 42.047 ; 42.047 ; 42.047 ; 42.047 ;
; CONFIG[5]    ; DATA[11]      ; 44.773 ; 43.566 ; 43.566 ; 44.773 ;
; CONFIG[5]    ; DATA[12]      ; 40.332 ; 40.022 ; 40.022 ; 40.332 ;
; CONFIG[5]    ; DATA[13]      ; 42.887 ; 41.739 ; 41.739 ; 42.887 ;
; CONFIG[5]    ; DATA[14]      ; 40.407 ; 40.407 ; 40.407 ; 40.407 ;
; CONFIG[5]    ; DATA[15]      ; 40.567 ; 40.567 ; 40.567 ; 40.567 ;
; CONFIG[5]    ; DTACKn        ; 35.037 ; 35.037 ; 35.037 ; 35.037 ;
; CONFIG[5]    ; FC[0]         ; 32.286 ; 32.286 ; 32.286 ; 32.286 ;
; CONFIG[5]    ; FC[1]         ; 31.746 ; 31.746 ; 31.746 ; 31.746 ;
; CONFIG[5]    ; FC[2]         ; 31.746 ; 31.746 ; 31.746 ; 31.746 ;
; CONFIG[5]    ; FLASH_CEn     ; 25.633 ; 25.453 ; 25.453 ; 25.633 ;
; CONFIG[5]    ; FLASH_OEn     ; 26.852 ; 26.672 ; 26.672 ; 26.852 ;
; CONFIG[5]    ; IDE_CS0n      ; 24.369 ; 21.556 ; 21.556 ; 24.369 ;
; CONFIG[5]    ; IDE_CS1n      ; 23.442 ; 20.629 ; 20.629 ; 23.442 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 23.736 ; 20.923 ; 20.923 ; 23.736 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 23.567 ; 20.754 ; 20.754 ; 23.567 ;
; CONFIG[5]    ; IDE_IORDn     ; 22.616 ; 19.803 ; 19.803 ; 22.616 ;
; CONFIG[5]    ; IDE_IOWRn     ; 25.753 ; 22.940 ; 22.940 ; 25.753 ;
; CONFIG[5]    ; JOY_RHn       ; 23.347 ; 20.738 ; 20.738 ; 23.347 ;
; CONFIG[5]    ; JOY_RLn       ; 25.367 ; 22.758 ; 22.758 ; 25.367 ;
; CONFIG[5]    ; JOY_WEn       ; 22.728 ; 25.337 ; 25.337 ; 22.728 ;
; CONFIG[5]    ; JOY_WL        ; 19.982 ; 22.591 ; 22.591 ; 19.982 ;
; CONFIG[5]    ; LDSn          ; 32.710 ; 32.710 ; 32.710 ; 32.710 ;
; CONFIG[5]    ; RAM_BA[1]     ; 17.697 ; 21.675 ; 21.675 ; 17.697 ;
; CONFIG[5]    ; RAM_CAS0n     ; 17.337 ; 19.574 ; 19.574 ; 17.337 ;
; CONFIG[5]    ; RAM_CAS1n     ; 18.758 ; 16.521 ; 16.521 ; 18.758 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 37.941 ; 37.941 ; 37.941 ; 37.941 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 39.657 ; 39.657 ; 39.657 ; 39.657 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 38.227 ; 38.082 ; 38.082 ; 38.227 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 37.891 ; 38.249 ; 38.249 ; 37.891 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 39.783 ; 39.783 ; 39.783 ; 39.783 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 39.640 ; 39.640 ; 39.640 ; 39.640 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 39.604 ; 39.604 ; 39.604 ; 39.604 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 39.297 ; 39.297 ; 39.297 ; 39.297 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 38.607 ; 38.607 ; 38.607 ; 38.607 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 39.846 ; 39.190 ; 39.190 ; 39.846 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 41.776 ; 41.776 ; 41.776 ; 41.776 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 40.561 ; 39.354 ; 39.354 ; 40.561 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 40.151 ; 39.841 ; 39.841 ; 40.151 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 39.577 ; 38.429 ; 38.429 ; 39.577 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 37.831 ; 37.831 ; 37.831 ; 37.831 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 37.543 ; 37.543 ; 37.543 ; 37.543 ;
; CONFIG[5]    ; RAM_RAS0n     ; 19.373 ; 22.225 ; 22.225 ; 19.373 ;
; CONFIG[5]    ; RAM_RAS1n     ; 21.948 ; 19.096 ; 19.096 ; 21.948 ;
; CONFIG[5]    ; ROM0n         ; 23.245 ; 20.409 ; 20.409 ; 23.245 ;
; CONFIG[5]    ; ROM1n         ; 24.882 ; 22.046 ; 22.046 ; 24.882 ;
; CONFIG[5]    ; ROM2n         ; 23.671 ; 23.491 ; 23.491 ; 23.671 ;
; CONFIG[5]    ; ROM3n         ; 26.725 ; 23.912 ; 23.912 ; 26.725 ;
; CONFIG[5]    ; ROM4n         ; 26.093 ; 23.280 ; 23.280 ; 26.093 ;
; CONFIG[5]    ; ROM5n         ; 24.568 ; 21.732 ; 21.732 ; 24.568 ;
; CONFIG[5]    ; ROM6n         ; 27.057 ; 24.244 ; 24.244 ; 27.057 ;
; CONFIG[5]    ; RWn           ; 33.002 ; 33.002 ; 33.002 ; 33.002 ;
; CONFIG[5]    ; UDSn          ; 32.710 ; 32.710 ; 32.710 ; 32.710 ;
; DATA[0]      ; DATA[0]       ; 22.287 ;        ;        ; 22.287 ;
; DATA[0]      ; RAM_DATA[0]   ; 17.676 ;        ;        ; 17.676 ;
; DATA[1]      ; DATA[1]       ; 21.789 ;        ;        ; 21.789 ;
; DATA[1]      ; RAM_DATA[1]   ; 19.846 ;        ;        ; 19.846 ;
; DATA[2]      ; DATA[2]       ; 21.507 ;        ;        ; 21.507 ;
; DATA[2]      ; RAM_DATA[2]   ; 19.219 ;        ;        ; 19.219 ;
; DATA[3]      ; DATA[3]       ; 21.541 ;        ;        ; 21.541 ;
; DATA[3]      ; RAM_DATA[3]   ; 19.065 ;        ;        ; 19.065 ;
; DATA[4]      ; DATA[4]       ; 16.750 ; 16.750 ; 16.750 ; 16.750 ;
; DATA[4]      ; RAM_DATA[4]   ; 17.306 ; 17.306 ; 17.306 ; 17.306 ;
; DATA[5]      ; DATA[5]       ; 19.688 ;        ;        ; 19.688 ;
; DATA[5]      ; RAM_DATA[5]   ; 16.326 ;        ;        ; 16.326 ;
; DATA[6]      ; DATA[6]       ; 18.035 ; 18.035 ; 18.035 ; 18.035 ;
; DATA[6]      ; RAM_DATA[6]   ; 17.559 ; 17.559 ; 17.559 ; 17.559 ;
; DATA[7]      ; DATA[7]       ; 18.442 ;        ;        ; 18.442 ;
; DATA[7]      ; RAM_DATA[7]   ; 17.377 ;        ;        ; 17.377 ;
; DATA[8]      ; DATA[8]       ; 20.155 ;        ;        ; 20.155 ;
; DATA[8]      ; RAM_DATA[8]   ; 18.794 ;        ;        ; 18.794 ;
; DATA[9]      ; DATA[9]       ; 21.796 ;        ;        ; 21.796 ;
; DATA[9]      ; RAM_DATA[9]   ; 19.930 ;        ;        ; 19.930 ;
; DATA[10]     ; DATA[10]      ; 20.806 ;        ;        ; 20.806 ;
; DATA[10]     ; RAM_DATA[10]  ; 20.535 ;        ;        ; 20.535 ;
; DATA[11]     ; DATA[11]      ; 22.508 ;        ;        ; 22.508 ;
; DATA[11]     ; RAM_DATA[11]  ; 18.296 ;        ;        ; 18.296 ;
; DATA[12]     ; DATA[12]      ; 23.067 ;        ;        ; 23.067 ;
; DATA[12]     ; RAM_DATA[12]  ; 22.886 ;        ;        ; 22.886 ;
; DATA[13]     ; DATA[13]      ; 23.615 ;        ;        ; 23.615 ;
; DATA[13]     ; RAM_DATA[13]  ; 20.305 ;        ;        ; 20.305 ;
; DATA[14]     ; DATA[14]      ; 16.839 ;        ;        ; 16.839 ;
; DATA[14]     ; RAM_DATA[14]  ; 14.263 ;        ;        ; 14.263 ;
; DATA[15]     ; DATA[15]      ; 17.411 ;        ;        ; 17.411 ;
; DATA[15]     ; RAM_DATA[15]  ; 14.387 ;        ;        ; 14.387 ;
; FC[0]        ; ACSI_RDn      ; 21.864 ; 21.864 ; 21.864 ; 21.864 ;
; FC[0]        ; ACSI_WRn      ; 21.854 ; 21.854 ; 21.854 ; 21.854 ;
; FC[0]        ; ASn           ; 29.074 ; 29.074 ; 29.074 ; 29.074 ;
; FC[0]        ; BUTTONn       ; 19.259 ; 18.501 ; 18.501 ; 19.259 ;
; FC[0]        ; CA1_OUT       ; 19.728 ; 16.703 ; 16.703 ; 19.728 ;
; FC[0]        ; CD[0]         ; 27.695 ; 27.695 ; 27.695 ; 27.695 ;
; FC[0]        ; CD[1]         ; 27.180 ; 27.180 ; 27.180 ; 27.180 ;
; FC[0]        ; CD[2]         ; 26.621 ; 26.621 ; 26.621 ; 26.621 ;
; FC[0]        ; CD[3]         ; 28.160 ; 28.160 ; 28.160 ; 28.160 ;
; FC[0]        ; CD[4]         ; 27.102 ; 27.102 ; 27.102 ; 27.102 ;
; FC[0]        ; CD[5]         ; 26.266 ; 26.266 ; 26.266 ; 26.266 ;
; FC[0]        ; CD[6]         ; 28.940 ; 28.940 ; 28.940 ; 28.940 ;
; FC[0]        ; CD[7]         ; 26.619 ; 26.619 ; 26.619 ; 26.619 ;
; FC[0]        ; DATA[0]       ; 40.097 ; 40.097 ; 40.097 ; 40.097 ;
; FC[0]        ; DATA[1]       ; 39.808 ; 39.808 ; 39.808 ; 39.808 ;
; FC[0]        ; DATA[2]       ; 38.830 ; 38.830 ; 38.830 ; 38.830 ;
; FC[0]        ; DATA[3]       ; 38.891 ; 38.891 ; 38.891 ; 38.891 ;
; FC[0]        ; DATA[4]       ; 37.846 ; 37.846 ; 37.846 ; 37.846 ;
; FC[0]        ; DATA[5]       ; 41.168 ; 41.168 ; 41.168 ; 41.168 ;
; FC[0]        ; DATA[6]       ; 38.699 ; 38.699 ; 38.699 ; 38.699 ;
; FC[0]        ; DATA[7]       ; 38.981 ; 38.981 ; 38.981 ; 38.981 ;
; FC[0]        ; DATA[8]       ; 38.587 ; 38.587 ; 38.587 ; 38.587 ;
; FC[0]        ; DATA[9]       ; 39.878 ; 39.878 ; 39.878 ; 39.878 ;
; FC[0]        ; DATA[10]      ; 40.213 ; 40.213 ; 40.213 ; 40.213 ;
; FC[0]        ; DATA[11]      ; 42.939 ; 42.939 ; 42.939 ; 42.939 ;
; FC[0]        ; DATA[12]      ; 38.498 ; 38.498 ; 38.498 ; 38.498 ;
; FC[0]        ; DATA[13]      ; 39.879 ; 39.879 ; 39.879 ; 39.879 ;
; FC[0]        ; DATA[14]      ; 38.437 ; 38.437 ; 38.437 ; 38.437 ;
; FC[0]        ; DATA[15]      ; 39.186 ; 39.186 ; 39.186 ; 39.186 ;
; FC[0]        ; DTACKn        ; 29.842 ; 29.842 ; 29.842 ; 29.842 ;
; FC[0]        ; FC[0]         ; 29.953 ; 29.953 ; 29.953 ; 29.953 ;
; FC[0]        ; FC[1]         ; 29.413 ; 29.413 ; 29.413 ; 29.413 ;
; FC[0]        ; FC[2]         ; 29.413 ; 29.413 ; 29.413 ; 29.413 ;
; FC[0]        ; FLASH_CEn     ; 22.121 ; 21.850 ; 21.850 ; 22.121 ;
; FC[0]        ; FLASH_OEn     ; 23.340 ; 23.069 ; 23.069 ; 23.340 ;
; FC[0]        ; IDE_CS0n      ; 17.391 ;        ;        ; 17.391 ;
; FC[0]        ; IDE_CS1n      ; 17.083 ;        ;        ; 17.083 ;
; FC[0]        ; IDE_D_EN_INn  ; 17.732 ;        ;        ; 17.732 ;
; FC[0]        ; IDE_D_EN_OUTn ; 17.086 ;        ;        ; 17.086 ;
; FC[0]        ; IDE_IORDn     ; 17.207 ;        ;        ; 17.207 ;
; FC[0]        ; IDE_IOWRn     ; 17.083 ;        ;        ; 17.083 ;
; FC[0]        ; JOY_RHn       ; 18.472 ; 18.472 ; 18.472 ; 18.472 ;
; FC[0]        ; JOY_RLn       ; 20.501 ; 20.501 ; 20.501 ; 20.501 ;
; FC[0]        ; JOY_WEn       ; 20.471 ; 20.471 ; 20.471 ; 20.471 ;
; FC[0]        ; JOY_WL        ; 17.515 ; 17.515 ; 17.515 ; 17.515 ;
; FC[0]        ; LDSn          ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; FC[0]        ; RAM_DATA[0]   ; 35.486 ; 35.486 ; 35.486 ; 35.486 ;
; FC[0]        ; RAM_DATA[1]   ; 37.865 ; 37.865 ; 37.865 ; 37.865 ;
; FC[0]        ; RAM_DATA[2]   ; 36.542 ; 36.542 ; 36.542 ; 36.542 ;
; FC[0]        ; RAM_DATA[3]   ; 36.415 ; 36.415 ; 36.415 ; 36.415 ;
; FC[0]        ; RAM_DATA[4]   ; 38.402 ; 38.402 ; 38.402 ; 38.402 ;
; FC[0]        ; RAM_DATA[5]   ; 37.806 ; 37.806 ; 37.806 ; 37.806 ;
; FC[0]        ; RAM_DATA[6]   ; 38.223 ; 38.223 ; 38.223 ; 38.223 ;
; FC[0]        ; RAM_DATA[7]   ; 37.916 ; 37.916 ; 37.916 ; 37.916 ;
; FC[0]        ; RAM_DATA[8]   ; 37.226 ; 37.226 ; 37.226 ; 37.226 ;
; FC[0]        ; RAM_DATA[9]   ; 38.012 ; 38.012 ; 38.012 ; 38.012 ;
; FC[0]        ; RAM_DATA[10]  ; 39.942 ; 39.942 ; 39.942 ; 39.942 ;
; FC[0]        ; RAM_DATA[11]  ; 38.727 ; 38.727 ; 38.727 ; 38.727 ;
; FC[0]        ; RAM_DATA[12]  ; 38.317 ; 38.317 ; 38.317 ; 38.317 ;
; FC[0]        ; RAM_DATA[13]  ; 36.569 ; 36.569 ; 36.569 ; 36.569 ;
; FC[0]        ; RAM_DATA[14]  ; 35.861 ; 35.861 ; 35.861 ; 35.861 ;
; FC[0]        ; RAM_DATA[15]  ; 36.162 ; 36.162 ; 36.162 ; 36.162 ;
; FC[0]        ; ROM0n         ; 19.925 ; 19.363 ; 19.363 ; 19.925 ;
; FC[0]        ; ROM1n         ; 21.562 ; 21.000 ; 21.000 ; 21.562 ;
; FC[0]        ; ROM2n         ; 20.159 ; 19.888 ; 19.888 ; 20.159 ;
; FC[0]        ; ROM3n         ; 19.129 ; 18.858 ; 18.858 ; 19.129 ;
; FC[0]        ; ROM4n         ; 18.494 ; 18.223 ; 18.223 ; 18.494 ;
; FC[0]        ; ROM5n         ; 21.248 ; 20.686 ; 20.686 ; 21.248 ;
; FC[0]        ; ROM6n         ; 19.461 ; 19.190 ; 19.190 ; 19.461 ;
; FC[0]        ; RWn           ; 30.669 ; 30.669 ; 30.669 ; 30.669 ;
; FC[0]        ; UDSn          ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; FC[1]        ; ACSI_RDn      ; 22.167 ; 22.167 ; 22.167 ; 22.167 ;
; FC[1]        ; ACSI_WRn      ; 22.157 ; 22.157 ; 22.157 ; 22.157 ;
; FC[1]        ; ASn           ; 29.377 ; 29.377 ; 29.377 ; 29.377 ;
; FC[1]        ; BUTTONn       ; 18.769 ; 16.502 ; 16.502 ; 18.769 ;
; FC[1]        ; CA1_OUT       ; 20.031 ; 17.012 ; 17.012 ; 20.031 ;
; FC[1]        ; CD[0]         ; 27.998 ; 27.998 ; 27.998 ; 27.998 ;
; FC[1]        ; CD[1]         ; 27.483 ; 27.483 ; 27.483 ; 27.483 ;
; FC[1]        ; CD[2]         ; 26.924 ; 26.924 ; 26.924 ; 26.924 ;
; FC[1]        ; CD[3]         ; 28.463 ; 28.463 ; 28.463 ; 28.463 ;
; FC[1]        ; CD[4]         ; 27.405 ; 27.405 ; 27.405 ; 27.405 ;
; FC[1]        ; CD[5]         ; 26.569 ; 26.569 ; 26.569 ; 26.569 ;
; FC[1]        ; CD[6]         ; 29.243 ; 29.243 ; 29.243 ; 29.243 ;
; FC[1]        ; CD[7]         ; 26.922 ; 26.922 ; 26.922 ; 26.922 ;
; FC[1]        ; DATA[0]       ; 40.400 ; 40.400 ; 40.400 ; 40.400 ;
; FC[1]        ; DATA[1]       ; 39.318 ; 39.318 ; 39.318 ; 39.318 ;
; FC[1]        ; DATA[2]       ; 38.340 ; 38.639 ; 38.639 ; 38.340 ;
; FC[1]        ; DATA[3]       ; 38.995 ; 38.995 ; 38.995 ; 38.995 ;
; FC[1]        ; DATA[4]       ; 37.356 ; 37.356 ; 37.356 ; 37.356 ;
; FC[1]        ; DATA[5]       ; 40.680 ; 40.680 ; 40.680 ; 40.680 ;
; FC[1]        ; DATA[6]       ; 38.209 ; 38.209 ; 38.209 ; 38.209 ;
; FC[1]        ; DATA[7]       ; 38.543 ; 38.543 ; 38.543 ; 38.543 ;
; FC[1]        ; DATA[8]       ; 38.097 ; 38.097 ; 38.097 ; 38.097 ;
; FC[1]        ; DATA[9]       ; 39.390 ; 39.390 ; 39.390 ; 39.390 ;
; FC[1]        ; DATA[10]      ; 39.725 ; 39.725 ; 39.725 ; 39.725 ;
; FC[1]        ; DATA[11]      ; 42.451 ; 42.451 ; 42.451 ; 42.451 ;
; FC[1]        ; DATA[12]      ; 38.010 ; 38.066 ; 38.066 ; 38.010 ;
; FC[1]        ; DATA[13]      ; 39.391 ; 39.449 ; 39.449 ; 39.391 ;
; FC[1]        ; DATA[14]      ; 37.947 ; 37.947 ; 37.947 ; 37.947 ;
; FC[1]        ; DATA[15]      ; 38.696 ; 38.696 ; 38.696 ; 38.696 ;
; FC[1]        ; DTACKn        ; 30.145 ; 30.145 ; 30.145 ; 30.145 ;
; FC[1]        ; FC[0]         ; 30.256 ; 30.256 ; 30.256 ; 30.256 ;
; FC[1]        ; FC[1]         ; 29.716 ; 29.716 ; 29.716 ; 29.716 ;
; FC[1]        ; FC[2]         ; 29.716 ; 29.716 ; 29.716 ; 29.716 ;
; FC[1]        ; FLASH_CEn     ; 21.631 ; 19.851 ; 19.851 ; 21.631 ;
; FC[1]        ; FLASH_OEn     ; 22.850 ; 21.070 ; 21.070 ; 22.850 ;
; FC[1]        ; IDE_CS0n      ; 16.901 ;        ;        ; 16.901 ;
; FC[1]        ; IDE_CS1n      ; 16.593 ;        ;        ; 16.593 ;
; FC[1]        ; IDE_D_EN_INn  ; 17.242 ;        ;        ; 17.242 ;
; FC[1]        ; IDE_D_EN_OUTn ; 16.596 ;        ;        ; 16.596 ;
; FC[1]        ; IDE_IORDn     ; 16.717 ;        ;        ; 16.717 ;
; FC[1]        ; IDE_IOWRn     ; 16.593 ;        ;        ; 16.593 ;
; FC[1]        ; JOY_RHn       ; 17.984 ; 17.984 ; 17.984 ; 17.984 ;
; FC[1]        ; JOY_RLn       ; 20.013 ; 20.013 ; 20.013 ; 20.013 ;
; FC[1]        ; JOY_WEn       ; 19.983 ; 19.983 ; 19.983 ; 19.983 ;
; FC[1]        ; JOY_WL        ; 17.027 ; 17.027 ; 17.027 ; 17.027 ;
; FC[1]        ; LDSn          ; 30.680 ; 30.680 ; 30.680 ; 30.680 ;
; FC[1]        ; RAM_DATA[0]   ; 35.789 ; 35.789 ; 35.789 ; 35.789 ;
; FC[1]        ; RAM_DATA[1]   ; 37.375 ; 37.375 ; 37.375 ; 37.375 ;
; FC[1]        ; RAM_DATA[2]   ; 36.052 ; 36.351 ; 36.351 ; 36.052 ;
; FC[1]        ; RAM_DATA[3]   ; 36.519 ; 36.519 ; 36.519 ; 36.519 ;
; FC[1]        ; RAM_DATA[4]   ; 37.912 ; 37.912 ; 37.912 ; 37.912 ;
; FC[1]        ; RAM_DATA[5]   ; 37.318 ; 37.318 ; 37.318 ; 37.318 ;
; FC[1]        ; RAM_DATA[6]   ; 37.733 ; 37.733 ; 37.733 ; 37.733 ;
; FC[1]        ; RAM_DATA[7]   ; 37.478 ; 37.478 ; 37.478 ; 37.478 ;
; FC[1]        ; RAM_DATA[8]   ; 36.736 ; 36.736 ; 36.736 ; 36.736 ;
; FC[1]        ; RAM_DATA[9]   ; 37.524 ; 37.524 ; 37.524 ; 37.524 ;
; FC[1]        ; RAM_DATA[10]  ; 39.454 ; 39.454 ; 39.454 ; 39.454 ;
; FC[1]        ; RAM_DATA[11]  ; 38.239 ; 38.239 ; 38.239 ; 38.239 ;
; FC[1]        ; RAM_DATA[12]  ; 37.829 ; 37.885 ; 37.885 ; 37.829 ;
; FC[1]        ; RAM_DATA[13]  ; 36.081 ; 36.139 ; 36.139 ; 36.081 ;
; FC[1]        ; RAM_DATA[14]  ; 35.371 ; 35.371 ; 35.371 ; 35.371 ;
; FC[1]        ; RAM_DATA[15]  ; 35.672 ; 35.672 ; 35.672 ; 35.672 ;
; FC[1]        ; ROM0n         ; 19.435 ; 17.364 ; 17.364 ; 19.435 ;
; FC[1]        ; ROM1n         ; 21.072 ; 19.001 ; 19.001 ; 21.072 ;
; FC[1]        ; ROM2n         ; 19.669 ; 17.889 ; 17.889 ; 19.669 ;
; FC[1]        ; ROM3n         ; 18.639 ; 16.859 ; 16.859 ; 18.639 ;
; FC[1]        ; ROM4n         ; 18.004 ; 16.224 ; 16.224 ; 18.004 ;
; FC[1]        ; ROM5n         ; 20.758 ; 18.687 ; 18.687 ; 20.758 ;
; FC[1]        ; ROM6n         ; 18.971 ; 17.191 ; 17.191 ; 18.971 ;
; FC[1]        ; RWn           ; 30.972 ; 30.972 ; 30.972 ; 30.972 ;
; FC[1]        ; UDSn          ; 30.680 ; 30.680 ; 30.680 ; 30.680 ;
; FC[2]        ; ACSI_RDn      ; 22.071 ; 22.071 ; 22.071 ; 22.071 ;
; FC[2]        ; ACSI_WRn      ; 22.061 ; 22.061 ; 22.061 ; 22.061 ;
; FC[2]        ; ASn           ; 29.281 ; 29.281 ; 29.281 ; 29.281 ;
; FC[2]        ; BUTTONn       ; 18.708 ;        ;        ; 18.708 ;
; FC[2]        ; CA1_OUT       ; 19.935 ; 16.916 ; 16.916 ; 19.935 ;
; FC[2]        ; CD[0]         ; 27.902 ; 27.902 ; 27.902 ; 27.902 ;
; FC[2]        ; CD[1]         ; 27.387 ; 27.387 ; 27.387 ; 27.387 ;
; FC[2]        ; CD[2]         ; 26.828 ; 26.828 ; 26.828 ; 26.828 ;
; FC[2]        ; CD[3]         ; 28.367 ; 28.367 ; 28.367 ; 28.367 ;
; FC[2]        ; CD[4]         ; 27.309 ; 27.309 ; 27.309 ; 27.309 ;
; FC[2]        ; CD[5]         ; 26.473 ; 26.473 ; 26.473 ; 26.473 ;
; FC[2]        ; CD[6]         ; 29.147 ; 29.147 ; 29.147 ; 29.147 ;
; FC[2]        ; CD[7]         ; 26.826 ; 26.826 ; 26.826 ; 26.826 ;
; FC[2]        ; DATA[0]       ; 40.304 ; 40.304 ; 40.304 ; 40.304 ;
; FC[2]        ; DATA[1]       ; 39.257 ; 39.257 ; 39.257 ; 39.257 ;
; FC[2]        ; DATA[2]       ; 38.279 ; 38.543 ; 38.543 ; 38.279 ;
; FC[2]        ; DATA[3]       ; 38.899 ; 38.899 ; 38.899 ; 38.899 ;
; FC[2]        ; DATA[4]       ; 37.295 ; 37.295 ; 37.295 ; 37.295 ;
; FC[2]        ; DATA[5]       ; 40.622 ; 40.622 ; 40.622 ; 40.622 ;
; FC[2]        ; DATA[6]       ; 38.148 ; 38.148 ; 38.148 ; 38.148 ;
; FC[2]        ; DATA[7]       ; 38.447 ; 38.447 ; 38.447 ; 38.447 ;
; FC[2]        ; DATA[8]       ; 38.036 ; 38.036 ; 38.036 ; 38.036 ;
; FC[2]        ; DATA[9]       ; 39.292 ; 39.332 ; 39.332 ; 39.292 ;
; FC[2]        ; DATA[10]      ; 39.667 ; 39.667 ; 39.667 ; 39.667 ;
; FC[2]        ; DATA[11]      ; 42.353 ; 42.393 ; 42.393 ; 42.353 ;
; FC[2]        ; DATA[12]      ; 37.912 ; 37.970 ; 37.970 ; 37.912 ;
; FC[2]        ; DATA[13]      ; 39.293 ; 39.353 ; 39.353 ; 39.293 ;
; FC[2]        ; DATA[14]      ; 37.886 ; 37.886 ; 37.886 ; 37.886 ;
; FC[2]        ; DATA[15]      ; 38.635 ; 38.635 ; 38.635 ; 38.635 ;
; FC[2]        ; DTACKn        ; 30.049 ; 30.049 ; 30.049 ; 30.049 ;
; FC[2]        ; FC[0]         ; 30.160 ; 30.160 ; 30.160 ; 30.160 ;
; FC[2]        ; FC[1]         ; 29.620 ; 29.620 ; 29.620 ; 29.620 ;
; FC[2]        ; FC[2]         ; 29.620 ; 29.620 ; 29.620 ; 29.620 ;
; FC[2]        ; FLASH_CEn     ; 21.570 ;        ;        ; 21.570 ;
; FC[2]        ; FLASH_OEn     ; 22.789 ;        ;        ; 22.789 ;
; FC[2]        ; IDE_CS0n      ; 16.840 ;        ;        ; 16.840 ;
; FC[2]        ; IDE_CS1n      ; 16.532 ;        ;        ; 16.532 ;
; FC[2]        ; IDE_D_EN_INn  ; 17.181 ;        ;        ; 17.181 ;
; FC[2]        ; IDE_D_EN_OUTn ; 16.535 ;        ;        ; 16.535 ;
; FC[2]        ; IDE_IORDn     ; 16.656 ;        ;        ; 16.656 ;
; FC[2]        ; IDE_IOWRn     ; 16.532 ;        ;        ; 16.532 ;
; FC[2]        ; JOY_RHn       ; 16.821 ; 17.926 ; 17.926 ; 16.821 ;
; FC[2]        ; JOY_RLn       ; 18.841 ; 19.955 ; 19.955 ; 18.841 ;
; FC[2]        ; JOY_WEn       ; 19.925 ; 18.811 ; 18.811 ; 19.925 ;
; FC[2]        ; JOY_WL        ; 16.969 ; 16.065 ; 16.065 ; 16.969 ;
; FC[2]        ; LDSn          ; 30.584 ; 30.584 ; 30.584 ; 30.584 ;
; FC[2]        ; RAM_DATA[0]   ; 35.693 ; 35.693 ; 35.693 ; 35.693 ;
; FC[2]        ; RAM_DATA[1]   ; 37.314 ; 37.314 ; 37.314 ; 37.314 ;
; FC[2]        ; RAM_DATA[2]   ; 35.991 ; 36.255 ; 36.255 ; 35.991 ;
; FC[2]        ; RAM_DATA[3]   ; 36.423 ; 36.423 ; 36.423 ; 36.423 ;
; FC[2]        ; RAM_DATA[4]   ; 37.851 ; 37.851 ; 37.851 ; 37.851 ;
; FC[2]        ; RAM_DATA[5]   ; 37.260 ; 37.260 ; 37.260 ; 37.260 ;
; FC[2]        ; RAM_DATA[6]   ; 37.672 ; 37.672 ; 37.672 ; 37.672 ;
; FC[2]        ; RAM_DATA[7]   ; 37.382 ; 37.382 ; 37.382 ; 37.382 ;
; FC[2]        ; RAM_DATA[8]   ; 36.675 ; 36.675 ; 36.675 ; 36.675 ;
; FC[2]        ; RAM_DATA[9]   ; 37.426 ; 37.466 ; 37.466 ; 37.426 ;
; FC[2]        ; RAM_DATA[10]  ; 39.396 ; 39.396 ; 39.396 ; 39.396 ;
; FC[2]        ; RAM_DATA[11]  ; 38.141 ; 38.181 ; 38.181 ; 38.141 ;
; FC[2]        ; RAM_DATA[12]  ; 37.731 ; 37.789 ; 37.789 ; 37.731 ;
; FC[2]        ; RAM_DATA[13]  ; 35.983 ; 36.043 ; 36.043 ; 35.983 ;
; FC[2]        ; RAM_DATA[14]  ; 35.310 ; 35.310 ; 35.310 ; 35.310 ;
; FC[2]        ; RAM_DATA[15]  ; 35.611 ; 35.611 ; 35.611 ; 35.611 ;
; FC[2]        ; ROM0n         ; 19.374 ;        ;        ; 19.374 ;
; FC[2]        ; ROM1n         ; 21.011 ;        ;        ; 21.011 ;
; FC[2]        ; ROM2n         ; 19.608 ;        ;        ; 19.608 ;
; FC[2]        ; ROM3n         ; 18.578 ;        ;        ; 18.578 ;
; FC[2]        ; ROM4n         ; 17.943 ;        ;        ; 17.943 ;
; FC[2]        ; ROM5n         ; 20.697 ;        ;        ; 20.697 ;
; FC[2]        ; ROM6n         ; 18.910 ;        ;        ; 18.910 ;
; FC[2]        ; RWn           ; 30.876 ; 30.876 ; 30.876 ; 30.876 ;
; FC[2]        ; UDSn          ; 30.584 ; 30.584 ; 30.584 ; 30.584 ;
; HDINTn       ; DATA[5]       ; 26.726 ; 26.726 ; 26.726 ; 26.726 ;
; HDINTn       ; DATA[13]      ; 27.379 ;        ;        ; 27.379 ;
; HDINTn       ; RAM_DATA[5]   ; 23.364 ; 23.364 ; 23.364 ; 23.364 ;
; HDINTn       ; RAM_DATA[13]  ; 24.069 ;        ;        ; 24.069 ;
; IDE_INTRQ    ; DATA[5]       ; 26.932 ; 26.932 ; 26.932 ; 26.932 ;
; IDE_INTRQ    ; DATA[13]      ;        ; 27.585 ; 27.585 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ; 23.570 ; 23.570 ; 23.570 ; 23.570 ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 24.275 ; 24.275 ;        ;
; LDSn         ; ACSI_RDn      ; 16.172 ; 16.172 ; 16.172 ; 16.172 ;
; LDSn         ; ACSI_WRn      ; 16.162 ; 16.162 ; 16.162 ; 16.162 ;
; LDSn         ; ASn           ; 28.228 ; 28.228 ; 28.228 ; 28.228 ;
; LDSn         ; BUTTONn       ; 17.903 ;        ;        ; 17.903 ;
; LDSn         ; CA1_OUT       ; 14.036 ;        ;        ; 14.036 ;
; LDSn         ; CD[0]         ; 22.003 ; 22.003 ; 22.003 ; 22.003 ;
; LDSn         ; CD[1]         ; 21.488 ; 21.488 ; 21.488 ; 21.488 ;
; LDSn         ; CD[2]         ; 20.929 ; 20.929 ; 20.929 ; 20.929 ;
; LDSn         ; CD[3]         ; 22.468 ; 22.468 ; 22.468 ; 22.468 ;
; LDSn         ; CD[4]         ; 21.410 ; 21.410 ; 21.410 ; 21.410 ;
; LDSn         ; CD[5]         ; 20.574 ; 20.574 ; 20.574 ; 20.574 ;
; LDSn         ; CD[6]         ; 23.248 ; 23.248 ; 23.248 ; 23.248 ;
; LDSn         ; CD[7]         ; 20.927 ; 20.927 ; 20.927 ; 20.927 ;
; LDSn         ; DATA[0]       ; 39.251 ; 39.251 ; 39.251 ; 39.251 ;
; LDSn         ; DATA[1]       ; 36.652 ; 36.652 ; 36.652 ; 36.652 ;
; LDSn         ; DATA[2]       ; 37.177 ; 37.490 ; 37.490 ; 37.177 ;
; LDSn         ; DATA[3]       ; 37.846 ; 37.846 ; 37.846 ; 37.846 ;
; LDSn         ; DATA[4]       ; 35.982 ; 35.982 ; 35.982 ; 35.982 ;
; LDSn         ; DATA[5]       ; 37.819 ; 37.819 ; 37.819 ; 37.819 ;
; LDSn         ; DATA[6]       ; 35.460 ; 35.460 ; 35.460 ; 35.460 ;
; LDSn         ; DATA[7]       ; 37.394 ; 37.394 ; 37.394 ; 37.394 ;
; LDSn         ; DATA[8]       ; 36.415 ; 36.415 ; 36.415 ; 36.415 ;
; LDSn         ; DATA[9]       ; 36.895 ; 37.474 ; 37.474 ; 36.895 ;
; LDSn         ; DATA[10]      ; 36.626 ; 36.626 ; 36.626 ; 36.626 ;
; LDSn         ; DATA[11]      ; 38.826 ; 39.352 ; 39.352 ; 38.826 ;
; LDSn         ; DATA[12]      ; 36.477 ; 36.917 ; 36.917 ; 36.477 ;
; LDSn         ; DATA[13]      ; 37.621 ; 38.300 ; 38.300 ; 37.621 ;
; LDSn         ; DATA[14]      ; 34.922 ; 34.922 ; 34.922 ; 34.922 ;
; LDSn         ; DATA[15]      ; 35.827 ; 35.827 ; 35.827 ; 35.827 ;
; LDSn         ; DTACKn        ; 27.380 ; 27.380 ; 27.380 ; 27.380 ;
; LDSn         ; FC[0]         ; 29.107 ; 29.107 ; 29.107 ; 29.107 ;
; LDSn         ; FC[1]         ; 28.567 ; 28.567 ; 28.567 ; 28.567 ;
; LDSn         ; FC[2]         ; 28.567 ; 28.567 ; 28.567 ; 28.567 ;
; LDSn         ; IDE_IORDn     ; 15.219 ;        ;        ; 15.219 ;
; LDSn         ; IDE_IOWRn     ; 15.145 ;        ;        ; 15.145 ;
; LDSn         ; JOY_RLn       ; 17.022 ;        ;        ; 17.022 ;
; LDSn         ; JOY_WEn       ;        ; 16.992 ; 16.992 ;        ;
; LDSn         ; JOY_WL        ;        ; 14.045 ; 14.045 ;        ;
; LDSn         ; LDSn          ; 29.531 ; 29.531 ; 29.531 ; 29.531 ;
; LDSn         ; RAM_CAS0n     ; 21.179 ;        ;        ; 21.179 ;
; LDSn         ; RAM_CAS1n     ; 20.361 ;        ;        ; 20.361 ;
; LDSn         ; RAM_DATA[0]   ; 34.640 ; 34.640 ; 34.640 ; 34.640 ;
; LDSn         ; RAM_DATA[1]   ; 34.709 ; 34.709 ; 34.709 ; 34.709 ;
; LDSn         ; RAM_DATA[2]   ; 34.889 ; 35.202 ; 35.202 ; 34.889 ;
; LDSn         ; RAM_DATA[3]   ; 35.370 ; 35.370 ; 35.370 ; 35.370 ;
; LDSn         ; RAM_DATA[4]   ; 36.538 ; 36.538 ; 36.538 ; 36.538 ;
; LDSn         ; RAM_DATA[5]   ; 34.457 ; 34.457 ; 34.457 ; 34.457 ;
; LDSn         ; RAM_DATA[6]   ; 34.984 ; 34.984 ; 34.984 ; 34.984 ;
; LDSn         ; RAM_DATA[7]   ; 36.329 ; 36.329 ; 36.329 ; 36.329 ;
; LDSn         ; RAM_DATA[8]   ; 35.054 ; 35.054 ; 35.054 ; 35.054 ;
; LDSn         ; RAM_DATA[9]   ; 35.029 ; 35.608 ; 35.608 ; 35.029 ;
; LDSn         ; RAM_DATA[10]  ; 36.355 ; 36.355 ; 36.355 ; 36.355 ;
; LDSn         ; RAM_DATA[11]  ; 34.614 ; 35.140 ; 35.140 ; 34.614 ;
; LDSn         ; RAM_DATA[12]  ; 36.296 ; 36.736 ; 36.736 ; 36.296 ;
; LDSn         ; RAM_DATA[13]  ; 34.311 ; 34.990 ; 34.990 ; 34.311 ;
; LDSn         ; RAM_DATA[14]  ; 32.346 ; 32.346 ; 32.346 ; 32.346 ;
; LDSn         ; RAM_DATA[15]  ; 32.803 ; 32.803 ; 32.803 ; 32.803 ;
; LDSn         ; RAM_DQM0H     ; 26.091 ; 25.661 ; 25.661 ; 26.091 ;
; LDSn         ; RAM_DQM0L     ; 24.410 ; 24.031 ; 24.031 ; 24.410 ;
; LDSn         ; RAM_DQM1H     ; 26.284 ; 25.854 ; 25.854 ; 26.284 ;
; LDSn         ; RAM_DQM1L     ; 24.400 ; 24.021 ; 24.021 ; 24.400 ;
; LDSn         ; RWn           ; 29.823 ; 29.823 ; 29.823 ; 29.823 ;
; LDSn         ; UDSn          ; 29.531 ; 29.531 ; 29.531 ; 29.531 ;
; LPT_BSY      ; DATA[0]       ; 23.759 ;        ;        ; 23.759 ;
; LPT_BSY      ; DATA[8]       ; 21.983 ;        ;        ; 21.983 ;
; LPT_BSY      ; RAM_DATA[0]   ; 19.148 ;        ;        ; 19.148 ;
; LPT_BSY      ; RAM_DATA[8]   ; 20.622 ;        ;        ; 20.622 ;
; LPT_D[0]     ; DATA[0]       ; 22.797 ;        ;        ; 22.797 ;
; LPT_D[0]     ; DATA[8]       ; 21.021 ;        ;        ; 21.021 ;
; LPT_D[0]     ; RAM_DATA[0]   ; 18.186 ;        ;        ; 18.186 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 19.660 ;        ;        ; 19.660 ;
; LPT_D[1]     ; DATA[1]       ; 22.129 ;        ;        ; 22.129 ;
; LPT_D[1]     ; DATA[9]       ; 21.856 ;        ;        ; 21.856 ;
; LPT_D[1]     ; RAM_DATA[1]   ; 20.186 ;        ;        ; 20.186 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 19.990 ;        ;        ; 19.990 ;
; LPT_D[2]     ; DATA[2]       ; 21.883 ;        ;        ; 21.883 ;
; LPT_D[2]     ; DATA[10]      ; 21.572 ;        ;        ; 21.572 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 19.595 ;        ;        ; 19.595 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 21.301 ;        ;        ; 21.301 ;
; LPT_D[3]     ; DATA[3]       ; 23.208 ;        ;        ; 23.208 ;
; LPT_D[3]     ; DATA[11]      ; 24.946 ;        ;        ; 24.946 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 20.732 ;        ;        ; 20.732 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 20.734 ;        ;        ; 20.734 ;
; LPT_D[4]     ; DATA[4]       ; 25.353 ; 25.353 ; 25.353 ; 25.353 ;
; LPT_D[4]     ; DATA[12]      ; 24.867 ;        ;        ; 24.867 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 25.909 ; 25.909 ; 25.909 ; 25.909 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 24.686 ;        ;        ; 24.686 ;
; LPT_D[5]     ; DATA[5]       ; 25.140 ; 25.140 ; 25.140 ; 25.140 ;
; LPT_D[5]     ; DATA[13]      ; 23.875 ;        ;        ; 23.875 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 21.778 ; 21.778 ; 21.778 ; 21.778 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 20.565 ;        ;        ; 20.565 ;
; LPT_D[6]     ; DATA[6]       ; 25.178 ; 25.178 ; 25.178 ; 25.178 ;
; LPT_D[6]     ; DATA[14]      ; 24.375 ; 24.375 ; 24.375 ; 24.375 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 24.702 ; 24.702 ; 24.702 ; 24.702 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 21.799 ; 21.799 ; 21.799 ; 21.799 ;
; LPT_D[7]     ; DATA[7]       ; 23.518 ; 23.518 ; 23.518 ; 23.518 ;
; LPT_D[7]     ; DATA[15]      ; 24.533 ; 24.533 ; 24.533 ; 24.533 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 22.453 ; 22.453 ; 22.453 ; 22.453 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 21.509 ; 21.509 ; 21.509 ; 21.509 ;
; MIDI_IN      ; MIDI_TLR      ; 8.877  ;        ;        ; 8.877  ;
; RAM_DATA[0]  ; DATA[0]       ; 26.884 ;        ;        ; 26.884 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 22.273 ;        ;        ; 22.273 ;
; RAM_DATA[1]  ; DATA[1]       ; 24.806 ;        ;        ; 24.806 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 22.863 ;        ;        ; 22.863 ;
; RAM_DATA[2]  ; DATA[2]       ; 23.683 ;        ;        ; 23.683 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 21.395 ;        ;        ; 21.395 ;
; RAM_DATA[3]  ; DATA[3]       ; 24.444 ;        ;        ; 24.444 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 21.968 ;        ;        ; 21.968 ;
; RAM_DATA[4]  ; DATA[4]       ; 21.575 ; 21.575 ; 21.575 ; 21.575 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 22.131 ; 22.131 ; 22.131 ; 22.131 ;
; RAM_DATA[5]  ; DATA[5]       ; 25.171 ; 25.171 ; 25.171 ; 25.171 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 21.809 ; 21.809 ; 21.809 ; 21.809 ;
; RAM_DATA[6]  ; DATA[6]       ; 26.141 ; 26.141 ; 26.141 ; 26.141 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 25.665 ; 25.665 ; 25.665 ; 25.665 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.325 ; 22.325 ; 22.325 ; 22.325 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 21.260 ; 21.260 ; 21.260 ; 21.260 ;
; RAM_DATA[8]  ; DATA[8]       ; 23.154 ;        ;        ; 23.154 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 21.793 ;        ;        ; 21.793 ;
; RAM_DATA[9]  ; DATA[9]       ; 23.861 ;        ;        ; 23.861 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 21.995 ;        ;        ; 21.995 ;
; RAM_DATA[10] ; DATA[10]      ; 23.206 ;        ;        ; 23.206 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 22.935 ;        ;        ; 22.935 ;
; RAM_DATA[11] ; DATA[11]      ; 26.329 ;        ;        ; 26.329 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 22.117 ;        ;        ; 22.117 ;
; RAM_DATA[12] ; DATA[12]      ; 25.925 ;        ;        ; 25.925 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 25.744 ;        ;        ; 25.744 ;
; RAM_DATA[13] ; DATA[13]      ; 25.900 ;        ;        ; 25.900 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 22.590 ;        ;        ; 22.590 ;
; RAM_DATA[14] ; DATA[14]      ; 25.651 ; 25.651 ; 25.651 ; 25.651 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 23.075 ; 23.075 ; 23.075 ; 23.075 ;
; RAM_DATA[15] ; DATA[15]      ; 26.410 ; 26.410 ; 26.410 ; 26.410 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 23.386 ; 23.386 ; 23.386 ; 23.386 ;
; RWn          ; ACSI_RDn      ; 17.106 ; 17.106 ; 17.106 ; 17.106 ;
; RWn          ; ACSI_WRn      ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; RWn          ; ASn           ; 25.644 ; 25.644 ; 25.644 ; 25.644 ;
; RWn          ; BUTTONn       ;        ; 21.271 ; 21.271 ;        ;
; RWn          ; CA1_OUT       ;        ; 14.970 ; 14.970 ;        ;
; RWn          ; CD[0]         ; 22.937 ; 22.937 ; 22.937 ; 22.937 ;
; RWn          ; CD[1]         ; 22.422 ; 22.422 ; 22.422 ; 22.422 ;
; RWn          ; CD[2]         ; 21.863 ; 21.863 ; 21.863 ; 21.863 ;
; RWn          ; CD[3]         ; 23.402 ; 23.402 ; 23.402 ; 23.402 ;
; RWn          ; CD[4]         ; 22.344 ; 22.344 ; 22.344 ; 22.344 ;
; RWn          ; CD[5]         ; 21.508 ; 21.508 ; 21.508 ; 21.508 ;
; RWn          ; CD[6]         ; 24.182 ; 24.182 ; 24.182 ; 24.182 ;
; RWn          ; CD[7]         ; 21.861 ; 21.861 ; 21.861 ; 21.861 ;
; RWn          ; DATA[0]       ; 40.383 ; 41.014 ; 41.014 ; 40.383 ;
; RWn          ; DATA[1]       ; 39.852 ; 39.852 ; 39.852 ; 39.852 ;
; RWn          ; DATA[2]       ; 38.755 ; 38.755 ; 38.755 ; 38.755 ;
; RWn          ; DATA[3]       ; 41.012 ; 41.012 ; 41.012 ; 41.012 ;
; RWn          ; DATA[4]       ; 37.238 ; 37.238 ; 37.238 ; 37.238 ;
; RWn          ; DATA[5]       ; 39.346 ; 39.346 ; 39.346 ; 39.346 ;
; RWn          ; DATA[6]       ; 36.879 ; 36.879 ; 36.879 ; 36.879 ;
; RWn          ; DATA[7]       ; 39.419 ; 39.419 ; 39.419 ; 39.419 ;
; RWn          ; DATA[8]       ; 38.607 ; 38.607 ; 38.607 ; 38.607 ;
; RWn          ; DATA[9]       ; 39.385 ; 39.385 ; 39.385 ; 39.385 ;
; RWn          ; DATA[10]      ; 39.468 ; 39.468 ; 39.468 ; 39.468 ;
; RWn          ; DATA[11]      ; 40.935 ; 40.935 ; 40.935 ; 40.935 ;
; RWn          ; DATA[12]      ; 39.524 ; 39.524 ; 39.524 ; 39.524 ;
; RWn          ; DATA[13]      ; 40.158 ; 40.717 ; 40.717 ; 40.158 ;
; RWn          ; DATA[14]      ; 39.419 ; 39.419 ; 39.419 ; 39.419 ;
; RWn          ; DATA[15]      ; 40.144 ; 40.144 ; 40.144 ; 40.144 ;
; RWn          ; DTACKn        ; 30.748 ; 30.748 ; 30.748 ; 30.748 ;
; RWn          ; FC[0]         ; 26.523 ; 26.523 ; 26.523 ; 26.523 ;
; RWn          ; FC[1]         ; 25.983 ; 25.983 ; 25.983 ; 25.983 ;
; RWn          ; FC[2]         ; 25.983 ; 25.983 ; 25.983 ; 25.983 ;
; RWn          ; FLASH_CEn     ;        ; 24.017 ; 24.017 ;        ;
; RWn          ; FLASH_OEn     ;        ; 25.236 ; 25.236 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 19.342 ; 19.342 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 18.808 ;        ;        ; 18.808 ;
; RWn          ; IDE_IORDn     ;        ; 18.992 ; 18.992 ;        ;
; RWn          ; IDE_IOWRn     ; 19.035 ;        ;        ; 19.035 ;
; RWn          ; JOY_RHn       ; 20.869 ; 20.869 ; 20.869 ; 20.869 ;
; RWn          ; JOY_RLn       ; 22.898 ; 22.898 ; 22.898 ; 22.898 ;
; RWn          ; JOY_WEn       ; 22.868 ; 22.868 ; 22.868 ; 22.868 ;
; RWn          ; JOY_WL        ; 19.912 ; 19.912 ; 19.912 ; 19.912 ;
; RWn          ; LDSn          ; 26.947 ; 26.947 ; 26.947 ; 26.947 ;
; RWn          ; RAM_DATA[0]   ; 35.772 ; 36.403 ; 36.403 ; 35.772 ;
; RWn          ; RAM_DATA[1]   ; 37.909 ; 37.909 ; 37.909 ; 37.909 ;
; RWn          ; RAM_DATA[2]   ; 36.467 ; 36.467 ; 36.467 ; 36.467 ;
; RWn          ; RAM_DATA[3]   ; 38.536 ; 38.536 ; 38.536 ; 38.536 ;
; RWn          ; RAM_DATA[4]   ; 37.794 ; 37.794 ; 37.794 ; 37.794 ;
; RWn          ; RAM_DATA[5]   ; 35.984 ; 35.984 ; 35.984 ; 35.984 ;
; RWn          ; RAM_DATA[6]   ; 36.403 ; 36.403 ; 36.403 ; 36.403 ;
; RWn          ; RAM_DATA[7]   ; 38.354 ; 38.354 ; 38.354 ; 38.354 ;
; RWn          ; RAM_DATA[8]   ; 37.246 ; 37.246 ; 37.246 ; 37.246 ;
; RWn          ; RAM_DATA[9]   ; 37.519 ; 37.519 ; 37.519 ; 37.519 ;
; RWn          ; RAM_DATA[10]  ; 39.197 ; 39.197 ; 39.197 ; 39.197 ;
; RWn          ; RAM_DATA[11]  ; 36.723 ; 36.723 ; 36.723 ; 36.723 ;
; RWn          ; RAM_DATA[12]  ; 39.343 ; 39.343 ; 39.343 ; 39.343 ;
; RWn          ; RAM_DATA[13]  ; 36.848 ; 37.407 ; 37.407 ; 36.848 ;
; RWn          ; RAM_DATA[14]  ; 36.843 ; 36.843 ; 36.843 ; 36.843 ;
; RWn          ; RAM_DATA[15]  ; 37.120 ; 37.120 ; 37.120 ; 37.120 ;
; RWn          ; RAM_DQM0H     ;        ; 18.959 ; 18.959 ;        ;
; RWn          ; RAM_DQM0L     ;        ; 17.328 ; 17.328 ;        ;
; RWn          ; RAM_DQM1H     ;        ; 19.152 ; 19.152 ;        ;
; RWn          ; RAM_DQM1L     ;        ; 17.318 ; 17.318 ;        ;
; RWn          ; RAM_WEn       ; 20.396 ;        ;        ; 20.396 ;
; RWn          ; ROM0n         ;        ; 21.254 ; 21.254 ;        ;
; RWn          ; ROM1n         ;        ; 22.891 ; 22.891 ;        ;
; RWn          ; ROM2n         ;        ; 22.055 ; 22.055 ;        ;
; RWn          ; ROM3n         ;        ; 21.025 ; 21.025 ;        ;
; RWn          ; ROM4n         ;        ; 20.390 ; 20.390 ;        ;
; RWn          ; ROM5n         ;        ; 22.577 ; 22.577 ;        ;
; RWn          ; ROM6n         ;        ; 21.357 ; 21.357 ;        ;
; RWn          ; RWn           ; 27.239 ; 27.239 ; 27.239 ; 27.239 ;
; RWn          ; UDSn          ; 26.947 ; 26.947 ; 26.947 ; 26.947 ;
; SCSI_ACKn    ; CD[0]         ; 17.047 ; 17.047 ; 17.047 ; 17.047 ;
; SCSI_ATNn    ; CD[1]         ; 18.828 ; 18.828 ; 18.828 ; 18.828 ;
; SCSI_BSYn    ; CD[6]         ;        ; 14.677 ; 14.677 ;        ;
; SCSI_D[0]    ; CD[0]         ; 18.516 ; 18.516 ; 18.516 ; 18.516 ;
; SCSI_D[1]    ; CD[1]         ; 17.833 ; 17.833 ; 17.833 ; 17.833 ;
; SCSI_D[2]    ; CD[2]         ;        ; 16.505 ; 16.505 ;        ;
; SCSI_D[3]    ; CD[3]         ; 19.369 ; 19.369 ; 19.369 ; 19.369 ;
; SCSI_D[4]    ; CD[4]         ; 13.423 ; 13.423 ; 13.423 ; 13.423 ;
; SCSI_D[5]    ; CD[5]         ; 12.859 ; 12.859 ; 12.859 ; 12.859 ;
; SCSI_D[6]    ; CD[6]         ; 16.352 ; 16.352 ; 16.352 ; 16.352 ;
; SCSI_D[7]    ; CD[7]         ;        ; 16.836 ; 16.836 ;        ;
; SCSI_DCn     ; CD[3]         ; 19.850 ; 19.850 ; 19.850 ; 19.850 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 15.389 ; 15.389 ; 15.389 ; 15.389 ;
; SCSI_DCn     ; SCSI_D[0]     ; 17.015 ; 17.015 ; 17.015 ; 17.015 ;
; SCSI_DCn     ; SCSI_D[1]     ; 17.015 ; 17.015 ; 17.015 ; 17.015 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.219 ; 17.219 ; 17.219 ; 17.219 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.219 ; 17.219 ; 17.219 ; 17.219 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.242 ; 17.242 ; 17.242 ; 17.242 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.242 ; 17.242 ; 17.242 ; 17.242 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.252 ; 17.252 ; 17.252 ; 17.252 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.252 ; 17.252 ; 17.252 ; 17.252 ;
; SCSI_DCn     ; SCSI_DP       ; 17.025 ; 17.025 ; 17.025 ; 17.025 ;
; SCSI_DP      ; CD[0]         ; 17.420 ; 17.420 ; 17.420 ; 17.420 ;
; SCSI_IOn     ; CD[2]         ;        ; 16.223 ; 16.223 ;        ;
; SCSI_IOn     ; CD[3]         ; 20.247 ; 20.247 ; 20.247 ; 20.247 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 15.786 ; 15.786 ; 15.786 ; 15.786 ;
; SCSI_IOn     ; SCSI_D[0]     ; 17.412 ; 17.412 ; 17.412 ; 17.412 ;
; SCSI_IOn     ; SCSI_D[1]     ; 17.412 ; 17.412 ; 17.412 ; 17.412 ;
; SCSI_IOn     ; SCSI_D[2]     ; 17.616 ; 17.616 ; 17.616 ; 17.616 ;
; SCSI_IOn     ; SCSI_D[3]     ; 17.616 ; 17.616 ; 17.616 ; 17.616 ;
; SCSI_IOn     ; SCSI_D[4]     ; 17.639 ; 17.639 ; 17.639 ; 17.639 ;
; SCSI_IOn     ; SCSI_D[5]     ; 17.639 ; 17.639 ; 17.639 ; 17.639 ;
; SCSI_IOn     ; SCSI_D[6]     ; 17.649 ; 17.649 ; 17.649 ; 17.649 ;
; SCSI_IOn     ; SCSI_D[7]     ; 17.649 ; 17.649 ; 17.649 ; 17.649 ;
; SCSI_IOn     ; SCSI_DP       ; 17.422 ; 17.422 ; 17.422 ; 17.422 ;
; SCSI_IOn     ; SCSI_RDn      ; 12.208 ;        ;        ; 12.208 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 12.176 ; 12.176 ;        ;
; SCSI_MSGn    ; CD[3]         ; 19.442 ; 19.442 ; 19.442 ; 19.442 ;
; SCSI_MSGn    ; CD[4]         ;        ; 12.341 ; 12.341 ;        ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 14.981 ; 14.981 ; 14.981 ; 14.981 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 16.607 ; 16.607 ; 16.607 ; 16.607 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 16.607 ; 16.607 ; 16.607 ; 16.607 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.811 ; 16.811 ; 16.811 ; 16.811 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.811 ; 16.811 ; 16.811 ; 16.811 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.844 ; 16.844 ; 16.844 ; 16.844 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.844 ; 16.844 ; 16.844 ; 16.844 ;
; SCSI_MSGn    ; SCSI_DP       ; 16.617 ; 16.617 ; 16.617 ; 16.617 ;
; SCSI_REQn    ; CD[3]         ; 19.496 ; 19.496 ; 19.496 ; 19.496 ;
; SCSI_REQn    ; CD[5]         ;        ; 12.083 ; 12.083 ;        ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 15.035 ;        ;        ; 15.035 ;
; SCSI_REQn    ; SCSI_D[0]     ; 16.661 ; 16.661 ; 16.661 ; 16.661 ;
; SCSI_REQn    ; SCSI_D[1]     ; 16.661 ; 16.661 ; 16.661 ; 16.661 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.865 ; 16.865 ; 16.865 ; 16.865 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.865 ; 16.865 ; 16.865 ; 16.865 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.888 ; 16.888 ; 16.888 ; 16.888 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.888 ; 16.888 ; 16.888 ; 16.888 ;
; SCSI_REQn    ; SCSI_D[6]     ; 16.898 ; 16.898 ; 16.898 ; 16.898 ;
; SCSI_REQn    ; SCSI_D[7]     ; 16.898 ; 16.898 ; 16.898 ; 16.898 ;
; SCSI_REQn    ; SCSI_DP       ; 16.671 ; 16.671 ; 16.671 ; 16.671 ;
; SCSI_RSTn    ; CD[7]         ;        ; 15.894 ; 15.894 ;        ;
; SCSI_SELn    ; CD[1]         ; 17.164 ; 17.164 ; 17.164 ; 17.164 ;
; SD_AVR_ENn   ; RESETn        ;        ; 14.448 ; 14.448 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 14.563 ; 14.563 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 14.608 ; 14.608 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 12.038 ;        ;        ; 12.038 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 12.534 ;        ;        ; 12.534 ;
; SD_RESETn    ; COM_TxD       ; 17.660 ; 17.660 ; 17.660 ; 17.660 ;
; UDSn         ; ACSI_RDn      ; 19.826 ; 19.826 ; 19.826 ; 19.826 ;
; UDSn         ; ACSI_WRn      ; 19.816 ; 19.816 ; 19.816 ; 19.816 ;
; UDSn         ; ASn           ; 27.851 ; 27.851 ; 27.851 ; 27.851 ;
; UDSn         ; CA1_OUT       ; 17.690 ;        ;        ; 17.690 ;
; UDSn         ; CD[0]         ; 25.657 ; 25.657 ; 25.657 ; 25.657 ;
; UDSn         ; CD[1]         ; 25.142 ; 25.142 ; 25.142 ; 25.142 ;
; UDSn         ; CD[2]         ; 24.583 ; 24.583 ; 24.583 ; 24.583 ;
; UDSn         ; CD[3]         ; 26.122 ; 26.122 ; 26.122 ; 26.122 ;
; UDSn         ; CD[4]         ; 25.064 ; 25.064 ; 25.064 ; 25.064 ;
; UDSn         ; CD[5]         ; 24.228 ; 24.228 ; 24.228 ; 24.228 ;
; UDSn         ; CD[6]         ; 26.902 ; 26.902 ; 26.902 ; 26.902 ;
; UDSn         ; CD[7]         ; 24.581 ; 24.581 ; 24.581 ; 24.581 ;
; UDSn         ; DATA[0]       ; 39.108 ; 39.108 ; 39.108 ; 39.108 ;
; UDSn         ; DATA[1]       ; 39.094 ; 39.094 ; 39.094 ; 39.094 ;
; UDSn         ; DATA[2]       ; 38.116 ; 38.116 ; 38.116 ; 38.116 ;
; UDSn         ; DATA[3]       ; 37.784 ; 38.142 ; 38.142 ; 37.784 ;
; UDSn         ; DATA[4]       ; 37.132 ; 37.132 ; 37.132 ; 37.132 ;
; UDSn         ; DATA[5]       ; 40.419 ; 40.419 ; 40.419 ; 40.419 ;
; UDSn         ; DATA[6]       ; 37.985 ; 37.985 ; 37.985 ; 37.985 ;
; UDSn         ; DATA[7]       ; 38.267 ; 38.267 ; 38.267 ; 38.267 ;
; UDSn         ; DATA[8]       ; 37.873 ; 37.873 ; 37.873 ; 37.873 ;
; UDSn         ; DATA[9]       ; 39.129 ; 38.820 ; 38.820 ; 39.129 ;
; UDSn         ; DATA[10]      ; 39.464 ; 39.464 ; 39.464 ; 39.464 ;
; UDSn         ; DATA[11]      ; 42.190 ; 41.471 ; 41.471 ; 42.190 ;
; UDSn         ; DATA[12]      ; 37.749 ; 36.540 ; 36.540 ; 37.749 ;
; UDSn         ; DATA[13]      ; 39.130 ; 38.549 ; 38.549 ; 39.130 ;
; UDSn         ; DATA[14]      ; 37.567 ; 37.567 ; 37.567 ; 37.567 ;
; UDSn         ; DATA[15]      ; 38.472 ; 38.472 ; 38.472 ; 38.472 ;
; UDSn         ; DTACKn        ; 28.203 ; 28.203 ; 28.203 ; 28.203 ;
; UDSn         ; FC[0]         ; 28.730 ; 28.730 ; 28.730 ; 28.730 ;
; UDSn         ; FC[1]         ; 28.190 ; 28.190 ; 28.190 ; 28.190 ;
; UDSn         ; FC[2]         ; 28.190 ; 28.190 ; 28.190 ; 28.190 ;
; UDSn         ; JOY_RHn       ; 16.263 ;        ;        ; 16.263 ;
; UDSn         ; LDSn          ; 29.154 ; 29.154 ; 29.154 ; 29.154 ;
; UDSn         ; RAM_CAS0n     ; 20.534 ;        ;        ; 20.534 ;
; UDSn         ; RAM_CAS1n     ; 19.716 ;        ;        ; 19.716 ;
; UDSn         ; RAM_DATA[0]   ; 34.497 ; 34.497 ; 34.497 ; 34.497 ;
; UDSn         ; RAM_DATA[1]   ; 37.151 ; 37.151 ; 37.151 ; 37.151 ;
; UDSn         ; RAM_DATA[2]   ; 35.828 ; 35.828 ; 35.828 ; 35.828 ;
; UDSn         ; RAM_DATA[3]   ; 35.308 ; 35.666 ; 35.666 ; 35.308 ;
; UDSn         ; RAM_DATA[4]   ; 37.688 ; 37.688 ; 37.688 ; 37.688 ;
; UDSn         ; RAM_DATA[5]   ; 37.057 ; 37.057 ; 37.057 ; 37.057 ;
; UDSn         ; RAM_DATA[6]   ; 37.509 ; 37.509 ; 37.509 ; 37.509 ;
; UDSn         ; RAM_DATA[7]   ; 37.202 ; 37.202 ; 37.202 ; 37.202 ;
; UDSn         ; RAM_DATA[8]   ; 36.512 ; 36.512 ; 36.512 ; 36.512 ;
; UDSn         ; RAM_DATA[9]   ; 37.263 ; 36.954 ; 36.954 ; 37.263 ;
; UDSn         ; RAM_DATA[10]  ; 39.193 ; 39.193 ; 39.193 ; 39.193 ;
; UDSn         ; RAM_DATA[11]  ; 37.978 ; 37.259 ; 37.259 ; 37.978 ;
; UDSn         ; RAM_DATA[12]  ; 37.568 ; 36.359 ; 36.359 ; 37.568 ;
; UDSn         ; RAM_DATA[13]  ; 35.820 ; 35.239 ; 35.239 ; 35.820 ;
; UDSn         ; RAM_DATA[14]  ; 34.991 ; 34.991 ; 34.991 ; 34.991 ;
; UDSn         ; RAM_DATA[15]  ; 35.448 ; 35.448 ; 35.448 ; 35.448 ;
; UDSn         ; RAM_DQM0H     ; 25.446 ; 25.016 ; 25.016 ; 25.446 ;
; UDSn         ; RAM_DQM0L     ; 23.765 ; 23.386 ; 23.386 ; 23.765 ;
; UDSn         ; RAM_DQM1H     ; 25.639 ; 25.209 ; 25.209 ; 25.639 ;
; UDSn         ; RAM_DQM1L     ; 23.755 ; 23.376 ; 23.376 ; 23.755 ;
; UDSn         ; RWn           ; 29.446 ; 29.446 ; 29.446 ; 29.446 ;
; UDSn         ; UDSn          ; 29.154 ; 29.154 ; 29.154 ; 29.154 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ADR[1]       ; DATA[0]       ; 25.571 ; 25.571 ; 25.571 ; 25.571 ;
; ADR[1]       ; DATA[1]       ; 24.237 ; 24.237 ; 24.237 ; 24.237 ;
; ADR[1]       ; DATA[2]       ; 23.958 ; 23.469 ; 23.469 ; 23.958 ;
; ADR[1]       ; DATA[3]       ; 24.606 ; 25.347 ; 25.347 ; 24.606 ;
; ADR[1]       ; DATA[4]       ; 22.307 ; 22.307 ; 22.307 ; 22.307 ;
; ADR[1]       ; DATA[5]       ; 24.686 ; 24.686 ; 24.686 ; 24.686 ;
; ADR[1]       ; DATA[6]       ; 22.955 ; 22.955 ; 22.955 ; 22.955 ;
; ADR[1]       ; DATA[7]       ; 24.087 ; 24.087 ; 24.087 ; 24.087 ;
; ADR[1]       ; DATA[8]       ; 23.795 ; 23.795 ; 23.795 ; 23.795 ;
; ADR[1]       ; DATA[9]       ; 23.435 ; 23.435 ; 23.435 ; 23.435 ;
; ADR[1]       ; DATA[10]      ; 24.671 ; 24.182 ; 24.182 ; 24.671 ;
; ADR[1]       ; DATA[11]      ; 26.120 ; 25.270 ; 25.270 ; 26.120 ;
; ADR[1]       ; DATA[12]      ; 24.593 ; 24.593 ; 24.593 ; 24.593 ;
; ADR[1]       ; DATA[13]      ; 25.339 ; 25.249 ; 25.249 ; 25.339 ;
; ADR[1]       ; DATA[14]      ; 25.495 ; 25.495 ; 25.495 ; 25.495 ;
; ADR[1]       ; DATA[15]      ; 25.726 ; 25.726 ; 25.726 ; 25.726 ;
; ADR[1]       ; RAM_DATA[0]   ; 20.960 ; 20.960 ; 20.960 ; 20.960 ;
; ADR[1]       ; RAM_DATA[1]   ; 22.294 ; 22.294 ; 22.294 ; 22.294 ;
; ADR[1]       ; RAM_DATA[2]   ; 21.670 ; 21.181 ; 21.181 ; 21.670 ;
; ADR[1]       ; RAM_DATA[3]   ; 22.130 ; 22.871 ; 22.871 ; 22.130 ;
; ADR[1]       ; RAM_DATA[4]   ; 22.863 ; 22.863 ; 22.863 ; 22.863 ;
; ADR[1]       ; RAM_DATA[5]   ; 21.324 ; 21.324 ; 21.324 ; 21.324 ;
; ADR[1]       ; RAM_DATA[6]   ; 22.479 ; 22.479 ; 22.479 ; 22.479 ;
; ADR[1]       ; RAM_DATA[7]   ; 23.022 ; 23.022 ; 23.022 ; 23.022 ;
; ADR[1]       ; RAM_DATA[8]   ; 22.434 ; 22.434 ; 22.434 ; 22.434 ;
; ADR[1]       ; RAM_DATA[9]   ; 21.569 ; 21.569 ; 21.569 ; 21.569 ;
; ADR[1]       ; RAM_DATA[10]  ; 24.400 ; 23.911 ; 23.911 ; 24.400 ;
; ADR[1]       ; RAM_DATA[11]  ; 21.908 ; 21.058 ; 21.058 ; 21.908 ;
; ADR[1]       ; RAM_DATA[12]  ; 24.412 ; 24.412 ; 24.412 ; 24.412 ;
; ADR[1]       ; RAM_DATA[13]  ; 22.029 ; 21.939 ; 21.939 ; 22.029 ;
; ADR[1]       ; RAM_DATA[14]  ; 22.919 ; 22.919 ; 22.919 ; 22.919 ;
; ADR[1]       ; RAM_DATA[15]  ; 22.702 ; 22.702 ; 22.702 ; 22.702 ;
; ADR[2]       ; DATA[0]       ; 25.780 ; 26.644 ; 26.644 ; 25.780 ;
; ADR[2]       ; DATA[1]       ; 25.500 ; 25.727 ; 25.727 ; 25.500 ;
; ADR[2]       ; DATA[2]       ; 24.893 ; 24.597 ; 24.597 ; 24.893 ;
; ADR[2]       ; DATA[3]       ; 25.733 ; 26.475 ; 26.475 ; 25.733 ;
; ADR[2]       ; DATA[4]       ; 23.117 ; 23.117 ; 23.117 ; 23.117 ;
; ADR[2]       ; DATA[5]       ; 23.907 ; 23.907 ; 23.907 ; 23.907 ;
; ADR[2]       ; DATA[6]       ; 23.528 ; 23.528 ; 23.528 ; 23.528 ;
; ADR[2]       ; DATA[7]       ; 25.214 ; 25.214 ; 25.214 ; 25.214 ;
; ADR[2]       ; DATA[8]       ; 24.004 ; 24.868 ; 24.868 ; 24.004 ;
; ADR[2]       ; DATA[9]       ; 24.698 ; 24.925 ; 24.925 ; 24.698 ;
; ADR[2]       ; DATA[10]      ; 25.606 ; 25.310 ; 25.310 ; 25.606 ;
; ADR[2]       ; DATA[11]      ; 27.012 ; 26.398 ; 26.398 ; 27.012 ;
; ADR[2]       ; DATA[12]      ; 25.403 ; 25.775 ; 25.775 ; 25.403 ;
; ADR[2]       ; DATA[13]      ; 24.560 ; 24.560 ; 24.560 ; 24.560 ;
; ADR[2]       ; DATA[14]      ; 26.068 ; 26.068 ; 26.068 ; 26.068 ;
; ADR[2]       ; DATA[15]      ; 26.578 ; 26.578 ; 26.578 ; 26.578 ;
; ADR[2]       ; RAM_DATA[0]   ; 21.169 ; 22.033 ; 22.033 ; 21.169 ;
; ADR[2]       ; RAM_DATA[1]   ; 23.557 ; 23.784 ; 23.784 ; 23.557 ;
; ADR[2]       ; RAM_DATA[2]   ; 22.605 ; 22.309 ; 22.309 ; 22.605 ;
; ADR[2]       ; RAM_DATA[3]   ; 23.257 ; 23.999 ; 23.999 ; 23.257 ;
; ADR[2]       ; RAM_DATA[4]   ; 23.673 ; 23.673 ; 23.673 ; 23.673 ;
; ADR[2]       ; RAM_DATA[5]   ; 20.545 ; 20.545 ; 20.545 ; 20.545 ;
; ADR[2]       ; RAM_DATA[6]   ; 23.052 ; 23.052 ; 23.052 ; 23.052 ;
; ADR[2]       ; RAM_DATA[7]   ; 24.149 ; 24.149 ; 24.149 ; 24.149 ;
; ADR[2]       ; RAM_DATA[8]   ; 22.643 ; 23.507 ; 23.507 ; 22.643 ;
; ADR[2]       ; RAM_DATA[9]   ; 22.832 ; 23.059 ; 23.059 ; 22.832 ;
; ADR[2]       ; RAM_DATA[10]  ; 25.335 ; 25.039 ; 25.039 ; 25.335 ;
; ADR[2]       ; RAM_DATA[11]  ; 22.800 ; 22.186 ; 22.186 ; 22.800 ;
; ADR[2]       ; RAM_DATA[12]  ; 25.222 ; 25.594 ; 25.594 ; 25.222 ;
; ADR[2]       ; RAM_DATA[13]  ; 21.250 ; 21.250 ; 21.250 ; 21.250 ;
; ADR[2]       ; RAM_DATA[14]  ; 23.492 ; 23.492 ; 23.492 ; 23.492 ;
; ADR[2]       ; RAM_DATA[15]  ; 23.554 ; 23.554 ; 23.554 ; 23.554 ;
; ADR[3]       ; DATA[0]       ; 25.280 ; 25.280 ; 25.280 ; 25.280 ;
; ADR[3]       ; DATA[1]       ; 25.042 ; 24.559 ; 24.559 ; 25.042 ;
; ADR[3]       ; DATA[2]       ; 23.569 ; 23.386 ; 23.386 ; 23.569 ;
; ADR[3]       ; DATA[3]       ; 24.553 ; 24.593 ; 24.593 ; 24.553 ;
; ADR[3]       ; DATA[4]       ; 22.346 ; 22.346 ; 22.346 ; 22.346 ;
; ADR[3]       ; DATA[5]       ; 24.616 ; 24.616 ; 24.616 ; 24.616 ;
; ADR[3]       ; DATA[6]       ; 22.407 ; 22.407 ; 22.407 ; 22.407 ;
; ADR[3]       ; DATA[7]       ; 24.034 ; 24.034 ; 24.034 ; 24.034 ;
; ADR[3]       ; DATA[8]       ; 23.504 ; 23.504 ; 23.504 ; 23.504 ;
; ADR[3]       ; DATA[9]       ; 24.336 ; 23.757 ; 23.757 ; 24.336 ;
; ADR[3]       ; DATA[10]      ; 24.282 ; 24.099 ; 24.099 ; 24.282 ;
; ADR[3]       ; DATA[11]      ; 25.443 ; 25.227 ; 25.227 ; 25.443 ;
; ADR[3]       ; DATA[12]      ; 24.859 ; 24.632 ; 24.632 ; 24.859 ;
; ADR[3]       ; DATA[13]      ; 25.236 ; 25.196 ; 25.196 ; 25.236 ;
; ADR[3]       ; DATA[14]      ; 24.947 ; 24.947 ; 24.947 ; 24.947 ;
; ADR[3]       ; DATA[15]      ; 25.207 ; 25.207 ; 25.207 ; 25.207 ;
; ADR[3]       ; RAM_DATA[0]   ; 20.669 ; 20.669 ; 20.669 ; 20.669 ;
; ADR[3]       ; RAM_DATA[1]   ; 23.099 ; 22.616 ; 22.616 ; 23.099 ;
; ADR[3]       ; RAM_DATA[2]   ; 21.281 ; 21.098 ; 21.098 ; 21.281 ;
; ADR[3]       ; RAM_DATA[3]   ; 22.077 ; 22.117 ; 22.117 ; 22.077 ;
; ADR[3]       ; RAM_DATA[4]   ; 22.902 ; 22.902 ; 22.902 ; 22.902 ;
; ADR[3]       ; RAM_DATA[5]   ; 21.254 ; 21.254 ; 21.254 ; 21.254 ;
; ADR[3]       ; RAM_DATA[6]   ; 21.931 ; 21.931 ; 21.931 ; 21.931 ;
; ADR[3]       ; RAM_DATA[7]   ; 22.969 ; 22.969 ; 22.969 ; 22.969 ;
; ADR[3]       ; RAM_DATA[8]   ; 22.143 ; 22.143 ; 22.143 ; 22.143 ;
; ADR[3]       ; RAM_DATA[9]   ; 22.470 ; 21.891 ; 21.891 ; 22.470 ;
; ADR[3]       ; RAM_DATA[10]  ; 24.011 ; 23.828 ; 23.828 ; 24.011 ;
; ADR[3]       ; RAM_DATA[11]  ; 21.231 ; 21.015 ; 21.015 ; 21.231 ;
; ADR[3]       ; RAM_DATA[12]  ; 24.678 ; 24.451 ; 24.451 ; 24.678 ;
; ADR[3]       ; RAM_DATA[13]  ; 21.926 ; 21.886 ; 21.886 ; 21.926 ;
; ADR[3]       ; RAM_DATA[14]  ; 22.371 ; 22.371 ; 22.371 ; 22.371 ;
; ADR[3]       ; RAM_DATA[15]  ; 22.183 ; 22.183 ; 22.183 ; 22.183 ;
; ADR[4]       ; DATA[0]       ; 25.842 ; 25.842 ; 25.842 ; 25.842 ;
; ADR[4]       ; DATA[1]       ; 24.389 ; 24.751 ; 24.751 ; 24.389 ;
; ADR[4]       ; DATA[2]       ; 23.029 ; 23.793 ; 23.793 ; 23.029 ;
; ADR[4]       ; DATA[3]       ; 24.824 ; 24.262 ; 24.262 ; 24.824 ;
; ADR[4]       ; DATA[4]       ; 22.602 ; 22.602 ; 22.602 ; 22.602 ;
; ADR[4]       ; DATA[5]       ; 24.576 ; 24.576 ; 24.576 ; 24.576 ;
; ADR[4]       ; DATA[6]       ; 22.515 ; 22.515 ; 22.515 ; 22.515 ;
; ADR[4]       ; DATA[7]       ; 23.743 ; 23.743 ; 23.743 ; 23.743 ;
; ADR[4]       ; DATA[8]       ; 24.066 ; 24.048 ; 24.048 ; 24.066 ;
; ADR[4]       ; DATA[9]       ; 23.587 ; 24.107 ; 24.107 ; 23.587 ;
; ADR[4]       ; DATA[10]      ; 23.742 ; 24.505 ; 24.505 ; 23.742 ;
; ADR[4]       ; DATA[11]      ; 24.830 ; 25.680 ; 25.680 ; 24.830 ;
; ADR[4]       ; DATA[12]      ; 24.528 ; 24.996 ; 24.996 ; 24.528 ;
; ADR[4]       ; DATA[13]      ; 24.905 ; 25.324 ; 25.324 ; 24.905 ;
; ADR[4]       ; DATA[14]      ; 25.055 ; 25.055 ; 25.055 ; 25.055 ;
; ADR[4]       ; DATA[15]      ; 25.370 ; 25.370 ; 25.370 ; 25.370 ;
; ADR[4]       ; RAM_DATA[0]   ; 21.231 ; 21.231 ; 21.231 ; 21.231 ;
; ADR[4]       ; RAM_DATA[1]   ; 22.446 ; 22.808 ; 22.808 ; 22.446 ;
; ADR[4]       ; RAM_DATA[2]   ; 20.741 ; 21.505 ; 21.505 ; 20.741 ;
; ADR[4]       ; RAM_DATA[3]   ; 22.348 ; 21.786 ; 21.786 ; 22.348 ;
; ADR[4]       ; RAM_DATA[4]   ; 23.158 ; 23.158 ; 23.158 ; 23.158 ;
; ADR[4]       ; RAM_DATA[5]   ; 21.214 ; 21.214 ; 21.214 ; 21.214 ;
; ADR[4]       ; RAM_DATA[6]   ; 22.039 ; 22.039 ; 22.039 ; 22.039 ;
; ADR[4]       ; RAM_DATA[7]   ; 22.678 ; 22.678 ; 22.678 ; 22.678 ;
; ADR[4]       ; RAM_DATA[8]   ; 22.705 ; 22.687 ; 22.687 ; 22.705 ;
; ADR[4]       ; RAM_DATA[9]   ; 21.721 ; 22.241 ; 22.241 ; 21.721 ;
; ADR[4]       ; RAM_DATA[10]  ; 23.471 ; 24.234 ; 24.234 ; 23.471 ;
; ADR[4]       ; RAM_DATA[11]  ; 20.618 ; 21.468 ; 21.468 ; 20.618 ;
; ADR[4]       ; RAM_DATA[12]  ; 24.347 ; 24.815 ; 24.815 ; 24.347 ;
; ADR[4]       ; RAM_DATA[13]  ; 21.595 ; 22.014 ; 22.014 ; 21.595 ;
; ADR[4]       ; RAM_DATA[14]  ; 22.479 ; 22.479 ; 22.479 ; 22.479 ;
; ADR[4]       ; RAM_DATA[15]  ; 22.346 ; 22.346 ; 22.346 ; 22.346 ;
; ADR[5]       ; DATA[0]       ; 26.134 ; 26.535 ; 26.535 ; 26.134 ;
; ADR[5]       ; DATA[1]       ; 24.807 ; 25.238 ; 25.238 ; 24.807 ;
; ADR[5]       ; DATA[2]       ; 24.306 ; 23.878 ; 23.878 ; 24.306 ;
; ADR[5]       ; DATA[3]       ; 24.318 ; 25.350 ; 25.350 ; 24.318 ;
; ADR[5]       ; DATA[4]       ; 23.377 ; 23.377 ; 23.377 ; 23.377 ;
; ADR[5]       ; DATA[5]       ; 24.809 ; 24.809 ; 24.809 ; 24.809 ;
; ADR[5]       ; DATA[6]       ; 23.267 ; 23.267 ; 23.267 ; 23.267 ;
; ADR[5]       ; DATA[7]       ; 23.799 ; 23.799 ; 23.799 ; 23.799 ;
; ADR[5]       ; DATA[8]       ; 24.104 ; 24.759 ; 24.759 ; 24.104 ;
; ADR[5]       ; DATA[9]       ; 24.956 ; 24.436 ; 24.436 ; 24.956 ;
; ADR[5]       ; DATA[10]      ; 24.561 ; 24.591 ; 24.591 ; 24.561 ;
; ADR[5]       ; DATA[11]      ; 26.529 ; 25.679 ; 25.679 ; 26.529 ;
; ADR[5]       ; DATA[12]      ; 25.052 ; 24.584 ; 24.584 ; 25.052 ;
; ADR[5]       ; DATA[13]      ; 25.380 ; 24.961 ; 24.961 ; 25.380 ;
; ADR[5]       ; DATA[14]      ; 25.439 ; 25.439 ; 25.439 ; 25.439 ;
; ADR[5]       ; DATA[15]      ; 25.438 ; 25.438 ; 25.438 ; 25.438 ;
; ADR[5]       ; RAM_DATA[0]   ; 21.523 ; 21.924 ; 21.924 ; 21.523 ;
; ADR[5]       ; RAM_DATA[1]   ; 22.864 ; 23.295 ; 23.295 ; 22.864 ;
; ADR[5]       ; RAM_DATA[2]   ; 22.018 ; 21.590 ; 21.590 ; 22.018 ;
; ADR[5]       ; RAM_DATA[3]   ; 21.842 ; 22.874 ; 22.874 ; 21.842 ;
; ADR[5]       ; RAM_DATA[4]   ; 23.933 ; 23.933 ; 23.933 ; 23.933 ;
; ADR[5]       ; RAM_DATA[5]   ; 21.447 ; 21.447 ; 21.447 ; 21.447 ;
; ADR[5]       ; RAM_DATA[6]   ; 22.791 ; 22.791 ; 22.791 ; 22.791 ;
; ADR[5]       ; RAM_DATA[7]   ; 22.734 ; 22.734 ; 22.734 ; 22.734 ;
; ADR[5]       ; RAM_DATA[8]   ; 22.743 ; 23.398 ; 23.398 ; 22.743 ;
; ADR[5]       ; RAM_DATA[9]   ; 23.090 ; 22.570 ; 22.570 ; 23.090 ;
; ADR[5]       ; RAM_DATA[10]  ; 24.290 ; 24.320 ; 24.320 ; 24.290 ;
; ADR[5]       ; RAM_DATA[11]  ; 22.317 ; 21.467 ; 21.467 ; 22.317 ;
; ADR[5]       ; RAM_DATA[12]  ; 24.871 ; 24.403 ; 24.403 ; 24.871 ;
; ADR[5]       ; RAM_DATA[13]  ; 22.070 ; 21.651 ; 21.651 ; 22.070 ;
; ADR[5]       ; RAM_DATA[14]  ; 22.863 ; 22.863 ; 22.863 ; 22.863 ;
; ADR[5]       ; RAM_DATA[15]  ; 22.414 ; 22.414 ; 22.414 ; 22.414 ;
; ASn          ; ACSI_RDn      ; 22.214 ; 22.214 ; 22.214 ; 22.214 ;
; ASn          ; ACSI_WRn      ; 22.204 ; 22.204 ; 22.204 ; 22.204 ;
; ASn          ; ASn           ; 23.245 ; 23.245 ; 23.245 ; 23.245 ;
; ASn          ; BUTTONn       ; 17.200 ;        ;        ; 17.200 ;
; ASn          ; CA1_OUT       ; 20.078 ;        ;        ; 20.078 ;
; ASn          ; CD[0]         ; 22.802 ; 22.802 ; 22.802 ; 22.802 ;
; ASn          ; CD[1]         ; 22.792 ; 22.792 ; 22.792 ; 22.792 ;
; ASn          ; CD[2]         ; 22.423 ; 22.423 ; 22.423 ; 22.423 ;
; ASn          ; CD[3]         ; 22.792 ; 22.792 ; 22.792 ; 22.792 ;
; ASn          ; CD[4]         ; 22.432 ; 22.432 ; 22.432 ; 22.432 ;
; ASn          ; CD[5]         ; 22.432 ; 22.432 ; 22.432 ; 22.432 ;
; ASn          ; CD[6]         ; 22.396 ; 22.396 ; 22.396 ; 22.396 ;
; ASn          ; CD[7]         ; 22.396 ; 22.396 ; 22.396 ; 22.396 ;
; ASn          ; DATA[0]       ; 23.488 ; 23.488 ; 23.488 ; 23.488 ;
; ASn          ; DATA[1]       ; 23.488 ; 23.203 ; 23.203 ; 23.488 ;
; ASn          ; DATA[2]       ; 23.466 ; 23.466 ; 23.466 ; 23.466 ;
; ASn          ; DATA[3]       ; 23.466 ; 23.466 ; 23.466 ; 23.466 ;
; ASn          ; DATA[4]       ; 22.191 ; 22.191 ; 22.191 ; 22.191 ;
; ASn          ; DATA[5]       ; 23.304 ; 23.304 ; 23.304 ; 23.304 ;
; ASn          ; DATA[6]       ; 21.770 ; 21.770 ; 21.770 ; 21.770 ;
; ASn          ; DATA[7]       ; 22.194 ; 22.194 ; 22.194 ; 22.194 ;
; ASn          ; DATA[8]       ; 22.943 ; 22.943 ; 22.943 ; 22.943 ;
; ASn          ; DATA[9]       ; 23.085 ; 23.085 ; 23.085 ; 23.085 ;
; ASn          ; DATA[10]      ; 23.115 ; 23.115 ; 23.115 ; 23.115 ;
; ASn          ; DATA[11]      ; 23.115 ; 23.115 ; 23.115 ; 23.115 ;
; ASn          ; DATA[12]      ; 22.469 ; 22.469 ; 22.469 ; 22.469 ;
; ASn          ; DATA[13]      ; 23.121 ; 23.121 ; 23.121 ; 23.121 ;
; ASn          ; DATA[14]      ; 21.357 ; 21.357 ; 21.357 ; 21.357 ;
; ASn          ; DATA[15]      ; 21.747 ; 21.747 ; 21.747 ; 21.747 ;
; ASn          ; DTACKn        ; 19.340 ; 19.340 ; 19.340 ; 19.340 ;
; ASn          ; FC[0]         ; 24.124 ; 24.124 ; 24.124 ; 24.124 ;
; ASn          ; FC[1]         ; 23.584 ; 23.584 ; 23.584 ; 23.584 ;
; ASn          ; FC[2]         ; 23.584 ; 23.584 ; 23.584 ; 23.584 ;
; ASn          ; FLASH_CEn     ; 20.062 ;        ;        ; 20.062 ;
; ASn          ; FLASH_OEn     ; 21.281 ;        ;        ; 21.281 ;
; ASn          ; IDE_CS0n      ; 15.332 ;        ;        ; 15.332 ;
; ASn          ; IDE_CS1n      ; 15.024 ;        ;        ; 15.024 ;
; ASn          ; IDE_D_EN_INn  ; 15.673 ;        ;        ; 15.673 ;
; ASn          ; IDE_D_EN_OUTn ; 15.027 ;        ;        ; 15.027 ;
; ASn          ; IDE_IORDn     ; 15.148 ;        ;        ; 15.148 ;
; ASn          ; IDE_IOWRn     ; 15.024 ;        ;        ; 15.024 ;
; ASn          ; JOY_RHn       ; 15.313 ;        ;        ; 15.313 ;
; ASn          ; JOY_RLn       ; 17.333 ;        ;        ; 17.333 ;
; ASn          ; JOY_WEn       ;        ; 17.303 ; 17.303 ;        ;
; ASn          ; JOY_WL        ;        ; 14.557 ; 14.557 ;        ;
; ASn          ; LDSn          ; 24.548 ; 24.548 ; 24.548 ; 24.548 ;
; ASn          ; RAM_DATA[0]   ; 20.088 ; 19.640 ; 19.640 ; 20.088 ;
; ASn          ; RAM_DATA[1]   ; 21.705 ; 21.260 ; 21.260 ; 21.705 ;
; ASn          ; RAM_DATA[2]   ; 21.183 ; 21.183 ; 21.183 ; 21.183 ;
; ASn          ; RAM_DATA[3]   ; 21.187 ; 21.187 ; 21.187 ; 21.187 ;
; ASn          ; RAM_DATA[4]   ; 22.747 ; 22.747 ; 22.747 ; 22.747 ;
; ASn          ; RAM_DATA[5]   ; 21.321 ; 21.321 ; 21.321 ; 21.321 ;
; ASn          ; RAM_DATA[6]   ; 21.294 ; 21.294 ; 21.294 ; 21.294 ;
; ASn          ; RAM_DATA[7]   ; 21.129 ; 21.129 ; 21.129 ; 21.129 ;
; ASn          ; RAM_DATA[8]   ; 21.582 ; 21.582 ; 21.582 ; 21.582 ;
; ASn          ; RAM_DATA[9]   ; 22.020 ; 21.845 ; 21.845 ; 22.020 ;
; ASn          ; RAM_DATA[10]  ; 23.507 ; 23.663 ; 23.663 ; 23.507 ;
; ASn          ; RAM_DATA[11]  ; 21.612 ; 21.612 ; 21.612 ; 21.612 ;
; ASn          ; RAM_DATA[12]  ; 22.288 ; 22.288 ; 22.288 ; 22.288 ;
; ASn          ; RAM_DATA[13]  ; 22.490 ; 22.490 ; 22.490 ; 22.490 ;
; ASn          ; RAM_DATA[14]  ; 18.781 ; 18.781 ; 18.781 ; 18.781 ;
; ASn          ; RAM_DATA[15]  ; 18.723 ; 18.723 ; 18.723 ; 18.723 ;
; ASn          ; ROM0n         ; 17.866 ;        ;        ; 17.866 ;
; ASn          ; ROM1n         ; 19.503 ;        ;        ; 19.503 ;
; ASn          ; ROM2n         ; 18.100 ;        ;        ; 18.100 ;
; ASn          ; ROM3n         ; 17.070 ;        ;        ; 17.070 ;
; ASn          ; ROM4n         ; 16.435 ;        ;        ; 16.435 ;
; ASn          ; ROM5n         ; 19.189 ;        ;        ; 19.189 ;
; ASn          ; ROM6n         ; 17.402 ;        ;        ; 17.402 ;
; ASn          ; RWn           ; 24.840 ; 24.840 ; 24.840 ; 24.840 ;
; ASn          ; UDSn          ; 24.548 ; 24.548 ; 24.548 ; 24.548 ;
; CD[0]        ; DATA[0]       ; 23.621 ;        ;        ; 23.621 ;
; CD[0]        ; RAM_DATA[0]   ; 19.010 ;        ;        ; 19.010 ;
; CD[1]        ; DATA[1]       ; 21.999 ;        ;        ; 21.999 ;
; CD[1]        ; RAM_DATA[1]   ; 20.056 ;        ;        ; 20.056 ;
; CD[2]        ; DATA[2]       ; 22.712 ;        ;        ; 22.712 ;
; CD[2]        ; RAM_DATA[2]   ; 20.424 ;        ;        ; 20.424 ;
; CD[3]        ; DATA[3]       ; 23.925 ;        ;        ; 23.925 ;
; CD[3]        ; RAM_DATA[3]   ; 21.449 ;        ;        ; 21.449 ;
; CD[4]        ; DATA[4]       ; 20.506 ; 20.506 ; 20.506 ; 20.506 ;
; CD[4]        ; RAM_DATA[4]   ; 21.062 ; 21.062 ; 21.062 ; 21.062 ;
; CD[5]        ; DATA[5]       ; 22.302 ; 22.302 ; 22.302 ; 22.302 ;
; CD[5]        ; RAM_DATA[5]   ; 18.940 ; 18.940 ; 18.940 ; 18.940 ;
; CD[6]        ; DATA[6]       ; 22.900 ; 22.900 ; 22.900 ; 22.900 ;
; CD[6]        ; RAM_DATA[6]   ; 22.424 ; 22.424 ; 22.424 ; 22.424 ;
; CD[7]        ; DATA[7]       ; 24.199 ; 24.199 ; 24.199 ; 24.199 ;
; CD[7]        ; RAM_DATA[7]   ; 23.134 ; 23.134 ; 23.134 ; 23.134 ;
; COM_DCD      ; DATA[1]       ;        ; 25.421 ; 25.421 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 24.619 ; 24.619 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 23.478 ; 23.478 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 22.753 ; 22.753 ;        ;
; COM_RI       ; DATA[6]       ; 25.283 ; 25.283 ; 25.283 ; 25.283 ;
; COM_RI       ; DATA[14]      ; 27.823 ; 27.823 ; 27.823 ; 27.823 ;
; COM_RI       ; RAM_DATA[6]   ; 24.807 ; 24.807 ; 24.807 ; 24.807 ;
; COM_RI       ; RAM_DATA[14]  ; 25.247 ; 25.247 ; 25.247 ; 25.247 ;
; CONFIG[1]    ; DATA[15]      ; 25.288 ; 25.288 ; 25.288 ; 25.288 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 22.264 ; 22.264 ; 22.264 ; 22.264 ;
; CONFIG[2]    ; DATA[14]      ; 24.440 ; 24.440 ; 24.440 ; 24.440 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 21.864 ; 21.864 ; 21.864 ; 21.864 ;
; CONFIG[5]    ; ACSI_RDn      ; 21.158 ; 21.158 ; 21.158 ; 21.158 ;
; CONFIG[5]    ; ACSI_WRn      ; 21.148 ; 21.148 ; 21.148 ; 21.148 ;
; CONFIG[5]    ; ASn           ; 24.338 ; 24.338 ; 24.338 ; 24.338 ;
; CONFIG[5]    ; BUTTONn       ; 19.717 ; 20.039 ; 20.039 ; 19.717 ;
; CONFIG[5]    ; CA1_OUT       ; 19.022 ; 19.344 ; 19.344 ; 19.022 ;
; CONFIG[5]    ; CD[0]         ; 21.746 ; 21.746 ; 21.746 ; 21.746 ;
; CONFIG[5]    ; CD[1]         ; 21.736 ; 21.736 ; 21.736 ; 21.736 ;
; CONFIG[5]    ; CD[2]         ; 21.367 ; 21.367 ; 21.367 ; 21.367 ;
; CONFIG[5]    ; CD[3]         ; 21.736 ; 21.736 ; 21.736 ; 21.736 ;
; CONFIG[5]    ; CD[4]         ; 21.376 ; 21.376 ; 21.376 ; 21.376 ;
; CONFIG[5]    ; CD[5]         ; 21.376 ; 21.376 ; 21.376 ; 21.376 ;
; CONFIG[5]    ; CD[6]         ; 21.340 ; 21.340 ; 21.340 ; 21.340 ;
; CONFIG[5]    ; CD[7]         ; 21.340 ; 21.340 ; 21.340 ; 21.340 ;
; CONFIG[5]    ; DATA[0]       ; 25.261 ; 25.261 ; 25.261 ; 25.261 ;
; CONFIG[5]    ; DATA[1]       ; 25.261 ; 25.261 ; 25.261 ; 25.261 ;
; CONFIG[5]    ; DATA[2]       ; 24.963 ; 24.963 ; 24.963 ; 24.963 ;
; CONFIG[5]    ; DATA[3]       ; 25.108 ; 25.108 ; 25.108 ; 25.108 ;
; CONFIG[5]    ; DATA[4]       ; 24.935 ; 24.935 ; 24.935 ; 24.935 ;
; CONFIG[5]    ; DATA[5]       ; 25.077 ; 25.077 ; 25.077 ; 25.077 ;
; CONFIG[5]    ; DATA[6]       ; 24.514 ; 24.514 ; 24.514 ; 24.514 ;
; CONFIG[5]    ; DATA[7]       ; 24.826 ; 24.826 ; 24.826 ; 24.826 ;
; CONFIG[5]    ; DATA[8]       ; 24.630 ; 24.630 ; 24.630 ; 24.630 ;
; CONFIG[5]    ; DATA[9]       ; 24.858 ; 24.858 ; 24.858 ; 24.858 ;
; CONFIG[5]    ; DATA[10]      ; 24.888 ; 24.888 ; 24.888 ; 24.888 ;
; CONFIG[5]    ; DATA[11]      ; 24.888 ; 24.888 ; 24.888 ; 24.888 ;
; CONFIG[5]    ; DATA[12]      ; 24.894 ; 24.894 ; 24.894 ; 24.894 ;
; CONFIG[5]    ; DATA[13]      ; 24.894 ; 24.894 ; 24.894 ; 24.894 ;
; CONFIG[5]    ; DATA[14]      ; 24.856 ; 24.856 ; 24.856 ; 24.856 ;
; CONFIG[5]    ; DATA[15]      ; 25.217 ; 25.217 ; 25.217 ; 25.217 ;
; CONFIG[5]    ; DTACKn        ; 20.020 ; 20.020 ; 20.020 ; 20.020 ;
; CONFIG[5]    ; FC[0]         ; 25.217 ; 25.217 ; 25.217 ; 25.217 ;
; CONFIG[5]    ; FC[1]         ; 24.677 ; 24.677 ; 24.677 ; 24.677 ;
; CONFIG[5]    ; FC[2]         ; 24.677 ; 24.677 ; 24.677 ; 24.677 ;
; CONFIG[5]    ; FLASH_CEn     ; 20.645 ; 20.645 ; 20.645 ; 20.645 ;
; CONFIG[5]    ; FLASH_OEn     ; 21.864 ; 21.864 ; 21.864 ; 21.864 ;
; CONFIG[5]    ; IDE_CS0n      ; 19.805 ; 19.805 ; 19.805 ; 19.805 ;
; CONFIG[5]    ; IDE_CS1n      ; 18.878 ; 18.878 ; 18.878 ; 18.878 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 19.172 ; 19.172 ; 19.172 ; 19.172 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 19.003 ; 19.003 ; 19.003 ; 19.003 ;
; CONFIG[5]    ; IDE_IORDn     ; 18.052 ; 18.052 ; 18.052 ; 18.052 ;
; CONFIG[5]    ; IDE_IOWRn     ; 21.189 ; 21.189 ; 21.189 ; 21.189 ;
; CONFIG[5]    ; JOY_RHn       ; 19.524 ; 19.846 ; 19.846 ; 19.524 ;
; CONFIG[5]    ; JOY_RLn       ; 21.544 ; 21.866 ; 21.866 ; 21.544 ;
; CONFIG[5]    ; JOY_WEn       ; 21.836 ; 21.514 ; 21.514 ; 21.836 ;
; CONFIG[5]    ; JOY_WL        ; 19.090 ; 18.768 ; 18.768 ; 19.090 ;
; CONFIG[5]    ; LDSn          ; 25.641 ; 25.641 ; 25.641 ; 25.641 ;
; CONFIG[5]    ; RAM_BA[1]     ; 17.697 ; 18.511 ; 18.511 ; 17.697 ;
; CONFIG[5]    ; RAM_CAS0n     ; 17.337 ; 17.337 ; 17.337 ; 17.337 ;
; CONFIG[5]    ; RAM_CAS1n     ; 16.521 ; 16.521 ; 16.521 ; 16.521 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 21.830 ; 21.830 ; 21.830 ; 21.830 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 24.714 ; 24.714 ; 24.714 ; 24.714 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 22.675 ; 22.675 ; 22.675 ; 22.675 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 22.632 ; 22.632 ; 22.632 ; 22.632 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 25.491 ; 25.491 ; 25.491 ; 25.491 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 23.881 ; 23.881 ; 23.881 ; 23.881 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 24.038 ; 24.038 ; 24.038 ; 24.038 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 23.873 ; 23.873 ; 23.873 ; 23.873 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 23.269 ; 23.269 ; 23.269 ; 23.269 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 23.618 ; 23.618 ; 23.618 ; 23.618 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 24.741 ; 24.741 ; 24.741 ; 24.741 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 23.692 ; 23.692 ; 23.692 ; 23.692 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 24.945 ; 24.945 ; 24.945 ; 24.945 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 23.812 ; 23.812 ; 23.812 ; 23.812 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 22.280 ; 22.280 ; 22.280 ; 22.280 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 22.222 ; 22.222 ; 22.222 ; 22.222 ;
; CONFIG[5]    ; RAM_RAS0n     ; 19.373 ; 19.373 ; 19.373 ; 19.373 ;
; CONFIG[5]    ; RAM_RAS1n     ; 19.096 ; 19.096 ; 19.096 ; 19.096 ;
; CONFIG[5]    ; ROM0n         ; 18.129 ; 18.196 ; 18.196 ; 18.129 ;
; CONFIG[5]    ; ROM1n         ; 19.761 ; 19.828 ; 19.828 ; 19.761 ;
; CONFIG[5]    ; ROM2n         ; 18.683 ; 18.683 ; 18.683 ; 18.683 ;
; CONFIG[5]    ; ROM3n         ; 19.293 ; 19.293 ; 19.293 ; 19.293 ;
; CONFIG[5]    ; ROM4n         ; 18.661 ; 18.661 ; 18.661 ; 18.661 ;
; CONFIG[5]    ; ROM5n         ; 20.011 ; 20.011 ; 20.011 ; 20.011 ;
; CONFIG[5]    ; ROM6n         ; 19.625 ; 19.625 ; 19.625 ; 19.625 ;
; CONFIG[5]    ; RWn           ; 25.933 ; 25.933 ; 25.933 ; 25.933 ;
; CONFIG[5]    ; UDSn          ; 25.641 ; 25.641 ; 25.641 ; 25.641 ;
; DATA[0]      ; DATA[0]       ; 19.516 ;        ;        ; 19.516 ;
; DATA[0]      ; RAM_DATA[0]   ; 14.905 ;        ;        ; 14.905 ;
; DATA[1]      ; DATA[1]       ; 18.891 ;        ;        ; 18.891 ;
; DATA[1]      ; RAM_DATA[1]   ; 16.948 ;        ;        ; 16.948 ;
; DATA[2]      ; DATA[2]       ; 18.229 ;        ;        ; 18.229 ;
; DATA[2]      ; RAM_DATA[2]   ; 15.941 ;        ;        ; 15.941 ;
; DATA[3]      ; DATA[3]       ; 18.311 ;        ;        ; 18.311 ;
; DATA[3]      ; RAM_DATA[3]   ; 15.835 ;        ;        ; 15.835 ;
; DATA[4]      ; DATA[4]       ; 16.750 ; 16.750 ; 16.750 ; 16.750 ;
; DATA[4]      ; RAM_DATA[4]   ; 17.306 ; 17.306 ; 17.306 ; 17.306 ;
; DATA[5]      ; DATA[5]       ; 19.688 ;        ;        ; 19.688 ;
; DATA[5]      ; RAM_DATA[5]   ; 16.326 ;        ;        ; 16.326 ;
; DATA[6]      ; DATA[6]       ; 18.035 ; 18.035 ; 18.035 ; 18.035 ;
; DATA[6]      ; RAM_DATA[6]   ; 17.559 ; 17.559 ; 17.559 ; 17.559 ;
; DATA[7]      ; DATA[7]       ; 18.442 ;        ;        ; 18.442 ;
; DATA[7]      ; RAM_DATA[7]   ; 17.377 ;        ;        ; 17.377 ;
; DATA[8]      ; DATA[8]       ; 18.968 ;        ;        ; 18.968 ;
; DATA[8]      ; RAM_DATA[8]   ; 17.607 ;        ;        ; 17.607 ;
; DATA[9]      ; DATA[9]       ; 17.689 ;        ;        ; 17.689 ;
; DATA[9]      ; RAM_DATA[9]   ; 15.823 ;        ;        ; 15.823 ;
; DATA[10]     ; DATA[10]      ; 19.439 ;        ;        ; 19.439 ;
; DATA[10]     ; RAM_DATA[10]  ; 19.168 ;        ;        ; 19.168 ;
; DATA[11]     ; DATA[11]      ; 20.768 ;        ;        ; 20.768 ;
; DATA[11]     ; RAM_DATA[11]  ; 16.556 ;        ;        ; 16.556 ;
; DATA[12]     ; DATA[12]      ; 16.306 ;        ;        ; 16.306 ;
; DATA[12]     ; RAM_DATA[12]  ; 16.125 ;        ;        ; 16.125 ;
; DATA[13]     ; DATA[13]      ; 19.957 ;        ;        ; 19.957 ;
; DATA[13]     ; RAM_DATA[13]  ; 16.647 ;        ;        ; 16.647 ;
; DATA[14]     ; DATA[14]      ; 16.839 ;        ;        ; 16.839 ;
; DATA[14]     ; RAM_DATA[14]  ; 14.263 ;        ;        ; 14.263 ;
; DATA[15]     ; DATA[15]      ; 17.411 ;        ;        ; 17.411 ;
; DATA[15]     ; RAM_DATA[15]  ; 14.387 ;        ;        ; 14.387 ;
; FC[0]        ; ACSI_RDn      ; 18.839 ; 18.839 ; 18.839 ; 18.839 ;
; FC[0]        ; ACSI_WRn      ; 18.829 ; 18.829 ; 18.829 ; 18.829 ;
; FC[0]        ; ASn           ; 20.298 ; 20.298 ; 20.298 ; 20.298 ;
; FC[0]        ; BUTTONn       ; 18.501 ; 18.501 ; 18.501 ; 18.501 ;
; FC[0]        ; CA1_OUT       ; 16.703 ; 16.703 ; 16.703 ; 16.703 ;
; FC[0]        ; CD[0]         ; 19.427 ; 19.427 ; 19.427 ; 19.427 ;
; FC[0]        ; CD[1]         ; 19.417 ; 19.417 ; 19.417 ; 19.417 ;
; FC[0]        ; CD[2]         ; 19.048 ; 19.048 ; 19.048 ; 19.048 ;
; FC[0]        ; CD[3]         ; 19.417 ; 19.417 ; 19.417 ; 19.417 ;
; FC[0]        ; CD[4]         ; 19.057 ; 19.057 ; 19.057 ; 19.057 ;
; FC[0]        ; CD[5]         ; 19.057 ; 19.057 ; 19.057 ; 19.057 ;
; FC[0]        ; CD[6]         ; 19.021 ; 19.021 ; 19.021 ; 19.021 ;
; FC[0]        ; CD[7]         ; 19.021 ; 19.021 ; 19.021 ; 19.021 ;
; FC[0]        ; DATA[0]       ; 24.055 ; 23.901 ; 23.901 ; 24.055 ;
; FC[0]        ; DATA[1]       ; 23.898 ; 22.853 ; 22.853 ; 23.898 ;
; FC[0]        ; DATA[2]       ; 23.047 ; 23.047 ; 23.047 ; 23.047 ;
; FC[0]        ; DATA[3]       ; 23.841 ; 23.841 ; 23.841 ; 23.841 ;
; FC[0]        ; DATA[4]       ; 23.485 ; 23.485 ; 23.485 ; 23.485 ;
; FC[0]        ; DATA[5]       ; 23.871 ; 23.871 ; 23.871 ; 23.871 ;
; FC[0]        ; DATA[6]       ; 22.768 ; 22.768 ; 22.768 ; 22.768 ;
; FC[0]        ; DATA[7]       ; 23.488 ; 23.488 ; 23.488 ; 23.488 ;
; FC[0]        ; DATA[8]       ; 22.709 ; 22.709 ; 22.709 ; 22.709 ;
; FC[0]        ; DATA[9]       ; 23.047 ; 23.047 ; 23.047 ; 23.047 ;
; FC[0]        ; DATA[10]      ; 23.682 ; 23.682 ; 23.682 ; 23.682 ;
; FC[0]        ; DATA[11]      ; 23.682 ; 23.682 ; 23.682 ; 23.682 ;
; FC[0]        ; DATA[12]      ; 23.688 ; 23.688 ; 23.688 ; 23.688 ;
; FC[0]        ; DATA[13]      ; 23.688 ; 23.688 ; 23.688 ; 23.688 ;
; FC[0]        ; DATA[14]      ; 23.416 ; 23.416 ; 23.416 ; 23.416 ;
; FC[0]        ; DATA[15]      ; 23.806 ; 23.806 ; 23.806 ; 23.806 ;
; FC[0]        ; DTACKn        ; 15.418 ; 15.418 ; 15.418 ; 15.418 ;
; FC[0]        ; FC[0]         ; 21.177 ; 21.177 ; 21.177 ; 21.177 ;
; FC[0]        ; FC[1]         ; 20.637 ; 20.637 ; 20.637 ; 20.637 ;
; FC[0]        ; FC[2]         ; 20.637 ; 20.637 ; 20.637 ; 20.637 ;
; FC[0]        ; FLASH_CEn     ; 21.850 ; 21.850 ; 21.850 ; 21.850 ;
; FC[0]        ; FLASH_OEn     ; 23.069 ; 23.069 ; 23.069 ; 23.069 ;
; FC[0]        ; IDE_CS0n      ; 17.391 ;        ;        ; 17.391 ;
; FC[0]        ; IDE_CS1n      ; 17.083 ;        ;        ; 17.083 ;
; FC[0]        ; IDE_D_EN_INn  ; 17.732 ;        ;        ; 17.732 ;
; FC[0]        ; IDE_D_EN_OUTn ; 17.086 ;        ;        ; 17.086 ;
; FC[0]        ; IDE_IORDn     ; 17.207 ;        ;        ; 17.207 ;
; FC[0]        ; IDE_IOWRn     ; 17.083 ;        ;        ; 17.083 ;
; FC[0]        ; JOY_RHn       ; 17.372 ; 18.354 ; 18.354 ; 17.372 ;
; FC[0]        ; JOY_RLn       ; 19.392 ; 20.383 ; 20.383 ; 19.392 ;
; FC[0]        ; JOY_WEn       ; 20.353 ; 19.362 ; 19.362 ; 20.353 ;
; FC[0]        ; JOY_WL        ; 17.397 ; 16.616 ; 16.616 ; 17.397 ;
; FC[0]        ; LDSn          ; 21.601 ; 21.601 ; 21.601 ; 21.601 ;
; FC[0]        ; RAM_DATA[0]   ; 19.738 ; 19.290 ; 19.290 ; 19.738 ;
; FC[0]        ; RAM_DATA[1]   ; 21.955 ; 20.910 ; 20.910 ; 21.955 ;
; FC[0]        ; RAM_DATA[2]   ; 20.759 ; 20.759 ; 20.759 ; 20.759 ;
; FC[0]        ; RAM_DATA[3]   ; 21.365 ; 21.365 ; 21.365 ; 21.365 ;
; FC[0]        ; RAM_DATA[4]   ; 24.041 ; 24.041 ; 24.041 ; 24.041 ;
; FC[0]        ; RAM_DATA[5]   ; 21.946 ; 21.946 ; 21.946 ; 21.946 ;
; FC[0]        ; RAM_DATA[6]   ; 22.292 ; 22.292 ; 22.292 ; 22.292 ;
; FC[0]        ; RAM_DATA[7]   ; 22.423 ; 22.423 ; 22.423 ; 22.423 ;
; FC[0]        ; RAM_DATA[8]   ; 21.348 ; 21.348 ; 21.348 ; 21.348 ;
; FC[0]        ; RAM_DATA[9]   ; 21.181 ; 21.181 ; 21.181 ; 21.181 ;
; FC[0]        ; RAM_DATA[10]  ; 23.753 ; 23.753 ; 23.753 ; 23.753 ;
; FC[0]        ; RAM_DATA[11]  ; 20.908 ; 20.908 ; 20.908 ; 20.908 ;
; FC[0]        ; RAM_DATA[12]  ; 23.839 ; 23.839 ; 23.839 ; 23.839 ;
; FC[0]        ; RAM_DATA[13]  ; 21.019 ; 21.019 ; 21.019 ; 21.019 ;
; FC[0]        ; RAM_DATA[14]  ; 20.840 ; 20.840 ; 20.840 ; 20.840 ;
; FC[0]        ; RAM_DATA[15]  ; 20.782 ; 20.782 ; 20.782 ; 20.782 ;
; FC[0]        ; ROM0n         ; 19.363 ; 19.363 ; 19.363 ; 19.363 ;
; FC[0]        ; ROM1n         ; 21.000 ; 21.000 ; 21.000 ; 21.000 ;
; FC[0]        ; ROM2n         ; 19.888 ; 19.888 ; 19.888 ; 19.888 ;
; FC[0]        ; ROM3n         ; 18.858 ; 18.858 ; 18.858 ; 18.858 ;
; FC[0]        ; ROM4n         ; 18.223 ; 18.223 ; 18.223 ; 18.223 ;
; FC[0]        ; ROM5n         ; 20.686 ; 20.686 ; 20.686 ; 20.686 ;
; FC[0]        ; ROM6n         ; 19.190 ; 19.190 ; 19.190 ; 19.190 ;
; FC[0]        ; RWn           ; 21.893 ; 21.893 ; 21.893 ; 21.893 ;
; FC[0]        ; UDSn          ; 21.601 ; 21.601 ; 21.601 ; 21.601 ;
; FC[1]        ; ACSI_RDn      ; 19.148 ; 19.148 ; 19.148 ; 19.148 ;
; FC[1]        ; ACSI_WRn      ; 19.138 ; 19.138 ; 19.138 ; 19.138 ;
; FC[1]        ; ASn           ; 20.607 ; 20.607 ; 20.607 ; 20.607 ;
; FC[1]        ; BUTTONn       ; 16.502 ; 16.502 ; 16.502 ; 16.502 ;
; FC[1]        ; CA1_OUT       ; 17.012 ; 17.012 ; 17.012 ; 17.012 ;
; FC[1]        ; CD[0]         ; 19.736 ; 19.736 ; 19.736 ; 19.736 ;
; FC[1]        ; CD[1]         ; 19.726 ; 19.726 ; 19.726 ; 19.726 ;
; FC[1]        ; CD[2]         ; 19.357 ; 19.357 ; 19.357 ; 19.357 ;
; FC[1]        ; CD[3]         ; 19.726 ; 19.726 ; 19.726 ; 19.726 ;
; FC[1]        ; CD[4]         ; 19.366 ; 19.366 ; 19.366 ; 19.366 ;
; FC[1]        ; CD[5]         ; 19.366 ; 19.366 ; 19.366 ; 19.366 ;
; FC[1]        ; CD[6]         ; 19.330 ; 19.330 ; 19.330 ; 19.330 ;
; FC[1]        ; CD[7]         ; 19.330 ; 19.330 ; 19.330 ; 19.330 ;
; FC[1]        ; DATA[0]       ; 23.567 ; 23.567 ; 23.567 ; 23.567 ;
; FC[1]        ; DATA[1]       ; 23.496 ; 23.156 ; 23.156 ; 23.496 ;
; FC[1]        ; DATA[2]       ; 23.356 ; 23.356 ; 23.356 ; 23.356 ;
; FC[1]        ; DATA[3]       ; 23.545 ; 23.545 ; 23.545 ; 23.545 ;
; FC[1]        ; DATA[4]       ; 23.019 ; 23.019 ; 23.019 ; 23.019 ;
; FC[1]        ; DATA[5]       ; 23.383 ; 23.383 ; 23.383 ; 23.383 ;
; FC[1]        ; DATA[6]       ; 22.280 ; 22.280 ; 22.280 ; 22.280 ;
; FC[1]        ; DATA[7]       ; 23.132 ; 23.132 ; 23.132 ; 23.132 ;
; FC[1]        ; DATA[8]       ; 23.018 ; 23.018 ; 23.018 ; 23.018 ;
; FC[1]        ; DATA[9]       ; 23.164 ; 23.164 ; 23.164 ; 23.164 ;
; FC[1]        ; DATA[10]      ; 23.194 ; 23.194 ; 23.194 ; 23.194 ;
; FC[1]        ; DATA[11]      ; 23.194 ; 23.194 ; 23.194 ; 23.194 ;
; FC[1]        ; DATA[12]      ; 23.200 ; 23.200 ; 23.200 ; 23.200 ;
; FC[1]        ; DATA[13]      ; 23.200 ; 23.200 ; 23.200 ; 23.200 ;
; FC[1]        ; DATA[14]      ; 22.926 ; 22.926 ; 22.926 ; 22.926 ;
; FC[1]        ; DATA[15]      ; 23.316 ; 23.316 ; 23.316 ; 23.316 ;
; FC[1]        ; DTACKn        ; 15.527 ; 15.527 ; 15.527 ; 15.527 ;
; FC[1]        ; FC[0]         ; 21.486 ; 21.486 ; 21.486 ; 21.486 ;
; FC[1]        ; FC[1]         ; 20.946 ; 20.946 ; 20.946 ; 20.946 ;
; FC[1]        ; FC[2]         ; 20.946 ; 20.946 ; 20.946 ; 20.946 ;
; FC[1]        ; FLASH_CEn     ; 19.851 ; 19.851 ; 19.851 ; 19.851 ;
; FC[1]        ; FLASH_OEn     ; 21.070 ; 21.070 ; 21.070 ; 21.070 ;
; FC[1]        ; IDE_CS0n      ; 16.901 ;        ;        ; 16.901 ;
; FC[1]        ; IDE_CS1n      ; 16.593 ;        ;        ; 16.593 ;
; FC[1]        ; IDE_D_EN_INn  ; 17.242 ;        ;        ; 17.242 ;
; FC[1]        ; IDE_D_EN_OUTn ; 16.596 ;        ;        ; 16.596 ;
; FC[1]        ; IDE_IORDn     ; 16.717 ;        ;        ; 16.717 ;
; FC[1]        ; IDE_IOWRn     ; 16.593 ;        ;        ; 16.593 ;
; FC[1]        ; JOY_RHn       ; 16.355 ; 16.355 ; 16.355 ; 16.355 ;
; FC[1]        ; JOY_RLn       ; 18.384 ; 18.384 ; 18.384 ; 18.384 ;
; FC[1]        ; JOY_WEn       ; 18.354 ; 18.354 ; 18.354 ; 18.354 ;
; FC[1]        ; JOY_WL        ; 15.398 ; 15.398 ; 15.398 ; 15.398 ;
; FC[1]        ; LDSn          ; 21.910 ; 21.910 ; 21.910 ; 21.910 ;
; FC[1]        ; RAM_DATA[0]   ; 20.041 ; 19.593 ; 19.593 ; 20.041 ;
; FC[1]        ; RAM_DATA[1]   ; 21.553 ; 21.213 ; 21.213 ; 21.553 ;
; FC[1]        ; RAM_DATA[2]   ; 21.068 ; 21.068 ; 21.068 ; 21.068 ;
; FC[1]        ; RAM_DATA[3]   ; 21.668 ; 21.668 ; 21.668 ; 21.668 ;
; FC[1]        ; RAM_DATA[4]   ; 23.575 ; 23.575 ; 23.575 ; 23.575 ;
; FC[1]        ; RAM_DATA[5]   ; 21.458 ; 21.458 ; 21.458 ; 21.458 ;
; FC[1]        ; RAM_DATA[6]   ; 21.804 ; 21.804 ; 21.804 ; 21.804 ;
; FC[1]        ; RAM_DATA[7]   ; 22.698 ; 22.698 ; 22.698 ; 22.698 ;
; FC[1]        ; RAM_DATA[8]   ; 21.657 ; 21.657 ; 21.657 ; 21.657 ;
; FC[1]        ; RAM_DATA[9]   ; 21.490 ; 21.490 ; 21.490 ; 21.490 ;
; FC[1]        ; RAM_DATA[10]  ; 23.441 ; 23.441 ; 23.441 ; 23.441 ;
; FC[1]        ; RAM_DATA[11]  ; 21.217 ; 21.217 ; 21.217 ; 21.217 ;
; FC[1]        ; RAM_DATA[12]  ; 23.857 ; 23.857 ; 23.857 ; 23.857 ;
; FC[1]        ; RAM_DATA[13]  ; 21.328 ; 21.328 ; 21.328 ; 21.328 ;
; FC[1]        ; RAM_DATA[14]  ; 20.350 ; 20.350 ; 20.350 ; 20.350 ;
; FC[1]        ; RAM_DATA[15]  ; 20.292 ; 20.292 ; 20.292 ; 20.292 ;
; FC[1]        ; ROM0n         ; 17.364 ; 17.364 ; 17.364 ; 17.364 ;
; FC[1]        ; ROM1n         ; 19.001 ; 19.001 ; 19.001 ; 19.001 ;
; FC[1]        ; ROM2n         ; 17.889 ; 17.889 ; 17.889 ; 17.889 ;
; FC[1]        ; ROM3n         ; 16.859 ; 16.859 ; 16.859 ; 16.859 ;
; FC[1]        ; ROM4n         ; 16.224 ; 16.224 ; 16.224 ; 16.224 ;
; FC[1]        ; ROM5n         ; 18.687 ; 18.687 ; 18.687 ; 18.687 ;
; FC[1]        ; ROM6n         ; 17.191 ; 17.191 ; 17.191 ; 17.191 ;
; FC[1]        ; RWn           ; 22.202 ; 22.202 ; 22.202 ; 22.202 ;
; FC[1]        ; UDSn          ; 21.910 ; 21.910 ; 21.910 ; 21.910 ;
; FC[2]        ; ACSI_RDn      ; 19.052 ; 19.052 ; 19.052 ; 19.052 ;
; FC[2]        ; ACSI_WRn      ; 19.042 ; 19.042 ; 19.042 ; 19.042 ;
; FC[2]        ; ASn           ; 20.511 ; 20.511 ; 20.511 ; 20.511 ;
; FC[2]        ; BUTTONn       ; 18.708 ;        ;        ; 18.708 ;
; FC[2]        ; CA1_OUT       ; 19.935 ; 16.916 ; 16.916 ; 19.935 ;
; FC[2]        ; CD[0]         ; 19.640 ; 19.640 ; 19.640 ; 19.640 ;
; FC[2]        ; CD[1]         ; 19.630 ; 19.630 ; 19.630 ; 19.630 ;
; FC[2]        ; CD[2]         ; 19.261 ; 19.261 ; 19.261 ; 19.261 ;
; FC[2]        ; CD[3]         ; 19.630 ; 19.630 ; 19.630 ; 19.630 ;
; FC[2]        ; CD[4]         ; 19.270 ; 19.270 ; 19.270 ; 19.270 ;
; FC[2]        ; CD[5]         ; 19.270 ; 19.270 ; 19.270 ; 19.270 ;
; FC[2]        ; CD[6]         ; 19.234 ; 19.234 ; 19.234 ; 19.234 ;
; FC[2]        ; CD[7]         ; 19.234 ; 19.234 ; 19.234 ; 19.234 ;
; FC[2]        ; DATA[0]       ; 23.509 ; 23.509 ; 23.509 ; 23.509 ;
; FC[2]        ; DATA[1]       ; 23.509 ; 23.060 ; 23.060 ; 23.509 ;
; FC[2]        ; DATA[2]       ; 23.260 ; 23.328 ; 23.328 ; 23.260 ;
; FC[2]        ; DATA[3]       ; 23.487 ; 23.487 ; 23.487 ; 23.487 ;
; FC[2]        ; DATA[4]       ; 22.961 ; 22.961 ; 22.961 ; 22.961 ;
; FC[2]        ; DATA[5]       ; 23.325 ; 23.325 ; 23.325 ; 23.325 ;
; FC[2]        ; DATA[6]       ; 22.222 ; 22.222 ; 22.222 ; 22.222 ;
; FC[2]        ; DATA[7]       ; 23.074 ; 23.074 ; 23.074 ; 23.074 ;
; FC[2]        ; DATA[8]       ; 22.985 ; 22.922 ; 22.922 ; 22.985 ;
; FC[2]        ; DATA[9]       ; 23.106 ; 23.106 ; 23.106 ; 23.106 ;
; FC[2]        ; DATA[10]      ; 23.136 ; 23.136 ; 23.136 ; 23.136 ;
; FC[2]        ; DATA[11]      ; 23.136 ; 23.136 ; 23.136 ; 23.136 ;
; FC[2]        ; DATA[12]      ; 23.142 ; 23.142 ; 23.142 ; 23.142 ;
; FC[2]        ; DATA[13]      ; 23.142 ; 23.142 ; 23.142 ; 23.142 ;
; FC[2]        ; DATA[14]      ; 22.865 ; 22.865 ; 22.865 ; 22.865 ;
; FC[2]        ; DATA[15]      ; 23.255 ; 23.255 ; 23.255 ; 23.255 ;
; FC[2]        ; DTACKn        ; 15.083 ; 15.083 ; 15.083 ; 15.083 ;
; FC[2]        ; FC[0]         ; 21.390 ; 21.390 ; 21.390 ; 21.390 ;
; FC[2]        ; FC[1]         ; 20.850 ; 20.850 ; 20.850 ; 20.850 ;
; FC[2]        ; FC[2]         ; 20.850 ; 20.850 ; 20.850 ; 20.850 ;
; FC[2]        ; FLASH_CEn     ; 21.570 ;        ;        ; 21.570 ;
; FC[2]        ; FLASH_OEn     ; 22.789 ;        ;        ; 22.789 ;
; FC[2]        ; IDE_CS0n      ; 16.840 ;        ;        ; 16.840 ;
; FC[2]        ; IDE_CS1n      ; 16.532 ;        ;        ; 16.532 ;
; FC[2]        ; IDE_D_EN_INn  ; 17.181 ;        ;        ; 17.181 ;
; FC[2]        ; IDE_D_EN_OUTn ; 16.535 ;        ;        ; 16.535 ;
; FC[2]        ; IDE_IORDn     ; 16.656 ;        ;        ; 16.656 ;
; FC[2]        ; IDE_IOWRn     ; 16.532 ;        ;        ; 16.532 ;
; FC[2]        ; JOY_RHn       ; 16.821 ; 17.926 ; 17.926 ; 16.821 ;
; FC[2]        ; JOY_RLn       ; 18.841 ; 19.955 ; 19.955 ; 18.841 ;
; FC[2]        ; JOY_WEn       ; 19.925 ; 18.811 ; 18.811 ; 19.925 ;
; FC[2]        ; JOY_WL        ; 16.969 ; 16.065 ; 16.065 ; 16.969 ;
; FC[2]        ; LDSn          ; 21.814 ; 21.814 ; 21.814 ; 21.814 ;
; FC[2]        ; RAM_DATA[0]   ; 19.945 ; 19.497 ; 19.497 ; 19.945 ;
; FC[2]        ; RAM_DATA[1]   ; 22.453 ; 21.117 ; 21.117 ; 22.453 ;
; FC[2]        ; RAM_DATA[2]   ; 20.972 ; 21.040 ; 21.040 ; 20.972 ;
; FC[2]        ; RAM_DATA[3]   ; 21.572 ; 21.572 ; 21.572 ; 21.572 ;
; FC[2]        ; RAM_DATA[4]   ; 23.517 ; 23.517 ; 23.517 ; 23.517 ;
; FC[2]        ; RAM_DATA[5]   ; 21.400 ; 21.400 ; 21.400 ; 21.400 ;
; FC[2]        ; RAM_DATA[6]   ; 21.746 ; 21.746 ; 21.746 ; 21.746 ;
; FC[2]        ; RAM_DATA[7]   ; 22.636 ; 22.636 ; 22.636 ; 22.636 ;
; FC[2]        ; RAM_DATA[8]   ; 21.624 ; 21.561 ; 21.561 ; 21.624 ;
; FC[2]        ; RAM_DATA[9]   ; 21.394 ; 21.681 ; 21.681 ; 21.394 ;
; FC[2]        ; RAM_DATA[10]  ; 24.023 ; 23.966 ; 23.966 ; 24.023 ;
; FC[2]        ; RAM_DATA[11]  ; 21.940 ; 21.121 ; 21.121 ; 21.940 ;
; FC[2]        ; RAM_DATA[12]  ; 23.796 ; 23.796 ; 23.796 ; 23.796 ;
; FC[2]        ; RAM_DATA[13]  ; 22.166 ; 21.232 ; 21.232 ; 22.166 ;
; FC[2]        ; RAM_DATA[14]  ; 20.289 ; 20.289 ; 20.289 ; 20.289 ;
; FC[2]        ; RAM_DATA[15]  ; 20.231 ; 20.231 ; 20.231 ; 20.231 ;
; FC[2]        ; ROM0n         ; 19.374 ;        ;        ; 19.374 ;
; FC[2]        ; ROM1n         ; 21.011 ;        ;        ; 21.011 ;
; FC[2]        ; ROM2n         ; 19.608 ;        ;        ; 19.608 ;
; FC[2]        ; ROM3n         ; 18.578 ;        ;        ; 18.578 ;
; FC[2]        ; ROM4n         ; 17.943 ;        ;        ; 17.943 ;
; FC[2]        ; ROM5n         ; 20.697 ;        ;        ; 20.697 ;
; FC[2]        ; ROM6n         ; 18.910 ;        ;        ; 18.910 ;
; FC[2]        ; RWn           ; 22.106 ; 22.106 ; 22.106 ; 22.106 ;
; FC[2]        ; UDSn          ; 21.814 ; 21.814 ; 21.814 ; 21.814 ;
; HDINTn       ; DATA[5]       ; 26.726 ; 26.726 ; 26.726 ; 26.726 ;
; HDINTn       ; DATA[13]      ; 27.379 ;        ;        ; 27.379 ;
; HDINTn       ; RAM_DATA[5]   ; 23.364 ; 23.364 ; 23.364 ; 23.364 ;
; HDINTn       ; RAM_DATA[13]  ; 24.069 ;        ;        ; 24.069 ;
; IDE_INTRQ    ; DATA[5]       ; 26.932 ; 26.932 ; 26.932 ; 26.932 ;
; IDE_INTRQ    ; DATA[13]      ;        ; 27.585 ; 27.585 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ; 23.570 ; 23.570 ; 23.570 ; 23.570 ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 24.275 ; 24.275 ;        ;
; LDSn         ; ACSI_RDn      ; 16.172 ; 16.172 ; 16.172 ; 16.172 ;
; LDSn         ; ACSI_WRn      ; 16.162 ; 16.162 ; 16.162 ; 16.162 ;
; LDSn         ; ASn           ; 20.671 ; 20.671 ; 20.671 ; 20.671 ;
; LDSn         ; BUTTONn       ; 17.903 ;        ;        ; 17.903 ;
; LDSn         ; CA1_OUT       ; 14.036 ;        ;        ; 14.036 ;
; LDSn         ; CD[0]         ; 16.760 ; 16.760 ; 16.760 ; 16.760 ;
; LDSn         ; CD[1]         ; 16.750 ; 16.750 ; 16.750 ; 16.750 ;
; LDSn         ; CD[2]         ; 16.381 ; 16.381 ; 16.381 ; 16.381 ;
; LDSn         ; CD[3]         ; 16.750 ; 16.750 ; 16.750 ; 16.750 ;
; LDSn         ; CD[4]         ; 16.390 ; 16.390 ; 16.390 ; 16.390 ;
; LDSn         ; CD[5]         ; 16.390 ; 16.390 ; 16.390 ; 16.390 ;
; LDSn         ; CD[6]         ; 16.354 ; 16.354 ; 16.354 ; 16.354 ;
; LDSn         ; CD[7]         ; 16.354 ; 16.354 ; 16.354 ; 16.354 ;
; LDSn         ; DATA[0]       ; 23.160 ; 22.712 ; 22.712 ; 23.160 ;
; LDSn         ; DATA[1]       ; 23.093 ; 21.664 ; 21.664 ; 23.093 ;
; LDSn         ; DATA[2]       ; 21.932 ; 21.932 ; 21.932 ; 21.932 ;
; LDSn         ; DATA[3]       ; 22.652 ; 22.652 ; 22.652 ; 22.652 ;
; LDSn         ; DATA[4]       ; 22.527 ; 22.527 ; 22.527 ; 22.527 ;
; LDSn         ; DATA[5]       ; 23.375 ; 23.375 ; 23.375 ; 23.375 ;
; LDSn         ; DATA[6]       ; 22.329 ; 22.329 ; 22.329 ; 22.329 ;
; LDSn         ; DATA[7]       ; 22.753 ; 22.753 ; 22.753 ; 22.753 ;
; LDSn         ; DATA[8]       ; 22.292 ; 22.292 ; 22.292 ; 22.292 ;
; LDSn         ; DATA[9]       ; 23.156 ; 23.156 ; 23.156 ; 23.156 ;
; LDSn         ; DATA[10]      ; 23.162 ; 23.162 ; 23.162 ; 23.162 ;
; LDSn         ; DATA[11]      ; 23.186 ; 23.186 ; 23.186 ; 23.186 ;
; LDSn         ; DATA[12]      ; 22.541 ; 22.541 ; 22.541 ; 22.541 ;
; LDSn         ; DATA[13]      ; 23.192 ; 23.192 ; 23.192 ; 23.192 ;
; LDSn         ; DATA[14]      ; 21.134 ; 21.134 ; 21.134 ; 21.134 ;
; LDSn         ; DATA[15]      ; 21.524 ; 21.524 ; 21.524 ; 21.524 ;
; LDSn         ; DTACKn        ; 16.766 ; 16.766 ; 16.766 ; 16.766 ;
; LDSn         ; FC[0]         ; 21.550 ; 21.550 ; 21.550 ; 21.550 ;
; LDSn         ; FC[1]         ; 21.010 ; 21.010 ; 21.010 ; 21.010 ;
; LDSn         ; FC[2]         ; 21.010 ; 21.010 ; 21.010 ; 21.010 ;
; LDSn         ; IDE_IORDn     ; 15.219 ;        ;        ; 15.219 ;
; LDSn         ; IDE_IOWRn     ; 15.145 ;        ;        ; 15.145 ;
; LDSn         ; JOY_RLn       ; 17.022 ;        ;        ; 17.022 ;
; LDSn         ; JOY_WEn       ;        ; 16.992 ; 16.992 ;        ;
; LDSn         ; JOY_WL        ;        ; 14.045 ; 14.045 ;        ;
; LDSn         ; LDSn          ; 21.974 ; 21.974 ; 21.974 ; 21.974 ;
; LDSn         ; RAM_CAS0n     ; 21.179 ;        ;        ; 21.179 ;
; LDSn         ; RAM_CAS1n     ; 20.361 ;        ;        ; 20.361 ;
; LDSn         ; RAM_DATA[0]   ; 18.549 ; 18.101 ; 18.101 ; 18.549 ;
; LDSn         ; RAM_DATA[1]   ; 21.150 ; 19.721 ; 19.721 ; 21.150 ;
; LDSn         ; RAM_DATA[2]   ; 19.644 ; 19.644 ; 19.644 ; 19.644 ;
; LDSn         ; RAM_DATA[3]   ; 20.176 ; 20.176 ; 20.176 ; 20.176 ;
; LDSn         ; RAM_DATA[4]   ; 23.083 ; 23.083 ; 23.083 ; 23.083 ;
; LDSn         ; RAM_DATA[5]   ; 21.553 ; 21.553 ; 21.553 ; 21.553 ;
; LDSn         ; RAM_DATA[6]   ; 21.853 ; 21.853 ; 21.853 ; 21.853 ;
; LDSn         ; RAM_DATA[7]   ; 21.688 ; 21.688 ; 21.688 ; 21.688 ;
; LDSn         ; RAM_DATA[8]   ; 20.931 ; 20.931 ; 20.931 ; 20.931 ;
; LDSn         ; RAM_DATA[9]   ; 21.418 ; 21.418 ; 21.418 ; 21.418 ;
; LDSn         ; RAM_DATA[10]  ; 22.891 ; 22.891 ; 22.891 ; 22.891 ;
; LDSn         ; RAM_DATA[11]  ; 21.036 ; 21.036 ; 21.036 ; 21.036 ;
; LDSn         ; RAM_DATA[12]  ; 22.360 ; 22.360 ; 22.360 ; 22.360 ;
; LDSn         ; RAM_DATA[13]  ; 21.388 ; 21.388 ; 21.388 ; 21.388 ;
; LDSn         ; RAM_DATA[14]  ; 18.558 ; 18.558 ; 18.558 ; 18.558 ;
; LDSn         ; RAM_DATA[15]  ; 18.500 ; 18.500 ; 18.500 ; 18.500 ;
; LDSn         ; RAM_DQM0H     ; 19.981 ; 19.807 ; 19.807 ; 19.981 ;
; LDSn         ; RAM_DQM0L     ; 18.556 ; 24.031 ; 24.031 ; 18.556 ;
; LDSn         ; RAM_DQM1H     ; 20.174 ; 20.000 ; 20.000 ; 20.174 ;
; LDSn         ; RAM_DQM1L     ; 18.546 ; 24.021 ; 24.021 ; 18.546 ;
; LDSn         ; RWn           ; 22.266 ; 22.266 ; 22.266 ; 22.266 ;
; LDSn         ; UDSn          ; 21.974 ; 21.974 ; 21.974 ; 21.974 ;
; LPT_BSY      ; DATA[0]       ; 23.759 ;        ;        ; 23.759 ;
; LPT_BSY      ; DATA[8]       ; 21.983 ;        ;        ; 21.983 ;
; LPT_BSY      ; RAM_DATA[0]   ; 19.148 ;        ;        ; 19.148 ;
; LPT_BSY      ; RAM_DATA[8]   ; 20.622 ;        ;        ; 20.622 ;
; LPT_D[0]     ; DATA[0]       ; 22.797 ;        ;        ; 22.797 ;
; LPT_D[0]     ; DATA[8]       ; 21.021 ;        ;        ; 21.021 ;
; LPT_D[0]     ; RAM_DATA[0]   ; 18.186 ;        ;        ; 18.186 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 19.660 ;        ;        ; 19.660 ;
; LPT_D[1]     ; DATA[1]       ; 22.129 ;        ;        ; 22.129 ;
; LPT_D[1]     ; DATA[9]       ; 21.663 ;        ;        ; 21.663 ;
; LPT_D[1]     ; RAM_DATA[1]   ; 20.186 ;        ;        ; 20.186 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 19.797 ;        ;        ; 19.797 ;
; LPT_D[2]     ; DATA[2]       ; 21.883 ;        ;        ; 21.883 ;
; LPT_D[2]     ; DATA[10]      ; 21.296 ;        ;        ; 21.296 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 19.595 ;        ;        ; 19.595 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 21.025 ;        ;        ; 21.025 ;
; LPT_D[3]     ; DATA[3]       ; 23.208 ;        ;        ; 23.208 ;
; LPT_D[3]     ; DATA[11]      ; 24.511 ;        ;        ; 24.511 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 20.732 ;        ;        ; 20.732 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 20.299 ;        ;        ; 20.299 ;
; LPT_D[4]     ; DATA[4]       ; 25.353 ; 25.353 ; 25.353 ; 25.353 ;
; LPT_D[4]     ; DATA[12]      ; 24.867 ;        ;        ; 24.867 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 25.909 ; 25.909 ; 25.909 ; 25.909 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 24.686 ;        ;        ; 24.686 ;
; LPT_D[5]     ; DATA[5]       ; 25.140 ; 25.140 ; 25.140 ; 25.140 ;
; LPT_D[5]     ; DATA[13]      ; 23.875 ;        ;        ; 23.875 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 21.778 ; 21.778 ; 21.778 ; 21.778 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 20.565 ;        ;        ; 20.565 ;
; LPT_D[6]     ; DATA[6]       ; 25.178 ; 25.178 ; 25.178 ; 25.178 ;
; LPT_D[6]     ; DATA[14]      ; 24.375 ; 24.375 ; 24.375 ; 24.375 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 24.702 ; 24.702 ; 24.702 ; 24.702 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 21.799 ; 21.799 ; 21.799 ; 21.799 ;
; LPT_D[7]     ; DATA[7]       ; 23.518 ; 23.518 ; 23.518 ; 23.518 ;
; LPT_D[7]     ; DATA[15]      ; 24.533 ; 24.533 ; 24.533 ; 24.533 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 22.453 ; 22.453 ; 22.453 ; 22.453 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 21.509 ; 21.509 ; 21.509 ; 21.509 ;
; MIDI_IN      ; MIDI_TLR      ; 8.877  ;        ;        ; 8.877  ;
; RAM_DATA[0]  ; DATA[0]       ; 26.543 ;        ;        ; 26.543 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 21.932 ;        ;        ; 21.932 ;
; RAM_DATA[1]  ; DATA[1]       ; 24.806 ;        ;        ; 24.806 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 22.863 ;        ;        ; 22.863 ;
; RAM_DATA[2]  ; DATA[2]       ; 23.683 ;        ;        ; 23.683 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 21.395 ;        ;        ; 21.395 ;
; RAM_DATA[3]  ; DATA[3]       ; 24.444 ;        ;        ; 24.444 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 21.968 ;        ;        ; 21.968 ;
; RAM_DATA[4]  ; DATA[4]       ; 21.575 ; 21.575 ; 21.575 ; 21.575 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 22.131 ; 22.131 ; 22.131 ; 22.131 ;
; RAM_DATA[5]  ; DATA[5]       ; 25.171 ; 25.171 ; 25.171 ; 25.171 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 21.809 ; 21.809 ; 21.809 ; 21.809 ;
; RAM_DATA[6]  ; DATA[6]       ; 26.023 ; 26.023 ; 26.023 ; 26.023 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 25.547 ; 25.547 ; 25.547 ; 25.547 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.325 ; 22.325 ; 22.325 ; 22.325 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 21.260 ; 21.260 ; 21.260 ; 21.260 ;
; RAM_DATA[8]  ; DATA[8]       ; 23.154 ;        ;        ; 23.154 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 21.793 ;        ;        ; 21.793 ;
; RAM_DATA[9]  ; DATA[9]       ; 23.861 ;        ;        ; 23.861 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 21.995 ;        ;        ; 21.995 ;
; RAM_DATA[10] ; DATA[10]      ; 23.206 ;        ;        ; 23.206 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 22.935 ;        ;        ; 22.935 ;
; RAM_DATA[11] ; DATA[11]      ; 26.329 ;        ;        ; 26.329 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 22.117 ;        ;        ; 22.117 ;
; RAM_DATA[12] ; DATA[12]      ; 25.925 ;        ;        ; 25.925 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 25.744 ;        ;        ; 25.744 ;
; RAM_DATA[13] ; DATA[13]      ; 25.900 ;        ;        ; 25.900 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 22.590 ;        ;        ; 22.590 ;
; RAM_DATA[14] ; DATA[14]      ; 25.651 ; 25.651 ; 25.651 ; 25.651 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 23.075 ; 23.075 ; 23.075 ; 23.075 ;
; RAM_DATA[15] ; DATA[15]      ; 26.410 ; 26.410 ; 26.410 ; 26.410 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 23.386 ; 23.386 ; 23.386 ; 23.386 ;
; RWn          ; ACSI_RDn      ; 17.106 ; 16.229 ; 16.229 ; 17.106 ;
; RWn          ; ACSI_WRn      ; 16.219 ; 17.096 ; 17.096 ; 16.219 ;
; RWn          ; ASn           ; 20.465 ; 20.465 ; 20.465 ; 20.465 ;
; RWn          ; BUTTONn       ;        ; 21.271 ; 21.271 ;        ;
; RWn          ; CA1_OUT       ;        ; 14.970 ; 14.970 ;        ;
; RWn          ; CD[0]         ; 16.173 ; 16.173 ; 16.173 ; 16.173 ;
; RWn          ; CD[1]         ; 15.744 ; 15.744 ; 15.744 ; 15.744 ;
; RWn          ; CD[2]         ; 15.794 ; 15.794 ; 15.794 ; 15.794 ;
; RWn          ; CD[3]         ; 16.163 ; 16.163 ; 16.163 ; 16.163 ;
; RWn          ; CD[4]         ; 15.803 ; 15.803 ; 15.803 ; 15.803 ;
; RWn          ; CD[5]         ; 15.803 ; 15.803 ; 15.803 ; 15.803 ;
; RWn          ; CD[6]         ; 15.767 ; 15.767 ; 15.767 ; 15.767 ;
; RWn          ; CD[7]         ; 15.767 ; 15.767 ; 15.767 ; 15.767 ;
; RWn          ; DATA[0]       ; 23.166 ; 23.727 ; 23.727 ; 23.166 ;
; RWn          ; DATA[1]       ; 22.244 ; 21.380 ; 21.380 ; 22.244 ;
; RWn          ; DATA[2]       ; 22.752 ; 22.302 ; 22.302 ; 22.752 ;
; RWn          ; DATA[3]       ; 23.519 ; 23.261 ; 23.261 ; 23.519 ;
; RWn          ; DATA[4]       ; 21.875 ; 21.875 ; 21.875 ; 21.875 ;
; RWn          ; DATA[5]       ; 23.849 ; 23.849 ; 23.849 ; 23.849 ;
; RWn          ; DATA[6]       ; 21.494 ; 21.494 ; 21.494 ; 21.494 ;
; RWn          ; DATA[7]       ; 23.075 ; 23.075 ; 23.075 ; 23.075 ;
; RWn          ; DATA[8]       ; 22.660 ; 22.314 ; 22.314 ; 22.660 ;
; RWn          ; DATA[9]       ; 23.380 ; 22.860 ; 22.860 ; 23.380 ;
; RWn          ; DATA[10]      ; 23.779 ; 22.935 ; 22.935 ; 23.779 ;
; RWn          ; DATA[11]      ; 24.953 ; 24.103 ; 24.103 ; 24.953 ;
; RWn          ; DATA[12]      ; 23.444 ; 23.444 ; 23.444 ; 23.444 ;
; RWn          ; DATA[13]      ; 25.101 ; 24.502 ; 24.502 ; 25.101 ;
; RWn          ; DATA[14]      ; 22.172 ; 22.172 ; 22.172 ; 22.172 ;
; RWn          ; DATA[15]      ; 22.270 ; 22.270 ; 22.270 ; 22.270 ;
; RWn          ; DTACKn        ; 16.201 ; 16.201 ; 16.201 ; 16.201 ;
; RWn          ; FC[0]         ; 21.344 ; 21.344 ; 21.344 ; 21.344 ;
; RWn          ; FC[1]         ; 20.804 ; 20.804 ; 20.804 ; 20.804 ;
; RWn          ; FC[2]         ; 20.804 ; 20.804 ; 20.804 ; 20.804 ;
; RWn          ; FLASH_CEn     ;        ; 24.017 ; 24.017 ;        ;
; RWn          ; FLASH_OEn     ;        ; 25.236 ; 25.236 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 19.342 ; 19.342 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 18.808 ;        ;        ; 18.808 ;
; RWn          ; IDE_IORDn     ;        ; 18.992 ; 18.992 ;        ;
; RWn          ; IDE_IOWRn     ; 19.035 ;        ;        ; 19.035 ;
; RWn          ; JOY_RHn       ; 20.869 ; 18.548 ; 18.548 ; 20.869 ;
; RWn          ; JOY_RLn       ; 22.898 ; 20.570 ; 20.570 ; 22.898 ;
; RWn          ; JOY_WEn       ; 20.540 ; 22.868 ; 22.868 ; 20.540 ;
; RWn          ; JOY_WL        ; 19.912 ; 17.444 ; 17.444 ; 19.912 ;
; RWn          ; LDSn          ; 21.768 ; 21.768 ; 21.768 ; 21.768 ;
; RWn          ; RAM_DATA[0]   ; 17.914 ; 17.914 ; 17.914 ; 17.914 ;
; RWn          ; RAM_DATA[1]   ; 18.512 ; 18.512 ; 18.512 ; 18.512 ;
; RWn          ; RAM_DATA[2]   ; 18.512 ; 18.512 ; 18.512 ; 18.512 ;
; RWn          ; RAM_DATA[3]   ; 19.417 ; 19.417 ; 19.417 ; 19.417 ;
; RWn          ; RAM_DATA[4]   ; 19.417 ; 19.417 ; 19.417 ; 19.417 ;
; RWn          ; RAM_DATA[5]   ; 20.487 ; 20.487 ; 20.487 ; 20.487 ;
; RWn          ; RAM_DATA[6]   ; 19.986 ; 19.986 ; 19.986 ; 19.986 ;
; RWn          ; RAM_DATA[7]   ; 20.526 ; 20.526 ; 20.526 ; 20.526 ;
; RWn          ; RAM_DATA[8]   ; 19.125 ; 19.125 ; 19.125 ; 19.125 ;
; RWn          ; RAM_DATA[9]   ; 19.125 ; 19.125 ; 19.125 ; 19.125 ;
; RWn          ; RAM_DATA[10]  ; 19.125 ; 19.125 ; 19.125 ; 19.125 ;
; RWn          ; RAM_DATA[11]  ; 19.115 ; 19.115 ; 19.115 ; 19.115 ;
; RWn          ; RAM_DATA[12]  ; 18.780 ; 18.780 ; 18.780 ; 18.780 ;
; RWn          ; RAM_DATA[13]  ; 18.780 ; 18.780 ; 18.780 ; 18.780 ;
; RWn          ; RAM_DATA[14]  ; 18.221 ; 18.221 ; 18.221 ; 18.221 ;
; RWn          ; RAM_DATA[15]  ; 18.221 ; 18.221 ; 18.221 ; 18.221 ;
; RWn          ; RAM_DQM0H     ;        ; 18.959 ; 18.959 ;        ;
; RWn          ; RAM_DQM0L     ;        ; 17.328 ; 17.328 ;        ;
; RWn          ; RAM_DQM1H     ;        ; 19.152 ; 19.152 ;        ;
; RWn          ; RAM_DQM1L     ;        ; 17.318 ; 17.318 ;        ;
; RWn          ; RAM_WEn       ; 20.396 ;        ;        ; 20.396 ;
; RWn          ; ROM0n         ;        ; 21.254 ; 21.254 ;        ;
; RWn          ; ROM1n         ;        ; 22.891 ; 22.891 ;        ;
; RWn          ; ROM2n         ;        ; 22.055 ; 22.055 ;        ;
; RWn          ; ROM3n         ;        ; 21.025 ; 21.025 ;        ;
; RWn          ; ROM4n         ;        ; 20.390 ; 20.390 ;        ;
; RWn          ; ROM5n         ;        ; 22.577 ; 22.577 ;        ;
; RWn          ; ROM6n         ;        ; 21.357 ; 21.357 ;        ;
; RWn          ; RWn           ; 22.060 ; 22.060 ; 22.060 ; 22.060 ;
; RWn          ; UDSn          ; 21.768 ; 21.768 ; 21.768 ; 21.768 ;
; SCSI_ACKn    ; CD[0]         ; 17.047 ; 17.047 ; 17.047 ; 17.047 ;
; SCSI_ATNn    ; CD[1]         ; 18.828 ; 18.828 ; 18.828 ; 18.828 ;
; SCSI_BSYn    ; CD[6]         ;        ; 14.677 ; 14.677 ;        ;
; SCSI_D[0]    ; CD[0]         ; 18.516 ; 18.516 ; 18.516 ; 18.516 ;
; SCSI_D[1]    ; CD[1]         ; 17.833 ; 17.833 ; 17.833 ; 17.833 ;
; SCSI_D[2]    ; CD[2]         ;        ; 16.505 ; 16.505 ;        ;
; SCSI_D[3]    ; CD[3]         ; 19.369 ; 19.369 ; 19.369 ; 19.369 ;
; SCSI_D[4]    ; CD[4]         ; 13.423 ; 13.423 ; 13.423 ; 13.423 ;
; SCSI_D[5]    ; CD[5]         ; 12.859 ; 12.859 ; 12.859 ; 12.859 ;
; SCSI_D[6]    ; CD[6]         ; 16.352 ; 16.352 ; 16.352 ; 16.352 ;
; SCSI_D[7]    ; CD[7]         ;        ; 16.836 ; 16.836 ;        ;
; SCSI_DCn     ; CD[3]         ; 17.109 ; 17.109 ; 17.109 ; 17.109 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 15.389 ; 15.389 ; 15.389 ; 15.389 ;
; SCSI_DCn     ; SCSI_D[0]     ; 17.015 ; 17.015 ; 17.015 ; 17.015 ;
; SCSI_DCn     ; SCSI_D[1]     ; 17.015 ; 17.015 ; 17.015 ; 17.015 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.219 ; 17.219 ; 17.219 ; 17.219 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.219 ; 17.219 ; 17.219 ; 17.219 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.242 ; 17.242 ; 17.242 ; 17.242 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.242 ; 17.242 ; 17.242 ; 17.242 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.252 ; 17.252 ; 17.252 ; 17.252 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.252 ; 17.252 ; 17.252 ; 17.252 ;
; SCSI_DCn     ; SCSI_DP       ; 17.025 ; 17.025 ; 17.025 ; 17.025 ;
; SCSI_DP      ; CD[0]         ; 17.420 ; 17.420 ; 17.420 ; 17.420 ;
; SCSI_IOn     ; CD[2]         ;        ; 16.223 ; 16.223 ;        ;
; SCSI_IOn     ; CD[3]         ; 20.247 ; 20.247 ; 20.247 ; 20.247 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 13.621 ; 15.786 ; 15.786 ; 13.621 ;
; SCSI_IOn     ; SCSI_D[0]     ; 15.247 ; 15.247 ; 15.247 ; 15.247 ;
; SCSI_IOn     ; SCSI_D[1]     ; 15.247 ; 15.247 ; 15.247 ; 15.247 ;
; SCSI_IOn     ; SCSI_D[2]     ; 15.451 ; 15.451 ; 15.451 ; 15.451 ;
; SCSI_IOn     ; SCSI_D[3]     ; 15.451 ; 15.451 ; 15.451 ; 15.451 ;
; SCSI_IOn     ; SCSI_D[4]     ; 15.474 ; 15.474 ; 15.474 ; 15.474 ;
; SCSI_IOn     ; SCSI_D[5]     ; 15.474 ; 15.474 ; 15.474 ; 15.474 ;
; SCSI_IOn     ; SCSI_D[6]     ; 15.484 ; 15.484 ; 15.484 ; 15.484 ;
; SCSI_IOn     ; SCSI_D[7]     ; 15.484 ; 15.484 ; 15.484 ; 15.484 ;
; SCSI_IOn     ; SCSI_DP       ; 15.257 ; 15.257 ; 15.257 ; 15.257 ;
; SCSI_IOn     ; SCSI_RDn      ; 12.208 ;        ;        ; 12.208 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 12.176 ; 12.176 ;        ;
; SCSI_MSGn    ; CD[3]         ; 19.442 ; 19.442 ; 19.442 ; 19.442 ;
; SCSI_MSGn    ; CD[4]         ;        ; 12.341 ; 12.341 ;        ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 14.981 ; 14.981 ; 14.981 ; 14.981 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 16.607 ; 16.607 ; 16.607 ; 16.607 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 16.607 ; 16.607 ; 16.607 ; 16.607 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.811 ; 16.811 ; 16.811 ; 16.811 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.811 ; 16.811 ; 16.811 ; 16.811 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.844 ; 16.844 ; 16.844 ; 16.844 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.844 ; 16.844 ; 16.844 ; 16.844 ;
; SCSI_MSGn    ; SCSI_DP       ; 16.617 ; 16.617 ; 16.617 ; 16.617 ;
; SCSI_REQn    ; CD[3]         ; 19.496 ; 19.496 ; 19.496 ; 19.496 ;
; SCSI_REQn    ; CD[5]         ;        ; 12.083 ; 12.083 ;        ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 15.035 ;        ;        ; 15.035 ;
; SCSI_REQn    ; SCSI_D[0]     ; 16.661 ; 16.661 ; 16.661 ; 16.661 ;
; SCSI_REQn    ; SCSI_D[1]     ; 16.661 ; 16.661 ; 16.661 ; 16.661 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.865 ; 16.865 ; 16.865 ; 16.865 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.865 ; 16.865 ; 16.865 ; 16.865 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.888 ; 16.888 ; 16.888 ; 16.888 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.888 ; 16.888 ; 16.888 ; 16.888 ;
; SCSI_REQn    ; SCSI_D[6]     ; 16.898 ; 16.898 ; 16.898 ; 16.898 ;
; SCSI_REQn    ; SCSI_D[7]     ; 16.898 ; 16.898 ; 16.898 ; 16.898 ;
; SCSI_REQn    ; SCSI_DP       ; 16.671 ; 16.671 ; 16.671 ; 16.671 ;
; SCSI_RSTn    ; CD[7]         ;        ; 15.894 ; 15.894 ;        ;
; SCSI_SELn    ; CD[1]         ; 17.164 ; 17.164 ; 17.164 ; 17.164 ;
; SD_AVR_ENn   ; RESETn        ;        ; 14.448 ; 14.448 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 14.563 ; 14.563 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 14.608 ; 14.608 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 12.038 ;        ;        ; 12.038 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 12.534 ;        ;        ; 12.534 ;
; SD_RESETn    ; COM_TxD       ; 17.660 ; 17.660 ; 17.660 ; 17.660 ;
; UDSn         ; ACSI_RDn      ; 19.826 ; 19.826 ; 19.826 ; 19.826 ;
; UDSn         ; ACSI_WRn      ; 19.816 ; 19.816 ; 19.816 ; 19.816 ;
; UDSn         ; ASn           ; 21.789 ; 21.789 ; 21.789 ; 21.789 ;
; UDSn         ; CA1_OUT       ; 17.690 ;        ;        ; 17.690 ;
; UDSn         ; CD[0]         ; 20.414 ; 20.414 ; 20.414 ; 20.414 ;
; UDSn         ; CD[1]         ; 20.404 ; 20.404 ; 20.404 ; 20.404 ;
; UDSn         ; CD[2]         ; 20.035 ; 20.035 ; 20.035 ; 20.035 ;
; UDSn         ; CD[3]         ; 20.404 ; 20.404 ; 20.404 ; 20.404 ;
; UDSn         ; CD[4]         ; 20.044 ; 20.044 ; 20.044 ; 20.044 ;
; UDSn         ; CD[5]         ; 20.044 ; 20.044 ; 20.044 ; 20.044 ;
; UDSn         ; CD[6]         ; 20.008 ; 20.008 ; 20.008 ; 20.008 ;
; UDSn         ; CD[7]         ; 20.008 ; 20.008 ; 20.008 ; 20.008 ;
; UDSn         ; DATA[0]       ; 25.101 ; 25.101 ; 25.101 ; 25.101 ;
; UDSn         ; DATA[1]       ; 25.101 ; 25.101 ; 25.101 ; 25.101 ;
; UDSn         ; DATA[2]       ; 25.079 ; 24.538 ; 24.538 ; 25.079 ;
; UDSn         ; DATA[3]       ; 24.938 ; 24.938 ; 24.938 ; 24.938 ;
; UDSn         ; DATA[4]       ; 23.973 ; 23.973 ; 23.973 ; 23.973 ;
; UDSn         ; DATA[5]       ; 24.917 ; 24.917 ; 24.917 ; 24.917 ;
; UDSn         ; DATA[6]       ; 23.596 ; 23.596 ; 23.596 ; 23.596 ;
; UDSn         ; DATA[7]       ; 24.020 ; 24.020 ; 24.020 ; 24.020 ;
; UDSn         ; DATA[8]       ; 22.585 ; 22.585 ; 22.585 ; 22.585 ;
; UDSn         ; DATA[9]       ; 23.347 ; 23.347 ; 23.347 ; 23.347 ;
; UDSn         ; DATA[10]      ; 23.690 ; 23.690 ; 23.690 ; 23.690 ;
; UDSn         ; DATA[11]      ; 24.728 ; 24.728 ; 24.728 ; 24.728 ;
; UDSn         ; DATA[12]      ; 23.327 ; 23.327 ; 23.327 ; 23.327 ;
; UDSn         ; DATA[13]      ; 24.734 ; 24.734 ; 24.734 ; 24.734 ;
; UDSn         ; DATA[14]      ; 22.377 ; 22.377 ; 22.377 ; 22.377 ;
; UDSn         ; DATA[15]      ; 22.767 ; 22.767 ; 22.767 ; 22.767 ;
; UDSn         ; DTACKn        ; 17.113 ; 17.113 ; 17.113 ; 17.113 ;
; UDSn         ; FC[0]         ; 22.668 ; 22.668 ; 22.668 ; 22.668 ;
; UDSn         ; FC[1]         ; 22.128 ; 22.128 ; 22.128 ; 22.128 ;
; UDSn         ; FC[2]         ; 22.128 ; 22.128 ; 22.128 ; 22.128 ;
; UDSn         ; JOY_RHn       ; 16.263 ;        ;        ; 16.263 ;
; UDSn         ; LDSn          ; 23.092 ; 23.092 ; 23.092 ; 23.092 ;
; UDSn         ; RAM_CAS0n     ; 20.534 ;        ;        ; 20.534 ;
; UDSn         ; RAM_CAS1n     ; 19.716 ;        ;        ; 19.716 ;
; UDSn         ; RAM_DATA[0]   ; 21.862 ; 21.804 ; 21.804 ; 21.862 ;
; UDSn         ; RAM_DATA[1]   ; 23.269 ; 23.606 ; 23.606 ; 23.269 ;
; UDSn         ; RAM_DATA[2]   ; 23.198 ; 22.250 ; 22.250 ; 23.198 ;
; UDSn         ; RAM_DATA[3]   ; 22.462 ; 22.462 ; 22.462 ; 22.462 ;
; UDSn         ; RAM_DATA[4]   ; 24.529 ; 24.529 ; 24.529 ; 24.529 ;
; UDSn         ; RAM_DATA[5]   ; 23.147 ; 23.147 ; 23.147 ; 23.147 ;
; UDSn         ; RAM_DATA[6]   ; 23.120 ; 23.120 ; 23.120 ; 23.120 ;
; UDSn         ; RAM_DATA[7]   ; 22.955 ; 22.955 ; 22.955 ; 22.955 ;
; UDSn         ; RAM_DATA[8]   ; 21.224 ; 21.224 ; 21.224 ; 21.224 ;
; UDSn         ; RAM_DATA[9]   ; 21.481 ; 21.481 ; 21.481 ; 21.481 ;
; UDSn         ; RAM_DATA[10]  ; 23.419 ; 23.419 ; 23.419 ; 23.419 ;
; UDSn         ; RAM_DATA[11]  ; 21.692 ; 21.692 ; 21.692 ; 21.692 ;
; UDSn         ; RAM_DATA[12]  ; 23.146 ; 23.146 ; 23.146 ; 23.146 ;
; UDSn         ; RAM_DATA[13]  ; 21.427 ; 21.427 ; 21.427 ; 21.427 ;
; UDSn         ; RAM_DATA[14]  ; 19.801 ; 19.801 ; 19.801 ; 19.801 ;
; UDSn         ; RAM_DATA[15]  ; 19.743 ; 19.743 ; 19.743 ; 19.743 ;
; UDSn         ; RAM_DQM0H     ; 18.855 ; 25.016 ; 25.016 ; 18.855 ;
; UDSn         ; RAM_DQM0L     ; 17.343 ; 17.143 ; 17.143 ; 17.343 ;
; UDSn         ; RAM_DQM1H     ; 19.048 ; 25.209 ; 25.209 ; 19.048 ;
; UDSn         ; RAM_DQM1L     ; 17.333 ; 17.133 ; 17.133 ; 17.333 ;
; UDSn         ; RWn           ; 23.384 ; 23.384 ; 23.384 ; 23.384 ;
; UDSn         ; UDSn          ; 23.092 ; 23.092 ; 23.092 ; 23.092 ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 12.621 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 12.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 12.823 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 12.823 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 12.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 12.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 12.814 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 12.804 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 13.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 13.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 12.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 12.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 12.023 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 12.013 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 13.099 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 13.089 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 12.980 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 12.817 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 12.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 12.753 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 12.753 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 12.778 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 12.793 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 12.803 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 12.778 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 36.168 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 33.392 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 33.798 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 33.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 33.419 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 33.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 33.428 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 33.428 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 33.392 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 33.392 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 13.635 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 38.833 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 39.268 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 39.268 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 39.246 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 39.246 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 39.084 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 39.084 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 38.843 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 38.833 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 38.865 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 38.865 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 38.895 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 38.895 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 38.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 38.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 39.234 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 39.224 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 6.202  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 39.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 36.507 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 37.047 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 36.507 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 36.507 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 37.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.876  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.947  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 9.947  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 10.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 10.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.450 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.450 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 12.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 12.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 12.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.148 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.813 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.813 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 10.254 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 10.254 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 37.763 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.024  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 8.600  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 11.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 11.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 11.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 11.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 11.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 11.850 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 11.850 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 11.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 11.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 11.633 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.197  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 5.048  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 37.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 7.164  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 7.751  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 7.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.960  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.950  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.036  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.026  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.917  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.754  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 7.730  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 25.193 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 22.130 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 22.536 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 22.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 22.157 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 22.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 22.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 22.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 22.130 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 22.130 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 27.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 28.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 28.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 27.984 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 27.984 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 27.822 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 27.822 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 27.581 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 27.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 27.603 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 27.603 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 27.633 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 27.633 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 27.639 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 27.639 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 27.972 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 27.962 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 28.488 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 25.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 26.072 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 25.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 25.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 26.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 26.788 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 26.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 12.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 12.823 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 12.823 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 12.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 12.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 12.814 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 12.804 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 13.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 13.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 12.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 12.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 12.023 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 12.013 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 13.099 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 13.089 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 12.980 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 12.817 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 12.003 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 12.753 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 12.753 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 12.778 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 12.793 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 12.803 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 12.778 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 36.168 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 33.392 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 33.798 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 33.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 33.419 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 33.788 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 33.428 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 33.428 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 33.392 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 33.392 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 13.635 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 38.833 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 39.268 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 39.268 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 39.246 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 39.246 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 39.084 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 39.084 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 38.843 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 38.833 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 38.865 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 38.865 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 38.895 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 38.895 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 38.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 38.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 39.234 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 39.224 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 6.202  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 39.594 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 36.507 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 37.047 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 36.507 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 36.507 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 37.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.876  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.947  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 9.947  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 10.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 10.545 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.450 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.450 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 12.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 12.019 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 12.559 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.158 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.148 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.813 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.813 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 10.254 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 10.254 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 37.763 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.024  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 8.600  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 11.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 11.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 11.623 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 11.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 11.827 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 11.850 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 11.850 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 11.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 11.860 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 11.633 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.197  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 5.048  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 37.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 7.164  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 7.751  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 7.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.960  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.950  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.036  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.026  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.917  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.754  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 7.730  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 25.193 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 22.130 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 22.536 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 22.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 22.157 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 22.526 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 22.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 22.166 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 22.130 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 22.130 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 27.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 28.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 28.006 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 27.984 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 27.984 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 27.822 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 27.822 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 27.581 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 27.571 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 27.603 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 27.603 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 27.633 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 27.633 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 27.639 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 27.639 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 27.972 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 27.962 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 28.488 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 25.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 26.072 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 25.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 25.532 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 26.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 26.788 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 26.496 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 26.384 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 23.608 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 24.014 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 24.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 23.635 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 24.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 23.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 23.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 23.608 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 23.608 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 13.062 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 29.049 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 29.484 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 29.484 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 29.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 29.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 29.300 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 29.300 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 29.059 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 29.049 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 29.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 29.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 29.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 29.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 29.117 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 29.117 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 29.450 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 29.440 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 30.014 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 26.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 27.263 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 26.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 26.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 6.226  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 27.687 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 8.756  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 8.756  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 10.259 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 10.259 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.368 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 10.828 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.368 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.967  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.967  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.967  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.957  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 9.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 9.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 9.063  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.063  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 27.979 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 27.687 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 7.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 26.384 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 23.608 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 24.014 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 24.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 23.635 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 24.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 23.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 23.644 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 23.608 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 23.608 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 13.062 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 29.049 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 29.484 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 29.484 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 29.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 29.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 29.300 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 29.300 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 29.059 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 29.049 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 29.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 29.081 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 29.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 29.111 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 29.117 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 29.117 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 29.450 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 29.440 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 30.014 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 26.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 27.263 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 26.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 26.723 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 6.226  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 27.687 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 8.756  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 8.756  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 10.259 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 10.259 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.368 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 10.828 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.368 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.967  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.967  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.967  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.957  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 9.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 9.622  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 9.063  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.063  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 27.979 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 27.687 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                             ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 12.621 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 6.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 7.760  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 7.760  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 7.742  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 7.742  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 7.751  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.071  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.071  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.960  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.950  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.036  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.026  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.917  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.754  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.690  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.690  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 7.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 7.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 7.088  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.536  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.526  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.157  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.526  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 7.726  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 12.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 13.407 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 13.407 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 13.385 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 13.385 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 13.223 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 13.223 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 12.982 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 12.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 13.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 13.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 13.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 13.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 13.040 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 13.040 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 13.373 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 13.363 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 5.490  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 11.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.845  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 9.269  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.876  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.168  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 9.168  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.766  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.766  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 10.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 10.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.240 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 10.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 10.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 10.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 10.369 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 9.475  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.475  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 9.561  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.024  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 8.600  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 7.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 7.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 7.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 8.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 8.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 8.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 8.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 7.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.197  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 5.048  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 9.269  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 6.949  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 7.751  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 7.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.960  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.950  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.036  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.026  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.917  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.754  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 7.730  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 16.333 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 13.830 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 14.236 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 14.226 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 13.857 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 14.226 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 13.866 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 13.866 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 13.830 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 13.830 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 16.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 17.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 17.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 17.251 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 17.251 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 17.089 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 17.089 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 16.848 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 16.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 16.870 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 16.870 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 16.900 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 16.900 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 16.906 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 16.906 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 17.239 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 17.229 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.734 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 16.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 17.212 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 16.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 16.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 17.636 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 17.928 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 17.636 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 7.760  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 7.760  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 7.742  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 7.742  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 7.751  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 7.741  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.071  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.071  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.960  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.950  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.036  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.026  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.917  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.754  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.940  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.690  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.690  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 7.730  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 7.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 7.088  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.536  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.526  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.157  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.526  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.130  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 7.726  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 12.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 13.407 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 13.407 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 13.385 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 13.385 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 13.223 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 13.223 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 12.982 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 12.972 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 13.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 13.004 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 13.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 13.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 13.040 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 13.040 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 13.373 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 13.363 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 5.490  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.845  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.305  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 9.269  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.876  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.599  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.594  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 6.740  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.433  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.168  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 9.168  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.766  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.766  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 10.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 10.671 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.240 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.780 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 10.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 10.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 10.379 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 10.369 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.034 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 9.475  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.475  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 9.561  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.024  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 8.600  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 7.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 7.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 7.864  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.068  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 8.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 8.091  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 8.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 8.101  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 7.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.197  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.772  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.782  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 5.048  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 9.269  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 6.949  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 7.760  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 7.742  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 7.751  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 7.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.071  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.500  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.960  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.950  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.036  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.026  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.917  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.754  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.940  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.690  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 7.730  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 7.740  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.715  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 16.333 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 13.830 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 14.236 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 14.226 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 13.857 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 14.226 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 13.866 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 13.866 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 13.830 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 13.830 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 16.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 17.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 17.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 17.251 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 17.251 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 17.089 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 17.089 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 16.848 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 16.838 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 16.870 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 16.870 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 16.900 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 16.900 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 16.906 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 16.906 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 17.239 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 17.229 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.734 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 16.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 17.212 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 16.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 16.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 17.636 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 17.928 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 17.636 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 15.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 12.697 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 13.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 13.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 12.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 13.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 12.733 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 12.733 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 12.697 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 12.697 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 10.211 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 17.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 17.998 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 17.998 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 17.976 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 17.976 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 17.814 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 17.814 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 17.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 17.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 17.595 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 17.595 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 17.625 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 17.625 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 17.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 17.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 17.964 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 17.954 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 11.013 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 15.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 16.079 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 15.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 15.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 6.226  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 16.503 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 7.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 7.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 8.457  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 8.457  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 9.362  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 9.362  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 10.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 9.931  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 10.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.070  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.070  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.070  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.060  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 8.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 8.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 16.795 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 16.503 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 7.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 15.200 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 12.697 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 13.103 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 13.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 12.724 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 13.093 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 12.733 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 12.733 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 12.697 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 12.697 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 10.211 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 17.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 17.998 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 17.998 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 17.976 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 17.976 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 17.814 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 17.814 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 17.573 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 17.563 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 17.595 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 17.595 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 17.625 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 17.625 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 17.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 17.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 17.964 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 17.954 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.013 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 15.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 16.079 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 15.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 15.539 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 6.226  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 16.503 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 7.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 7.859  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 8.457  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 8.457  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 9.362  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 9.362  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 10.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 9.931  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 10.471 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.070  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.070  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.070  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.060  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 8.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 8.725  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 8.166  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 16.795 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 16.503 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.422  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 12.621    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 12.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 12.823    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 12.823    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 12.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 12.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 12.814    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 12.804    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 13.134    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 13.134    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 12.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 12.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 12.023    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 12.013    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 13.099    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 13.089    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 12.980    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 12.817    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 12.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 12.753    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 12.753    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 12.778    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 12.793    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 12.803    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 12.778    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 36.168    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 33.392    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 33.798    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 33.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 33.419    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 33.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 33.428    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 33.428    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 33.392    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 33.392    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 13.635    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 38.833    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 39.268    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 39.268    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 39.246    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 39.246    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 39.084    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 39.084    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 38.843    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 38.833    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 38.865    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 38.865    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 38.895    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 38.895    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 38.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 38.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 39.234    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 39.224    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 6.202     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 39.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 36.507    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 37.047    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 36.507    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 36.507    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 37.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 9.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 10.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 10.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 11.450    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 11.450    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 12.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 12.019    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 12.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 11.148    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.813    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.813    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 10.254    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 10.254    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 37.763    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 8.600     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 11.623    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 11.623    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 11.623    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 11.827    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 11.827    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 11.850    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 11.850    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 11.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 11.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 11.633    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.197     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 5.048     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 37.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 7.164     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 7.751     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 7.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.960     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.950     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.036     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.026     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.917     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.754     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 7.730     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 25.193    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 22.130    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 22.536    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 22.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 22.157    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 22.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 22.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 22.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 22.130    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 22.130    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 27.571    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 28.006    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 28.006    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 27.984    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 27.984    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 27.822    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 27.822    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 27.581    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 27.571    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 27.603    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 27.603    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 27.633    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 27.633    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 27.639    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 27.639    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 27.972    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 27.962    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 28.488    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 25.532    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 26.072    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 25.532    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 25.532    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 26.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 26.788    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 26.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 12.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 12.823    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 12.823    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 12.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 12.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 12.814    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 12.804    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 13.134    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 13.134    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 12.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 12.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 12.023    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 12.013    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 13.099    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 13.089    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 12.980    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 12.817    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 12.003    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 12.753    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 12.753    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 12.778    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 12.793    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 12.803    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 12.778    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 36.168    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 33.392    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 33.798    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 33.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 33.419    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 33.788    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 33.428    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 33.428    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 33.392    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 33.392    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 13.635    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 38.833    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 39.268    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 39.268    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 39.246    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 39.246    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 39.084    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 39.084    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 38.843    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 38.833    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 38.865    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 38.865    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 38.895    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 38.895    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 38.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 38.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 39.234    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 39.224    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 6.202     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 39.594    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 36.507    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 37.047    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 36.507    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 36.507    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 37.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 9.947     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 10.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 10.545    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 11.450    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 11.450    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 12.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 12.019    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 12.559    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 11.158    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 11.148    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.813    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.813    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 10.254    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 10.254    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 37.763    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 8.600     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 11.623    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 11.623    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 11.623    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 11.827    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 11.827    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 11.850    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 11.850    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 11.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 11.860    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 11.633    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.197     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 5.048     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 37.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 7.164     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 7.751     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 7.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.960     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.950     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.036     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.026     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.917     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.754     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 7.730     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 25.193    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 22.130    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 22.536    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 22.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 22.157    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 22.526    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 22.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 22.166    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 22.130    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 22.130    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 27.571    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 28.006    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 28.006    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 27.984    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 27.984    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 27.822    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 27.822    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 27.581    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 27.571    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 27.603    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 27.603    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 27.633    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 27.633    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 27.639    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 27.639    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 27.972    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 27.962    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 28.488    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 25.532    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 26.072    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 25.532    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 25.532    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 26.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 26.788    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 26.496    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 26.384    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 23.608    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 24.014    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 24.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 23.635    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 24.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 23.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 23.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 23.608    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 23.608    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 13.062    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 29.049    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 29.484    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 29.484    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 29.462    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 29.462    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 29.300    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 29.300    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 29.059    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 29.049    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 29.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 29.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 29.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 29.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 29.117    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 29.117    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 29.450    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 29.440    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 30.014    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 26.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 27.263    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 26.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 26.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 6.226     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 27.687    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 8.756     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 8.756     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 10.259    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 10.259    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.368    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 10.828    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.368    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.967     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.967     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.967     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.957     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 9.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 9.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 9.063     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.063     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 27.979    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 27.687    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 7.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 26.384    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 23.608    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 24.014    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 24.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 23.635    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 24.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 23.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 23.644    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 23.608    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 23.608    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 13.062    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 29.049    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 29.484    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 29.484    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 29.462    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 29.462    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 29.300    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 29.300    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 29.059    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 29.049    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 29.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 29.081    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 29.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 29.111    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 29.117    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 29.117    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 29.450    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 29.440    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 30.014    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 26.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 27.263    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 26.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 26.723    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 6.226     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 27.687    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 8.756     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 8.756     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 10.259    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 10.259    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.368    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 10.828    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.368    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.967     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.967     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.967     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.957     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 9.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 9.622     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 9.063     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.063     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 27.979    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 27.687    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 12.621    ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 6.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 7.760     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 7.760     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 7.742     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 7.742     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 7.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.071     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.071     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.960     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.950     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.036     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.026     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.917     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.754     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.690     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.690     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 7.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 7.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 7.088     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.536     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.526     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.157     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.526     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 7.726     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 12.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 13.407    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 13.407    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 13.385    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 13.385    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 13.223    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 13.223    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 12.982    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 12.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 13.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 13.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 13.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 13.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 13.040    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 13.040    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 13.373    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 13.363    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 5.490     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 11.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 8.845     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 9.269     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 7.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 9.168     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 9.168     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 9.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 9.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 10.671    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 10.671    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 11.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 11.240    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 11.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 10.379    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 10.379    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 10.379    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 10.369    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 10.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 10.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 9.475     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 9.475     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 9.561     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 6.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 8.600     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 7.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 7.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 7.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 8.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 8.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 8.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 8.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 8.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 8.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 7.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 6.197     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 5.048     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 9.269     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 6.949     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 7.751     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 7.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 6.960     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 6.950     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 8.036     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 8.026     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 7.917     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 7.754     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 7.730     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 16.333    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 13.830    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 14.236    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 14.226    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 13.857    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 14.226    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 13.866    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 13.866    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 13.830    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 13.830    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 16.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 17.273    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 17.273    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 17.251    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 17.251    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 17.089    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 17.089    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 16.848    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 16.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 16.870    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 16.870    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 16.900    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 16.900    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 16.906    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 16.906    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 17.239    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 17.229    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 12.734    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 16.672    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 17.212    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 16.672    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 16.672    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 17.636    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 17.928    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 17.636    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 7.760     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 7.760     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 7.742     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 7.742     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 7.751     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 7.741     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.071     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.071     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.960     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.950     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.036     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.026     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.917     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.754     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.940     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.690     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.690     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 7.730     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 7.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 7.088     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.536     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.526     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.157     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.526     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.130     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 7.726     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 12.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 13.407    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 13.407    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 13.385    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 13.385    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 13.223    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 13.223    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 12.982    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 12.972    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 13.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 13.004    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 13.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 13.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 13.040    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 13.040    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 13.373    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 13.363    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 5.490     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 8.845     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 8.305     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 9.269     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 7.876     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 7.599     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 7.594     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 6.740     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 6.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 9.168     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 9.168     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 9.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 9.766     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 10.671    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 10.671    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 11.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 11.240    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 11.780    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 10.379    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 10.379    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 10.379    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 10.369    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 10.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 10.034    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 9.475     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 9.475     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 9.561     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 6.024     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 8.600     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 7.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 7.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 7.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 8.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 8.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 8.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 8.091     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 8.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 8.101     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 7.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 6.197     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 4.772     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 4.782     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 5.048     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 9.269     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 6.949     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 7.760     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 7.742     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 7.751     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 7.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 8.071     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 7.500     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 6.960     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 6.950     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 8.036     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 8.026     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 7.917     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 7.754     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 6.940     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 7.690     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 7.730     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 7.740     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 7.715     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 16.333    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 13.830    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 14.236    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 14.226    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 13.857    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 14.226    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 13.866    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 13.866    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 13.830    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 13.830    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 16.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 17.273    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 17.273    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 17.251    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 17.251    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 17.089    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 17.089    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 16.848    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 16.838    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 16.870    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 16.870    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 16.900    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 16.900    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 16.906    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 16.906    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 17.239    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 17.229    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 12.734    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 16.672    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 17.212    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 16.672    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 16.672    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 17.636    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 17.928    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 17.636    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 15.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 12.697    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 13.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 13.093    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 12.724    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 13.093    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 12.733    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 12.733    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 12.697    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 12.697    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 10.211    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 17.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 17.998    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 17.998    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 17.976    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 17.976    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 17.814    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 17.814    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 17.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 17.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 17.595    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 17.595    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 17.625    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 17.625    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 17.631    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 17.631    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 17.964    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 17.954    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 11.013    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 15.539    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 16.079    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 15.539    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 15.539    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 6.226     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 16.503    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 7.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 7.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 8.457     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 8.457     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 9.362     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 9.362     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 10.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 9.931     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 10.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 9.070     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 9.070     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 9.070     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 9.060     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 8.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 8.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 16.795    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 16.503    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 7.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 15.200    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 12.697    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 13.103    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 13.093    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 12.724    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 13.093    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 12.733    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 12.733    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 12.697    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 12.697    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 10.211    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 17.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 17.998    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 17.998    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 17.976    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 17.976    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 17.814    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 17.814    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 17.573    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 17.563    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 17.595    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 17.595    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 17.625    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 17.625    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 17.631    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 17.631    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 17.964    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 17.954    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.013    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 15.539    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 16.079    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 15.539    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 15.539    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 6.226     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 16.503    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 7.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 7.859     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 8.457     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 8.457     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 9.362     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 9.362     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 10.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 9.931     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 10.471    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 9.070     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 9.070     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 9.070     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 9.060     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 8.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 8.725     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 8.166     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 16.795    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 16.503    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 7.422     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------+
; Fast Model Setup Summary                                                            ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; -0.590 ; -50.514       ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -0.040 ; -0.040        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -0.040 ; -0.040        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 0.269  ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.269  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 4.302  ; 0.000         ;
; CLK_PLL1                                                   ; 61.372 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 62.012 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Hold Summary                                                             ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -1.600 ; -450.465      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -1.600 ; -450.465      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; -1.460 ; -348.941      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -1.084 ; -141.124      ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -1.084 ; -141.124      ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 0.215  ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.215  ; 0.000         ;
; CLK_PLL1                                                   ; 0.358  ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Recovery Summary                                                         ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 27.164 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 27.164 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 29.992 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 29.992 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+------------------------------------------------------------------------------------+
; Fast Model Removal Summary                                                         ;
+------------------------------------------------------------+-------+---------------+
; Clock                                                      ; Slack ; End Point TNS ;
+------------------------------------------------------------+-------+---------------+
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 0.983 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.983 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1.252 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1.252 ; 0.000         ;
+------------------------------------------------------------+-------+---------------+


+-------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width Summary                                              ;
+------------------------------------------------------------+--------+---------------+
; Clock                                                      ; Slack  ; End Point TNS ;
+------------------------------------------------------------+--------+---------------+
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 10.568 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13.498 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13.498 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 18.531 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 29.231 ; 0.000         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 29.231 ; 0.000         ;
; CLK_PLL1                                                   ; 30.250 ; 0.000         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 30.250 ; 0.000         ;
; CLK_PLL2                                                   ; 31.250 ; 0.000         ;
; CRT_PIN4_CLK1                                              ; 31.250 ; 0.000         ;
; altera_reserved_tck                                        ; 97.778 ; 0.000         ;
+------------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                        ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                  ; To Node                                                                                      ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.590 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[301] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.587      ;
; -0.590 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[301] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.587      ;
; -0.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[301]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.584      ;
; -0.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[9]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[301]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.584      ;
; -0.586 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[134] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.582      ;
; -0.586 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[236]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.583      ;
; -0.586 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[134] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.582      ;
; -0.586 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[236]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.583      ;
; -0.585 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[236] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.582      ;
; -0.585 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[135] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.581      ;
; -0.585 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[136]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.581      ;
; -0.585 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[236] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.582      ;
; -0.585 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[135] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.581      ;
; -0.585 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[136]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.581      ;
; -0.584 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[231]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.581      ;
; -0.584 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[231]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.581      ;
; -0.582 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[231] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.579      ;
; -0.582 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[140] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.580      ;
; -0.582 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]                        ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[231] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.579      ;
; -0.582 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[140] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.580      ;
; -0.577 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[238] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.574      ;
; -0.577 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[232]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.574      ;
; -0.577 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[233]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.574      ;
; -0.577 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[238] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.574      ;
; -0.577 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[232]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.574      ;
; -0.577 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[233]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.574      ;
; -0.574 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[282]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.571      ;
; -0.574 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[294]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.572      ;
; -0.574 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[282]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.571      ;
; -0.574 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[294]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.572      ;
; -0.573 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[293] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.571      ;
; -0.573 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[293] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.571      ;
; -0.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[282] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.569      ;
; -0.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[284]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.569      ;
; -0.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[293]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.570      ;
; -0.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[282] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.569      ;
; -0.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[284]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.569      ;
; -0.572 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[293]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.570      ;
; -0.571 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[284] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.568      ;
; -0.571 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[294] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.569      ;
; -0.571 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[284] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.568      ;
; -0.571 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[294] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.569      ;
; -0.569 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[5]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[297] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.566      ;
; -0.569 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[5]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[297] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.566      ;
; -0.568 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[286] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.565      ;
; -0.568 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[235]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.565      ;
; -0.568 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[298]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.565      ;
; -0.568 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[286] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.565      ;
; -0.568 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[235]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.565      ;
; -0.568 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[298]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.565      ;
; -0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[235] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.563      ;
; -0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[298] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.563      ;
; -0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[235] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.563      ;
; -0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[6]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[298] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.563      ;
; -0.565 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[299] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.562      ;
; -0.565 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[299] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.562      ;
; -0.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[288] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.983     ; 0.562      ;
; -0.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[288] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.983     ; 0.562      ;
; -0.513 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[141] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.509      ;
; -0.513 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[141] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.509      ;
; -0.507 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[142] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.503      ;
; -0.507 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[142] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.986     ; 0.503      ;
; -0.505 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[233] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.502      ;
; -0.505 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[233] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.502      ;
; -0.501 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[3]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[295] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.499      ;
; -0.501 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[3]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[295] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.499      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[232] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.495      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[136] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.496      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[281] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.495      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[296]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.496      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[232] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.495      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[136] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.496      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[281] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.495      ;
; -0.498 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[296]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.496      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[296] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.495      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[141]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.495      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[281]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.494      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[278]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.494      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[290]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.495      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[4]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[296] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.495      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[141]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.495      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[1]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[281]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.494      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[278]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.494      ;
; -0.497 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[290]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.495      ;
; -0.494 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[278] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.491      ;
; -0.494 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[278] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.491      ;
; -0.492 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[300] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.490      ;
; -0.492 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[300] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.490      ;
; -0.491 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[240] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.488      ;
; -0.491 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[290] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.489      ;
; -0.491 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[11] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[292] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.489      ;
; -0.491 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[240] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.488      ;
; -0.491 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[0]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[290] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.489      ;
; -0.491 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[11] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[292] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.489      ;
; -0.490 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[234] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.487      ;
; -0.490 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[287] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.487      ;
; -0.490 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]                         ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[234] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.487      ;
; -0.490 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDB_OFFSET[7]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[287] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.985     ; 0.487      ;
; -0.489 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[300]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.487      ;
; -0.489 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|\DISPLAY_SWITCH:HDE_OFFSET[8]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[300]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 1.950        ; -1.984     ; 0.487      ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                            ;
+--------+----------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                          ; To Node                                                                    ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -0.040 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.816     ; 6.070      ;
; 0.018  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.808     ; 6.020      ;
; 0.027  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.819     ; 6.000      ;
; 0.037  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.817     ; 5.992      ;
; 0.041  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.834     ; 5.971      ;
; 0.065  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSCROLL[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.809     ; 5.972      ;
; 0.106  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.797     ; 5.943      ;
; 0.134  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.826     ; 5.886      ;
; 0.173  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.825     ; 5.848      ;
; 0.179  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.825     ; 5.842      ;
; 0.185  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[1]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.826     ; 5.835      ;
; 0.207  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.798     ; 5.841      ;
; 0.223  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[17] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.821     ; 5.802      ;
; 0.224  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHT[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.807     ; 5.815      ;
; 0.229  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.816     ; 5.801      ;
; 0.230  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.816     ; 5.800      ;
; 0.247  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_F[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.817     ; 5.782      ;
; 0.256  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.822     ; 5.768      ;
; 0.261  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[17]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.827     ; 5.758      ;
; 0.271  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.824     ; 5.751      ;
; 0.272  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|DMA_CONTROL[1]           ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.761      ;
; 0.274  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[25]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.805     ; 5.767      ;
; 0.281  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.799     ; 5.766      ;
; 0.285  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[25]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.824     ; 5.737      ;
; 0.287  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[0][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.808     ; 5.751      ;
; 0.292  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[15][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.809     ; 5.745      ;
; 0.302  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.817     ; 5.727      ;
; 0.312  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[1]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.826     ; 5.708      ;
; 0.321  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[8][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.797     ; 5.728      ;
; 0.325  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.816     ; 5.705      ;
; 0.360  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.812     ; 5.674      ;
; 0.362  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.812     ; 5.672      ;
; 0.362  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[1][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.803     ; 5.681      ;
; 0.364  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.808     ; 5.674      ;
; 0.366  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.817     ; 5.663      ;
; 0.367  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.810     ; 5.669      ;
; 0.369  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[12][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.810     ; 5.667      ;
; 0.370  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[6][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.805     ; 5.671      ;
; 0.370  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[7][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.805     ; 5.671      ;
; 0.372  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[9]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.830     ; 5.644      ;
; 0.379  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.834     ; 5.633      ;
; 0.379  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.847     ; 5.620      ;
; 0.390  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[2][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.801     ; 5.655      ;
; 0.391  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.830     ; 5.625      ;
; 0.393  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[4][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.801     ; 5.652      ;
; 0.393  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.851     ; 5.602      ;
; 0.397  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[25]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.822     ; 5.627      ;
; 0.405  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.834     ; 5.607      ;
; 0.410  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.623      ;
; 0.411  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[9][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.790     ; 5.645      ;
; 0.411  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.622      ;
; 0.416  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[241]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.814     ; 5.616      ;
; 0.421  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_MICROWIRE:I_MICROWIRE|GPx_EN_REG[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.819     ; 5.606      ;
; 0.421  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.804     ; 5.621      ;
; 0.424  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.609      ;
; 0.428  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[17]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.818     ; 5.600      ;
; 0.433  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.834     ; 5.579      ;
; 0.435  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.833     ; 5.578      ;
; 0.437  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|INTERLACED_EN  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.596      ;
; 0.438  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|FREQ_DIV_INT[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.816     ; 5.592      ;
; 0.439  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[11][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.795     ; 5.612      ;
; 0.444  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[10][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.795     ; 5.607      ;
; 0.452  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_ST[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.798     ; 5.596      ;
; 0.456  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.833     ; 5.557      ;
; 0.457  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.822     ; 5.567      ;
; 0.458  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.797     ; 5.591      ;
; 0.458  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSCROLL[2]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.809     ; 5.579      ;
; 0.459  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.823     ; 5.564      ;
; 0.460  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.842     ; 5.544      ;
; 0.462  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[16]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.827     ; 5.557      ;
; 0.462  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.803     ; 5.581      ;
; 0.465  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|SMODE_CTRL[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.798     ; 5.583      ;
; 0.471  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[8]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.818     ; 5.557      ;
; 0.472  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[24]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.825     ; 5.549      ;
; 0.472  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[16]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.818     ; 5.556      ;
; 0.472  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.825     ; 5.549      ;
; 0.473  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[2]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.834     ; 5.539      ;
; 0.476  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[3][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.806     ; 5.564      ;
; 0.477  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[5][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.808     ; 5.561      ;
; 0.479  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[17]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.822     ; 5.545      ;
; 0.479  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[204]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.814     ; 5.553      ;
; 0.482  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[240]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.814     ; 5.550      ;
; 0.485  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[0]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.548      ;
; 0.486  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|BUFF_INT[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.803     ; 5.557      ;
; 0.486  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.797     ; 5.563      ;
; 0.487  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[9]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.803     ; 5.556      ;
; 0.488  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.545      ;
; 0.491  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_MICROWIRE:I_MICROWIRE|GPx_EN_REG[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.819     ; 5.536      ;
; 0.493  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.825     ; 5.528      ;
; 0.495  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.830     ; 5.521      ;
; 0.495  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.825     ; 5.526      ;
; 0.496  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.816     ; 5.534      ;
; 0.500  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_DEST[0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.815     ; 5.531      ;
; 0.501  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.829     ; 5.516      ;
; 0.502  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.836     ; 5.508      ;
; 0.507  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.813     ; 5.526      ;
; 0.509  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[4]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.836     ; 5.501      ;
; 0.510  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.851     ; 5.485      ;
; 0.512  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.834     ; 5.500      ;
; 0.516  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 7.814        ; -1.851     ; 5.479      ;
+--------+----------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                            ;
+--------+----------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                          ; To Node                                                                    ; Launch Clock                                             ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -0.040 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.816     ; 6.070      ;
; 0.018  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.808     ; 6.020      ;
; 0.027  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.819     ; 6.000      ;
; 0.037  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.817     ; 5.992      ;
; 0.041  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.834     ; 5.971      ;
; 0.065  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSCROLL[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.809     ; 5.972      ;
; 0.106  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.797     ; 5.943      ;
; 0.134  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.826     ; 5.886      ;
; 0.173  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.825     ; 5.848      ;
; 0.179  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[9]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.825     ; 5.842      ;
; 0.185  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[1]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.826     ; 5.835      ;
; 0.207  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.798     ; 5.841      ;
; 0.223  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[17] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.821     ; 5.802      ;
; 0.224  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHT[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.807     ; 5.815      ;
; 0.229  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.816     ; 5.801      ;
; 0.230  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.816     ; 5.800      ;
; 0.247  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_F[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.817     ; 5.782      ;
; 0.256  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.822     ; 5.768      ;
; 0.261  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[17]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.827     ; 5.758      ;
; 0.271  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.824     ; 5.751      ;
; 0.272  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|DMA_CONTROL[1]           ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.761      ;
; 0.274  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[25]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.805     ; 5.767      ;
; 0.281  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[14][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.799     ; 5.766      ;
; 0.285  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[25]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.824     ; 5.737      ;
; 0.287  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[0][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.808     ; 5.751      ;
; 0.292  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[15][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.809     ; 5.745      ;
; 0.302  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.817     ; 5.727      ;
; 0.312  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[1]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.826     ; 5.708      ;
; 0.321  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[8][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.797     ; 5.728      ;
; 0.325  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.816     ; 5.705      ;
; 0.360  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.812     ; 5.674      ;
; 0.362  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.812     ; 5.672      ;
; 0.362  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[1][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.803     ; 5.681      ;
; 0.364  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.808     ; 5.674      ;
; 0.366  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.817     ; 5.663      ;
; 0.367  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[13][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.810     ; 5.669      ;
; 0.369  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[12][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.810     ; 5.667      ;
; 0.370  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[6][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.805     ; 5.671      ;
; 0.370  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[7][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.805     ; 5.671      ;
; 0.372  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[9]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.830     ; 5.644      ;
; 0.379  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.834     ; 5.633      ;
; 0.379  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.847     ; 5.620      ;
; 0.390  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[2][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.801     ; 5.655      ;
; 0.391  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|LINEWIDTH[8]                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.830     ; 5.625      ;
; 0.393  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[4][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.801     ; 5.652      ;
; 0.393  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.851     ; 5.602      ;
; 0.397  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[25]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.822     ; 5.627      ;
; 0.405  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[8]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.834     ; 5.607      ;
; 0.410  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.623      ;
; 0.411  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[9][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.790     ; 5.645      ;
; 0.411  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.622      ;
; 0.416  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[241]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.814     ; 5.616      ;
; 0.421  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_MICROWIRE:I_MICROWIRE|GPx_EN_REG[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.819     ; 5.606      ;
; 0.421  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.804     ; 5.621      ;
; 0.424  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.609      ;
; 0.428  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[17]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.818     ; 5.600      ;
; 0.433  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.834     ; 5.579      ;
; 0.435  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.833     ; 5.578      ;
; 0.437  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|INTERLACED_EN  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.596      ;
; 0.438  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|FREQ_DIV_INT[1]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.816     ; 5.592      ;
; 0.439  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[11][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.795     ; 5.612      ;
; 0.444  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[10][1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.795     ; 5.607      ;
; 0.452  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHIFTMODE_ST[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.798     ; 5.596      ;
; 0.456  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBB[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.833     ; 5.557      ;
; 0.457  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[0]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.822     ; 5.567      ;
; 0.458  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.797     ; 5.591      ;
; 0.458  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSCROLL[2]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.809     ; 5.579      ;
; 0.459  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFE[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.823     ; 5.564      ;
; 0.460  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.842     ; 5.544      ;
; 0.462  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[16]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.827     ; 5.557      ;
; 0.462  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VBE[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.803     ; 5.581      ;
; 0.465  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|SMODE_CTRL[1]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.798     ; 5.583      ;
; 0.471  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[8]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.818     ; 5.557      ;
; 0.472  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[24]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.825     ; 5.549      ;
; 0.472  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_END[16]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.818     ; 5.556      ;
; 0.472  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[5]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.825     ; 5.549      ;
; 0.473  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[2]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.834     ; 5.539      ;
; 0.476  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[3][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.806     ; 5.564      ;
; 0.477  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|ST_PALETTE[5][1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.808     ; 5.561      ;
; 0.479  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|RP_FRAME_START[17]       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.822     ; 5.545      ;
; 0.479  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[204]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.814     ; 5.553      ;
; 0.482  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_BUFFER[240]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.814     ; 5.550      ;
; 0.485  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_GAIN[0]            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.548      ;
; 0.486  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|BUFF_INT[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.803     ; 5.557      ;
; 0.486  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFT[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.797     ; 5.563      ;
; 0.487  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_SRC[9]          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.803     ; 5.556      ;
; 0.488  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CODEC_DAC_SEL[0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.545      ;
; 0.491  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_MICROWIRE:I_MICROWIRE|GPx_EN_REG[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.819     ; 5.536      ;
; 0.493  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.825     ; 5.528      ;
; 0.495  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.830     ; 5.521      ;
; 0.495  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_BASE[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.825     ; 5.526      ;
; 0.496  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HFS[0]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.816     ; 5.534      ;
; 0.500  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_SOUND_REGs:SOUND_DMA_REGs|CROSSBAR_DEST[0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.815     ; 5.531      ;
; 0.501  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.829     ; 5.516      ;
; 0.502  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|VIDEO_ADR[9]   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.836     ; 5.508      ;
; 0.507  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[6]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.813     ; 5.526      ;
; 0.509  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HDB[4]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.836     ; 5.501      ;
; 0.510  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[0]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.851     ; 5.485      ;
; 0.512  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VSS[1]                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.834     ; 5.500      ;
; 0.516  ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1] ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|MCU_VIDEO_COUNTER:I_VIDEO|LINEOFFSET[1]  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 7.814        ; -1.851     ; 5.479      ;
+--------+----------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                     ;
+-------+----------------------------------------------------+--------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                          ; To Node                                                                              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------+--------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.269 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.825     ; 5.752      ;
; 0.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.825     ; 5.686      ;
; 0.354 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.801     ; 5.691      ;
; 0.389 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.796     ; 5.661      ;
; 0.411 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.790     ; 5.645      ;
; 0.412 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.816     ; 5.618      ;
; 0.414 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.816     ; 5.616      ;
; 0.419 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[0][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.789     ; 5.638      ;
; 0.441 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.822     ; 5.583      ;
; 0.441 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.822     ; 5.583      ;
; 0.442 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[9][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.799     ; 5.605      ;
; 0.447 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.824     ; 5.575      ;
; 0.448 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.593      ;
; 0.457 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[6][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.813     ; 5.576      ;
; 0.458 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.797     ; 5.591      ;
; 0.458 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[7][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.813     ; 5.575      ;
; 0.461 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.797     ; 5.588      ;
; 0.466 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.818     ; 5.562      ;
; 0.466 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.842     ; 5.538      ;
; 0.467 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.818     ; 5.561      ;
; 0.469 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK1[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.800     ; 5.577      ;
; 0.470 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.793     ; 5.583      ;
; 0.471 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.820     ; 5.555      ;
; 0.471 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.800     ; 5.577      ;
; 0.473 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.793     ; 5.580      ;
; 0.486 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.809     ; 5.551      ;
; 0.488 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.792     ; 5.566      ;
; 0.489 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.792     ; 5.565      ;
; 0.490 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.801     ; 5.557      ;
; 0.520 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.813     ; 5.513      ;
; 0.528 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_RELOAD[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.802     ; 5.516      ;
; 0.535 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.824     ; 5.487      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[12][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.799     ; 5.510      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[13][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.798     ; 5.511      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.824     ; 5.485      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.801     ; 5.510      ;
; 0.538 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.798     ; 5.510      ;
; 0.539 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.793     ; 5.514      ;
; 0.542 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.799     ; 5.505      ;
; 0.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HOP[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.790     ; 5.511      ;
; 0.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.801     ; 5.500      ;
; 0.546 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.801     ; 5.499      ;
; 0.551 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[6][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.798     ; 5.497      ;
; 0.551 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[7][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.798     ; 5.497      ;
; 0.554 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.487      ;
; 0.558 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.818     ; 5.470      ;
; 0.558 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.818     ; 5.470      ;
; 0.560 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[0]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.792     ; 5.494      ;
; 0.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.792     ; 5.491      ;
; 0.564 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.817     ; 5.465      ;
; 0.564 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.811     ; 5.471      ;
; 0.565 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.820     ; 5.461      ;
; 0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.817     ; 5.463      ;
; 0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.811     ; 5.469      ;
; 0.569 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[9]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.801     ; 5.476      ;
; 0.569 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.825     ; 5.452      ;
; 0.575 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.824     ; 5.447      ;
; 0.576 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.809     ; 5.461      ;
; 0.581 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.808     ; 5.457      ;
; 0.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.797     ; 5.462      ;
; 0.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.807     ; 5.452      ;
; 0.588 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[4][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.798     ; 5.460      ;
; 0.601 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.808     ; 5.437      ;
; 0.612 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.801     ; 5.435      ;
; 0.619 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.811     ; 5.416      ;
; 0.619 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.811     ; 5.416      ;
; 0.630 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.808     ; 5.408      ;
; 0.631 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.815     ; 5.400      ;
; 0.633 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.815     ; 5.398      ;
; 0.636 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|REPLAY_FIFO_REG[16][0]                          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.806     ; 5.404      ;
; 0.643 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[9]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.803     ; 5.402      ;
; 0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_COUNT[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.802     ; 5.397      ;
; 0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.801     ; 5.400      ;
; 0.649 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[2][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.800     ; 5.397      ;
; 0.649 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[3][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.800     ; 5.397      ;
; 0.655 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.807     ; 5.384      ;
; 0.656 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK1[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.797     ; 5.393      ;
; 0.659 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[9]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.796     ; 5.391      ;
; 0.660 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.795     ; 5.391      ;
; 0.661 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.797     ; 5.388      ;
; 0.664 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.377      ;
; 0.665 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.376      ;
; 0.671 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.804     ; 5.371      ;
; 0.671 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.804     ; 5.371      ;
; 0.673 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.822     ; 5.351      ;
; 0.673 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[0]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.816        ; -1.800     ; 5.375      ;
; 0.675 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][8]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.822     ; 5.349      ;
; 0.675 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[0][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.366      ;
; 0.676 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK3[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.798     ; 5.372      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.818     ; 5.351      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.818     ; 5.351      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.801     ; 5.368      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.801     ; 5.368      ;
; 0.678 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[4][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.363      ;
; 0.678 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[13][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.802     ; 5.366      ;
; 0.680 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[12][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.802     ; 5.364      ;
; 0.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[3][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.803     ; 5.361      ;
; 0.685 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.822     ; 5.339      ;
; 0.685 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.805     ; 5.356      ;
; 0.686 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 7.814        ; -1.797     ; 5.363      ;
+-------+----------------------------------------------------+--------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                     ;
+-------+----------------------------------------------------+--------------------------------------------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                          ; To Node                                                                              ; Launch Clock                                             ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------+--------------------------------------------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.269 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.825     ; 5.752      ;
; 0.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.825     ; 5.686      ;
; 0.354 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.801     ; 5.691      ;
; 0.389 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.796     ; 5.661      ;
; 0.411 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.790     ; 5.645      ;
; 0.412 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.816     ; 5.618      ;
; 0.414 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.816     ; 5.616      ;
; 0.419 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[0][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.789     ; 5.638      ;
; 0.441 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.822     ; 5.583      ;
; 0.441 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.822     ; 5.583      ;
; 0.442 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[9][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.799     ; 5.605      ;
; 0.447 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.824     ; 5.575      ;
; 0.448 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.593      ;
; 0.457 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[6][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.813     ; 5.576      ;
; 0.458 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.797     ; 5.591      ;
; 0.458 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[7][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.813     ; 5.575      ;
; 0.461 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[1]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.797     ; 5.588      ;
; 0.466 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.818     ; 5.562      ;
; 0.466 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|HD_REG[0]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.842     ; 5.538      ;
; 0.467 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.818     ; 5.561      ;
; 0.469 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK1[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.800     ; 5.577      ;
; 0.470 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.793     ; 5.583      ;
; 0.471 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.820     ; 5.555      ;
; 0.471 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[1]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.800     ; 5.577      ;
; 0.473 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[1]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.793     ; 5.580      ;
; 0.486 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_Y_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.809     ; 5.551      ;
; 0.488 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.792     ; 5.566      ;
; 0.489 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[1]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.792     ; 5.565      ;
; 0.490 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.801     ; 5.557      ;
; 0.520 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.813     ; 5.513      ;
; 0.528 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_RELOAD[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.802     ; 5.516      ;
; 0.535 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[13][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.824     ; 5.487      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[12][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.799     ; 5.510      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[13][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.798     ; 5.511      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.824     ; 5.485      ;
; 0.537 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[9]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.801     ; 5.510      ;
; 0.538 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.798     ; 5.510      ;
; 0.539 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_Y_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.793     ; 5.514      ;
; 0.542 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.799     ; 5.505      ;
; 0.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HOP[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.790     ; 5.511      ;
; 0.545 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.801     ; 5.500      ;
; 0.546 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][1]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.801     ; 5.499      ;
; 0.551 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[6][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.798     ; 5.497      ;
; 0.551 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[7][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.798     ; 5.497      ;
; 0.554 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.487      ;
; 0.558 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[11][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.818     ; 5.470      ;
; 0.558 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[12][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.818     ; 5.470      ;
; 0.560 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SKEW[0]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.792     ; 5.494      ;
; 0.563 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|OP[0]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.792     ; 5.491      ;
; 0.564 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[2][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.817     ; 5.465      ;
; 0.564 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.811     ; 5.471      ;
; 0.565 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[1][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.820     ; 5.461      ;
; 0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[3][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.817     ; 5.463      ;
; 0.566 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][9]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.811     ; 5.469      ;
; 0.569 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|FDMA_ACSI_REGs:ACSI_DMA_REGS|DMA_MODE_REG[9]                      ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.801     ; 5.476      ;
; 0.569 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.825     ; 5.452      ;
; 0.575 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.824     ; 5.447      ;
; 0.576 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.809     ; 5.461      ;
; 0.581 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0]     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.808     ; 5.457      ;
; 0.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[1]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.797     ; 5.462      ;
; 0.587 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.807     ; 5.452      ;
; 0.588 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[4][1]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.798     ; 5.460      ;
; 0.601 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[8][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.808     ; 5.437      ;
; 0.612 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.801     ; 5.435      ;
; 0.619 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[4][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.811     ; 5.416      ;
; 0.619 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[5][1]                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.811     ; 5.416      ;
; 0.630 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[14][1]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.808     ; 5.408      ;
; 0.631 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[10][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.815     ; 5.400      ;
; 0.633 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|ACSI_FIFO_REG[15][9]                            ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.815     ; 5.398      ;
; 0.636 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; FDMA_TOP_SOC:I_DMA|DMA_FIFOs:I_FIFOs|REPLAY_FIFO_REG[16][0]                          ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.806     ; 5.404      ;
; 0.643 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[9]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.803     ; 5.402      ;
; 0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|X_COUNT[1]                 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.802     ; 5.397      ;
; 0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68K30L_TOP:I_CPU|WF68K30L_BUS_INTERFACE:I_BUS_IF|DATA_INMUX[1]                     ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.801     ; 5.400      ;
; 0.649 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[2][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.800     ; 5.397      ;
; 0.649 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[3][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.800     ; 5.397      ;
; 0.655 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.807     ; 5.384      ;
; 0.656 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK1[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.797     ; 5.393      ;
; 0.659 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[9]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.796     ; 5.391      ;
; 0.660 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_X_INCR[9]             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.795     ; 5.391      ;
; 0.661 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK2[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.797     ; 5.388      ;
; 0.664 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][9]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.377      ;
; 0.665 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][9]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.376      ;
; 0.671 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.804     ; 5.371      ;
; 0.671 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1] ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1]                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.804     ; 5.371      ;
; 0.673 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.822     ; 5.351      ;
; 0.673 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|DEST_BUFF[0]               ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.816        ; -1.800     ; 5.375      ;
; 0.675 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[5][8]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.822     ; 5.349      ;
; 0.675 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[0][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.366      ;
; 0.676 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|ENDMASK3[0]                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.798     ; 5.372      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.818     ; 5.351      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.818     ; 5.351      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[14][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.801     ; 5.368      ;
; 0.677 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[15][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.801     ; 5.368      ;
; 0.678 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[4][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.363      ;
; 0.678 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[13][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.802     ; 5.366      ;
; 0.680 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[12][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.802     ; 5.364      ;
; 0.682 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[3][0]         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.803     ; 5.361      ;
; 0.685 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[11][0]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.822     ; 5.339      ;
; 0.685 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|HALFTONE_RAM[10][8]        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.805     ; 5.356      ;
; 0.686 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9] ; COMBEL_TOP:I_COMBEL|BLITTER_TOP:I_BLT|BLITTER_CORE:I_CORE|SRC_X_INCR[9]              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 7.814        ; -1.797     ; 5.363      ;
+-------+----------------------------------------------------+--------------------------------------------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                   ;
+-------+----------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                          ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 4.302 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.166     ; 3.376      ;
; 4.302 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.166     ; 3.376      ;
; 4.302 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.166     ; 3.376      ;
; 4.302 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.166     ; 3.376      ;
; 4.302 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.166     ; 3.376      ;
; 4.302 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.166     ; 3.376      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.304 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][11]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.173     ; 3.367      ;
; 4.321 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.153     ; 3.370      ;
; 4.321 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.153     ; 3.370      ;
; 4.321 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.153     ; 3.370      ;
; 4.321 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.153     ; 3.370      ;
; 4.321 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.153     ; 3.370      ;
; 4.321 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][23]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.153     ; 3.370      ;
; 4.325 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.151     ; 3.368      ;
; 4.325 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.151     ; 3.368      ;
; 4.330 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.167     ; 3.347      ;
; 4.330 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.167     ; 3.347      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.335 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.152     ; 3.357      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.339 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][18]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.137     ; 3.368      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.341 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.164     ; 3.339      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.344 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][8]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.361      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][14]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.345 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][7]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.144     ; 3.355      ;
; 4.346 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.162     ; 3.336      ;
; 4.346 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.162     ; 3.336      ;
; 4.346 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.162     ; 3.336      ;
; 4.346 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.162     ; 3.336      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.349 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][26]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.354      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[9][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[3][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[9][31]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.352 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.139     ; 3.353      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[5][24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[4][24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[6][24]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.357 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[7][4]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.141     ; 3.346      ;
; 4.358 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.161     ; 3.325      ;
; 4.358 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][6]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.161     ; 3.325      ;
; 4.359 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[1][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.135     ; 3.350      ;
; 4.359 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[2][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; 7.812        ; -0.135     ; 3.350      ;
+-------+----------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CLK_PLL1'                                                                                               ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 61.372 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.160      ;
; 61.372 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.160      ;
; 61.372 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.160      ;
; 61.372 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.160      ;
; 61.372 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.160      ;
; 61.458 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.074      ;
; 61.458 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.074      ;
; 61.458 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.074      ;
; 61.458 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.074      ;
; 61.458 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 1.074      ;
; 61.564 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.968      ;
; 61.564 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.968      ;
; 61.564 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.968      ;
; 61.564 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.968      ;
; 61.564 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.968      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.583 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.949      ;
; 61.618 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.914      ;
; 61.639 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.893      ;
; 61.642 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.890      ;
; 61.642 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.890      ;
; 61.642 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.890      ;
; 61.642 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.890      ;
; 61.642 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.890      ;
; 61.704 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.828      ;
; 61.725 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.807      ;
; 61.810 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.722      ;
; 61.829 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.703      ;
; 61.831 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.701      ;
; 61.850 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.682      ;
; 61.888 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.644      ;
; 61.909 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.623      ;
; 62.013 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 62.500       ; 0.000      ; 0.519      ;
+--------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 62.012 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.520      ;
; 62.137 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.395      ;
; 62.138 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.394      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
; 62.165 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 62.500       ; 0.000      ; 0.367      ;
+--------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.600 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.963      ; 0.515      ;
; -1.600 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.963      ; 0.515      ;
; -1.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.963      ; 0.531      ;
; -1.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.963      ; 0.531      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.993      ; 0.642      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.613      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.993      ; 0.642      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.613      ;
; -1.500 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.643      ;
; -1.500 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.643      ;
; -1.478 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.638      ;
; -1.478 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.638      ;
; -1.389 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.754      ;
; -1.389 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.754      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.372 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.986      ; 0.766      ;
; -1.372 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.986      ; 0.766      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.773      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.762      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.773      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.762      ;
; -1.366 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.766      ;
; -1.366 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.766      ;
; -1.353 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.986      ; 0.785      ;
; -1.353 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.986      ; 0.785      ;
; -1.318 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.993      ; 0.827      ;
; -1.318 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.993      ; 0.827      ;
; -1.315 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.988      ; 0.825      ;
; -1.315 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.988      ; 0.825      ;
; -1.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.819      ;
; -1.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.819      ;
; -1.299 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.976      ; 0.829      ;
; -1.299 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.976      ; 0.829      ;
; -1.289 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.978      ; 0.841      ;
; -1.289 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.978      ; 0.841      ;
; -1.280 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.843      ;
; -1.280 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.843      ;
; -1.279 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.970      ; 0.843      ;
; -1.279 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.970      ; 0.843      ;
; -1.278 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.990      ; 0.864      ;
; -1.278 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.990      ; 0.864      ;
; -1.271 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.861      ;
; -1.271 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.861      ;
; -1.268 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.973      ; 0.857      ;
; -1.268 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.973      ; 0.857      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.878      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.979      ; 0.866      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.986      ; 0.873      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.878      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.979      ; 0.866      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.986      ; 0.873      ;
; -1.255 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.978      ; 0.875      ;
; -1.255 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.978      ; 0.875      ;
; -1.251 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.939      ; 0.840      ;
; -1.251 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.939      ; 0.840      ;
; -1.242 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.955      ; 0.865      ;
; -1.242 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.955      ; 0.865      ;
; -1.236 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.955      ; 0.871      ;
; -1.236 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.955      ; 0.871      ;
; -1.222 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.894      ;
; -1.222 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.894      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.896      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.896      ;
; -1.219 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.904      ;
; -1.219 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.904      ;
; -1.208 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.924      ;
; -1.208 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.924      ;
; -1.207 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.909      ;
; -1.207 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.964      ; 0.909      ;
; -1.204 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.939      ;
; -1.204 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.939      ;
; -1.203 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.988      ; 0.937      ;
; -1.203 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.988      ; 0.937      ;
; -1.199 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.961      ; 0.914      ;
; -1.199 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.961      ; 0.914      ;
; -1.195 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.961      ; 0.918      ;
; -1.195 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.961      ; 0.918      ;
; -1.181 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.962      ;
; -1.181 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.991      ; 0.962      ;
; -1.174 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.958      ;
; -1.174 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.980      ; 0.958      ;
; -1.173 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.997      ; 0.976      ;
; -1.173 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.997      ; 0.976      ;
; -1.167 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.970      ; 0.955      ;
; -1.167 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.970      ; 0.955      ;
; -1.164 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.977      ; 0.965      ;
; -1.164 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.977      ; 0.965      ;
; -1.163 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.979      ; 0.968      ;
; -1.163 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.979      ; 0.968      ;
; -1.161 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.987      ; 0.978      ;
; -1.161 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.987      ; 0.978      ;
; -1.153 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.939      ; 0.938      ;
; -1.153 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.939      ; 0.938      ;
; -1.152 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.984      ; 0.984      ;
; -1.152 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.984      ; 0.984      ;
; -1.149 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.971      ; 0.974      ;
; -1.149 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 1.997      ; 1.000      ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -1.600 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.963      ; 0.515      ;
; -1.600 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.963      ; 0.515      ;
; -1.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.963      ; 0.531      ;
; -1.584 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.963      ; 0.531      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.993      ; 0.642      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.613      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.993      ; 0.642      ;
; -1.503 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.613      ;
; -1.500 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.643      ;
; -1.500 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.643      ;
; -1.478 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.638      ;
; -1.478 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.638      ;
; -1.389 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.754      ;
; -1.389 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.754      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.379 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.753      ;
; -1.372 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.986      ; 0.766      ;
; -1.372 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.986      ; 0.766      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.773      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.762      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.773      ;
; -1.370 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.762      ;
; -1.366 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.766      ;
; -1.366 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.766      ;
; -1.353 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.986      ; 0.785      ;
; -1.353 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.986      ; 0.785      ;
; -1.318 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.993      ; 0.827      ;
; -1.318 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.993      ; 0.827      ;
; -1.315 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.988      ; 0.825      ;
; -1.315 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.988      ; 0.825      ;
; -1.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.819      ;
; -1.304 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.819      ;
; -1.299 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.976      ; 0.829      ;
; -1.299 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.976      ; 0.829      ;
; -1.289 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.978      ; 0.841      ;
; -1.289 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.978      ; 0.841      ;
; -1.280 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.843      ;
; -1.280 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.843      ;
; -1.279 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.970      ; 0.843      ;
; -1.279 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.970      ; 0.843      ;
; -1.278 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.990      ; 0.864      ;
; -1.278 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.990      ; 0.864      ;
; -1.271 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.861      ;
; -1.271 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.861      ;
; -1.268 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.973      ; 0.857      ;
; -1.268 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.973      ; 0.857      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.878      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.979      ; 0.866      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.986      ; 0.873      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.878      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.979      ; 0.866      ;
; -1.265 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.986      ; 0.873      ;
; -1.255 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.978      ; 0.875      ;
; -1.255 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.978      ; 0.875      ;
; -1.251 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.939      ; 0.840      ;
; -1.251 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.939      ; 0.840      ;
; -1.242 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.955      ; 0.865      ;
; -1.242 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.955      ; 0.865      ;
; -1.236 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.955      ; 0.871      ;
; -1.236 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.955      ; 0.871      ;
; -1.222 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.894      ;
; -1.222 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.894      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.896      ;
; -1.220 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.896      ;
; -1.219 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.904      ;
; -1.219 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.904      ;
; -1.208 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.924      ;
; -1.208 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.924      ;
; -1.207 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.909      ;
; -1.207 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.964      ; 0.909      ;
; -1.204 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.939      ;
; -1.204 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.939      ;
; -1.203 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.988      ; 0.937      ;
; -1.203 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.988      ; 0.937      ;
; -1.199 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.961      ; 0.914      ;
; -1.199 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.961      ; 0.914      ;
; -1.195 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.961      ; 0.918      ;
; -1.195 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.961      ; 0.918      ;
; -1.181 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.962      ;
; -1.181 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.991      ; 0.962      ;
; -1.174 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.958      ;
; -1.174 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.980      ; 0.958      ;
; -1.173 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.997      ; 0.976      ;
; -1.173 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.997      ; 0.976      ;
; -1.167 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.970      ; 0.955      ;
; -1.167 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.970      ; 0.955      ;
; -1.164 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.977      ; 0.965      ;
; -1.164 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.977      ; 0.965      ;
; -1.163 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.979      ; 0.968      ;
; -1.163 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.979      ; 0.968      ;
; -1.161 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.987      ; 0.978      ;
; -1.161 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.987      ; 0.978      ;
; -1.153 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.939      ; 0.938      ;
; -1.153 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.939      ; 0.938      ;
; -1.152 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.984      ; 0.984      ;
; -1.152 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.984      ; 0.984      ;
; -1.149 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.971      ; 0.974      ;
; -1.149 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; 1.997      ; 1.000      ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.460 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.825      ; 0.515      ;
; -1.460 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.825      ; 0.515      ;
; -1.444 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.825      ; 0.531      ;
; -1.444 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.825      ; 0.531      ;
; -1.363 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.855      ; 0.642      ;
; -1.363 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.613      ;
; -1.363 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.855      ; 0.642      ;
; -1.363 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.613      ;
; -1.360 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.643      ;
; -1.360 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.643      ;
; -1.338 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.638      ;
; -1.338 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.638      ;
; -1.249 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.754      ;
; -1.249 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.754      ;
; -1.239 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.753      ;
; -1.239 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.753      ;
; -1.239 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.753      ;
; -1.239 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.753      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.848      ; 0.766      ;
; -1.232 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.848      ; 0.766      ;
; -1.230 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.773      ;
; -1.230 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.762      ;
; -1.230 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.773      ;
; -1.230 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.762      ;
; -1.226 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.766      ;
; -1.226 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.766      ;
; -1.213 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.848      ; 0.785      ;
; -1.213 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.848      ; 0.785      ;
; -1.178 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.855      ; 0.827      ;
; -1.178 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.855      ; 0.827      ;
; -1.175 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.850      ; 0.825      ;
; -1.175 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.850      ; 0.825      ;
; -1.164 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.819      ;
; -1.164 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.819      ;
; -1.159 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.838      ; 0.829      ;
; -1.159 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.838      ; 0.829      ;
; -1.149 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.840      ; 0.841      ;
; -1.149 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.840      ; 0.841      ;
; -1.140 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.843      ;
; -1.140 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.843      ;
; -1.139 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.832      ; 0.843      ;
; -1.139 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.832      ; 0.843      ;
; -1.138 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.852      ; 0.864      ;
; -1.138 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.852      ; 0.864      ;
; -1.131 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.861      ;
; -1.131 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.861      ;
; -1.128 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.835      ; 0.857      ;
; -1.128 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.835      ; 0.857      ;
; -1.125 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.878      ;
; -1.125 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.841      ; 0.866      ;
; -1.125 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.848      ; 0.873      ;
; -1.125 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.878      ;
; -1.125 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.841      ; 0.866      ;
; -1.125 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.848      ; 0.873      ;
; -1.115 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.840      ; 0.875      ;
; -1.115 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.840      ; 0.875      ;
; -1.111 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.801      ; 0.840      ;
; -1.111 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.801      ; 0.840      ;
; -1.102 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.817      ; 0.865      ;
; -1.102 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.817      ; 0.865      ;
; -1.096 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.817      ; 0.871      ;
; -1.096 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.817      ; 0.871      ;
; -1.082 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.894      ;
; -1.082 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.894      ;
; -1.080 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.896      ;
; -1.080 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.896      ;
; -1.079 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.904      ;
; -1.079 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.904      ;
; -1.068 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.924      ;
; -1.068 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.924      ;
; -1.067 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.909      ;
; -1.067 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.826      ; 0.909      ;
; -1.064 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.939      ;
; -1.064 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.939      ;
; -1.063 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.850      ; 0.937      ;
; -1.063 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.850      ; 0.937      ;
; -1.059 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.823      ; 0.914      ;
; -1.059 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.823      ; 0.914      ;
; -1.055 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.823      ; 0.918      ;
; -1.055 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.823      ; 0.918      ;
; -1.041 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.962      ;
; -1.041 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.853      ; 0.962      ;
; -1.034 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.958      ;
; -1.034 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.842      ; 0.958      ;
; -1.033 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.859      ; 0.976      ;
; -1.033 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.859      ; 0.976      ;
; -1.027 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.832      ; 0.955      ;
; -1.027 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.832      ; 0.955      ;
; -1.024 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.839      ; 0.965      ;
; -1.024 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.839      ; 0.965      ;
; -1.023 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.841      ; 0.968      ;
; -1.023 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.841      ; 0.968      ;
; -1.021 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.849      ; 0.978      ;
; -1.021 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.849      ; 0.978      ;
; -1.013 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.801      ; 0.938      ;
; -1.013 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.801      ; 0.938      ;
; -1.012 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.846      ; 0.984      ;
; -1.012 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.846      ; 0.984      ;
; -1.009 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.833      ; 0.974      ;
; -1.009 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; -0.002       ; 1.859      ; 1.000      ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.447      ; 0.515      ;
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.447      ; 0.515      ;
; -1.068 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.447      ; 0.531      ;
; -1.068 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.447      ; 0.531      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.477      ; 0.642      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.613      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.477      ; 0.642      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.613      ;
; -0.984 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.643      ;
; -0.984 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.643      ;
; -0.962 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.638      ;
; -0.962 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.638      ;
; -0.873 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.754      ;
; -0.873 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.754      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.753      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.753      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.753      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.753      ;
; -0.856 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.470      ; 0.766      ;
; -0.856 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.470      ; 0.766      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.773      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.762      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.773      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.762      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.766      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.766      ;
; -0.837 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.470      ; 0.785      ;
; -0.837 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.470      ; 0.785      ;
; -0.825 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                               ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.453      ; 0.780      ;
; -0.825 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                               ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.453      ; 0.780      ;
; -0.802 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.477      ; 0.827      ;
; -0.802 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.477      ; 0.827      ;
; -0.799 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.472      ; 0.825      ;
; -0.799 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.472      ; 0.825      ;
; -0.788 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.455      ; 0.819      ;
; -0.788 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.455      ; 0.819      ;
; -0.783 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.460      ; 0.829      ;
; -0.783 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.460      ; 0.829      ;
; -0.773 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.462      ; 0.841      ;
; -0.773 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.462      ; 0.841      ;
; -0.764 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.455      ; 0.843      ;
; -0.764 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.455      ; 0.843      ;
; -0.763 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.454      ; 0.843      ;
; -0.763 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.454      ; 0.843      ;
; -0.762 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.474      ; 0.864      ;
; -0.762 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.474      ; 0.864      ;
; -0.755 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.861      ;
; -0.755 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.861      ;
; -0.752 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.457      ; 0.857      ;
; -0.752 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.457      ; 0.857      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.878      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.463      ; 0.866      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.470      ; 0.873      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.878      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.463      ; 0.866      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.470      ; 0.873      ;
; -0.739 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.462      ; 0.875      ;
; -0.739 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.462      ; 0.875      ;
; -0.735 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.423      ; 0.840      ;
; -0.735 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.423      ; 0.840      ;
; -0.726 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.439      ; 0.865      ;
; -0.726 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.439      ; 0.865      ;
; -0.720 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.439      ; 0.871      ;
; -0.720 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.439      ; 0.871      ;
; -0.706 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.894      ;
; -0.706 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.894      ;
; -0.704 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.896      ;
; -0.704 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.896      ;
; -0.703 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.455      ; 0.904      ;
; -0.703 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.455      ; 0.904      ;
; -0.692 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.924      ;
; -0.692 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.924      ;
; -0.691 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.909      ;
; -0.691 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.448      ; 0.909      ;
; -0.688 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.939      ;
; -0.688 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.939      ;
; -0.687 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.472      ; 0.937      ;
; -0.687 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.472      ; 0.937      ;
; -0.683 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.445      ; 0.914      ;
; -0.683 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.445      ; 0.914      ;
; -0.679 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.445      ; 0.918      ;
; -0.679 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.445      ; 0.918      ;
; -0.665 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.962      ;
; -0.665 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.475      ; 0.962      ;
; -0.658 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.958      ;
; -0.658 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.464      ; 0.958      ;
; -0.657 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.481      ; 0.976      ;
; -0.657 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.481      ; 0.976      ;
; -0.651 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.454      ; 0.955      ;
; -0.651 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.454      ; 0.955      ;
; -0.648 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.461      ; 0.965      ;
; -0.648 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.461      ; 0.965      ;
; -0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.463      ; 0.968      ;
; -0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.463      ; 0.968      ;
; -0.645 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.471      ; 0.978      ;
; -0.645 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.471      ; 0.978      ;
; -0.637 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.423      ; 0.938      ;
; -0.637 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.423      ; 0.938      ;
; -0.636 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.468      ; 0.984      ;
; -0.636 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 1.468      ; 0.984      ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                            ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                          ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.447      ; 0.515      ;
; -1.084 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.447      ; 0.515      ;
; -1.068 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.447      ; 0.531      ;
; -1.068 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.447      ; 0.531      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.477      ; 0.642      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.613      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[1]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][1]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.477      ; 0.642      ;
; -0.987 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.613      ;
; -0.984 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.643      ;
; -0.984 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[12]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][12] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.643      ;
; -0.962 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.638      ;
; -0.962 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[23]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][23] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.638      ;
; -0.873 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.754      ;
; -0.873 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[0]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.754      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.753      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.753      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.753      ;
; -0.863 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.753      ;
; -0.856 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.470      ; 0.766      ;
; -0.856 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.470      ; 0.766      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.773      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.762      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.773      ;
; -0.854 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.762      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.766      ;
; -0.850 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.766      ;
; -0.837 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.470      ; 0.785      ;
; -0.837 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.470      ; 0.785      ;
; -0.825 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                               ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.453      ; 0.780      ;
; -0.825 ; VIDEL_TOP:I_VIDEO|VDATA_ACK                               ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.453      ; 0.780      ;
; -0.802 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.477      ; 0.827      ;
; -0.802 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[17]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][17]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.477      ; 0.827      ;
; -0.799 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.472      ; 0.825      ;
; -0.799 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[25]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][25]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.472      ; 0.825      ;
; -0.788 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.455      ; 0.819      ;
; -0.788 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[19]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][19] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.455      ; 0.819      ;
; -0.783 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.460      ; 0.829      ;
; -0.783 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][20] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.460      ; 0.829      ;
; -0.773 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.462      ; 0.841      ;
; -0.773 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.462      ; 0.841      ;
; -0.764 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.455      ; 0.843      ;
; -0.764 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[31]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][31] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.455      ; 0.843      ;
; -0.763 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.454      ; 0.843      ;
; -0.763 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.454      ; 0.843      ;
; -0.762 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.474      ; 0.864      ;
; -0.762 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[6]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][6]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.474      ; 0.864      ;
; -0.755 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.861      ;
; -0.755 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.861      ;
; -0.752 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.457      ; 0.857      ;
; -0.752 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[30]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][30] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.457      ; 0.857      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.878      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.463      ; 0.866      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.470      ; 0.873      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][2]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.878      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[24]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][24] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.463      ; 0.866      ;
; -0.749 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[4]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][4]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.470      ; 0.873      ;
; -0.739 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.462      ; 0.875      ;
; -0.739 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][5]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.462      ; 0.875      ;
; -0.735 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.423      ; 0.840      ;
; -0.735 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VTYPE         ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.423      ; 0.840      ;
; -0.726 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.439      ; 0.865      ;
; -0.726 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.439      ; 0.865      ;
; -0.720 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.439      ; 0.871      ;
; -0.720 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.439      ; 0.871      ;
; -0.706 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.894      ;
; -0.706 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[20]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][20]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.894      ;
; -0.704 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.896      ;
; -0.704 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[16]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][16] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.896      ;
; -0.703 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.455      ; 0.904      ;
; -0.703 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[22]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[11][22] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.455      ; 0.904      ;
; -0.692 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.924      ;
; -0.692 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.924      ;
; -0.691 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.909      ;
; -0.691 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[3]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[10][3]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.448      ; 0.909      ;
; -0.688 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.939      ;
; -0.688 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[14]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][14] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.939      ;
; -0.687 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.472      ; 0.937      ;
; -0.687 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[9]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][9]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.472      ; 0.937      ;
; -0.683 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.445      ; 0.914      ;
; -0.683 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.445      ; 0.914      ;
; -0.679 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.445      ; 0.918      ;
; -0.679 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[8]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[12][8]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.445      ; 0.918      ;
; -0.665 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.962      ;
; -0.665 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[2]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[16][2]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.475      ; 0.962      ;
; -0.658 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.958      ;
; -0.658 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[7]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][7]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.464      ; 0.958      ;
; -0.657 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.481      ; 0.976      ;
; -0.657 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[15]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][15]  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.481      ; 0.976      ;
; -0.651 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.454      ; 0.955      ;
; -0.651 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[5]                    ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][5]   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.454      ; 0.955      ;
; -0.648 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.461      ; 0.965      ;
; -0.648 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[10]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][10] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.461      ; 0.965      ;
; -0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.463      ; 0.968      ;
; -0.647 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[14][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.463      ; 0.968      ;
; -0.645 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.471      ; 0.978      ;
; -0.645 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[11]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[15][11] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.471      ; 0.978      ;
; -0.637 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.423      ; 0.938      ;
; -0.637 ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_CTRL[1] ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_STRB           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.423      ; 0.938      ;
; -0.636 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.468      ; 0.984      ;
; -0.636 ; VIDEL_TOP:I_VIDEO|VIDEO_DATA_BUFFER[27]                   ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[13][27] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 1.468      ; 0.984      ;
+--------+-----------------------------------------------------------+------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                                                                                                             ; To Node                                                                                                                                                                                                                                                                                                 ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; \P_2M4576:TMP_2M54[0]                                                                                                                                                                                                                                                                                 ; \P_2M4576:TMP_2M54[0]                                                                                                                                                                                                                                                                                   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig                                                                                                                                                            ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig                                                                                                                                                              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:done                                                                                                                                                                  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:done                                                                                                                                                                    ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:base_address[0]                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:base_address[0]                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:is_buffer_wrapped                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|\buffer_manager:is_buffer_wrapped                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|last_level_delayed                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|last_level_delayed                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_out_mode_ff                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_out_mode_ff                                                                                                                                                                                                                ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.367      ;
; 0.235 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][7]                                                                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][7]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.387      ;
; 0.235 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][267]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][267]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.387      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|condition_delay_reg[0]                                                                                                                                                                                                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|condition_delay_reg[1]                                                                                                                                                                                                             ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:147:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:147:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][33]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][33]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][32]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][32]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][82]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][82]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][105]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][105]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][108]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][108]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][141]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][141]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][148]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][148]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[155]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][155]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][208]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][208]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][212]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][212]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[211]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][211]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][218]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][218]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][253]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][253]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][265]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][265]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.236 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][296]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][296]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.388      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:169:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:169:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:167:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:167:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:131:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:131:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:156:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:156:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:73:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|holdff  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|regoutff  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][29]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][29]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][2]                                                                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][2]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][25]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][25]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][23]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][23]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[2]                                                                                                                                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][2]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[5]                                                                                                                                                                                                               ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][5]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][59]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][59]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][76]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][76]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][105]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][105]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][102]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][102]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][81]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][81]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][130]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][130]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][168]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][168]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][202]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][202]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][210]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][210]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][188]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][188]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][200]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][200]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][224]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][224]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][223]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][223]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][226]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][226]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[231]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][231]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[229]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][229]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][270]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][270]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][268]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][268]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][282]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][282]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.237 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][300]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][300]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.389      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:185:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:185:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:210:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:210:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:220:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:220:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:120:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:120:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:149:sm1|holdff ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:149:sm1|regoutff ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][14]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][14]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][17]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][17]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][6]                                                                                                                                                                                                       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][6]                                                                                                                                                                                                         ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][21]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][21]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][34]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][34]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][29]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][29]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[31]                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][31]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][39]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][39]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][51]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][51]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][60]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][60]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][57]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][57]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][53]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][53]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][57]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][57]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[51]                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][51]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][78]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][78]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][103]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][103]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][72]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][72]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][106]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][106]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][95]                                                                                                                                                                                                      ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][95]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[99]                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][99]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[87]                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][87]                                                                                                                                                                                                        ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][131]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][131]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][133]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][133]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][152]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][152]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][153]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][153]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][157]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][157]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][165]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][165]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][169]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][169]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][147]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][147]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][160]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][160]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[160]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][160]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][195]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[3][195]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][205]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][205]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][213]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[2][213]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
; 0.238 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[0][182]                                                                                                                                                                                                     ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_pipe_reg[1][182]                                                                                                                                                                                                       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; 0.000      ; 0.390      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                                                                        ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock                                             ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.215 ; CLK_2M0              ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[1] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[0] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.367      ;
; 0.242 ; \P_AUX_CLOCKS:TMP[0] ; \P_AUX_CLOCKS:TMP[1] ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.394      ;
; 0.243 ; \P_AUX_CLOCKS:TMP[0] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.395      ;
; 0.368 ; \P_AUX_CLOCKS:TMP[1] ; CLK_2M0              ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; 0.000        ; 0.000      ; 0.520      ;
+-------+----------------------+----------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CLK_PLL1'                                                                                               ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node            ; To Node              ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+
; 0.358 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.510      ;
; 0.359 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.511      ;
; 0.367 ; \PLL_RESET:LOCK      ; PLL_ARESET           ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.519      ;
; 0.376 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.528      ;
; 0.376 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.528      ;
; 0.376 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.528      ;
; 0.471 ; \PLL_LOCK_FLT:TMP[2] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.623      ;
; 0.492 ; \PLL_LOCK_FLT:TMP[2] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.644      ;
; 0.496 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.648      ;
; 0.516 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.668      ;
; 0.516 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.668      ;
; 0.530 ; \PLL_LOCK_FLT:TMP[3] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.682      ;
; 0.549 ; \PLL_LOCK_FLT:TMP[4] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.701      ;
; 0.551 ; \PLL_LOCK_FLT:TMP[3] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.703      ;
; 0.551 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.703      ;
; 0.552 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.704      ;
; 0.570 ; \PLL_LOCK_FLT:TMP[4] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.722      ;
; 0.587 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.739      ;
; 0.610 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.762      ;
; 0.622 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.774      ;
; 0.645 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.797      ;
; 0.655 ; \PLL_LOCK_FLT:TMP[1] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.807      ;
; 0.676 ; \PLL_LOCK_FLT:TMP[1] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.828      ;
; 0.680 ; \PLL_LOCK_FLT:TMP[0] ; \PLL_LOCK_FLT:TMP[4] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.832      ;
; 0.738 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.890      ;
; 0.738 ; \PLL_LOCK_FLT:TMP[2] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.890      ;
; 0.741 ; \PLL_LOCK_FLT:TMP[0] ; PLL_LOCKS            ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.893      ;
; 0.762 ; \PLL_LOCK_FLT:TMP[0] ; PLL_FAULT~reg0       ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.914      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.797 ; \PLL_LOCK_FLT:TMP[3] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.949      ;
; 0.816 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[3] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.968      ;
; 0.816 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[2] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.968      ;
; 0.816 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.968      ;
; 0.816 ; \PLL_LOCK_FLT:TMP[4] ; \PLL_LOCK_FLT:TMP[1] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 0.968      ;
; 0.922 ; \PLL_LOCK_FLT:TMP[1] ; \PLL_LOCK_FLT:TMP[0] ; CLK_PLL1     ; CLK_PLL1    ; 0.000        ; 0.000      ; 1.074      ;
+-------+----------------------+----------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                       ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                                                   ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 27.164 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 4.165      ;
; 27.164 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 4.165      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.149      ;
; 27.288 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 4.041      ;
; 27.288 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.047      ; 4.041      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.032      ; 4.025      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 3.958      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.043      ; 3.961      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 3.958      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.040      ; 3.958      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.035      ; 3.953      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.042      ; 3.960      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.033      ; 3.951      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 31.250       ; 0.038      ; 3.956      ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                                                                                                       ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                       ; To Node                                                                                                   ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 27.164 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 4.165      ;
; 27.164 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 4.165      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.149      ;
; 27.165 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.149      ;
; 27.288 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 4.041      ;
; 27.288 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FS_B_VAR   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.047      ; 4.041      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|FS_B_I             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|M_CIP              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.025      ;
; 27.289 ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ  ; WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_FS_B:FIRST_READ ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.032      ; 4.025      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.957      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.363 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 3.958      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.043      ; 3.961      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 3.958      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.040      ; 3.958      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.035      ; 3.953      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[2]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.042      ; 3.960      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1]                                           ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.039      ; 3.957      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10]                                         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.033      ; 3.951      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|PORT_A[7]                                                                        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.036      ; 3.954      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15]                                            ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]                                             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.037      ; 3.955      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
; 27.364 ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6] ; WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 31.250       ; 0.038      ; 3.956      ;
+--------+-------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                              ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.029     ; 1.261      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 31.250       ; -0.030     ; 1.105      ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                              ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 1.261      ;
; 29.992 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.029     ; 1.261      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
; 30.147 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 31.250       ; -0.030     ; 1.105      ;
+--------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                              ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.030     ; 1.105      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; 0.000        ; -0.029     ; 1.261      ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                              ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                            ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[4]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[1]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[2]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[3]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[5]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[0]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[6]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[7]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[8]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 0.983 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|INIT_STATE[9]    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.030     ; 1.105      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[0] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[2] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 1.261      ;
; 1.138 ; RESET_CORE_Sn ; COMBEL_TOP:I_COMBEL|MCU_TOP:I_MCU|\P_SDINIT:TMP[1] ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 0.000        ; -0.029     ; 1.261      ;
+-------+---------------+----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                                                                                ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                              ; Launch Clock                                               ; Latch Clock                                              ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.025     ; 1.379      ;
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.025     ; 1.379      ;
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.025     ; 1.379      ;
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.025     ; 1.379      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.533      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.035     ; 1.529      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.024     ; 1.550      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.026     ; 1.561      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.033     ; 1.632      ;
; 1.562 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.008     ; 1.706      ;
; 1.562 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.008     ; 1.706      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.749      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.749      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.749      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; 0.001      ; 1.749      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; 0.000        ; -0.006     ; 1.777      ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                                                                                ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node     ; To Node                                              ; Launch Clock                                               ; Latch Clock                                                ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.025     ; 1.379      ;
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.025     ; 1.379      ;
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_2     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.025     ; 1.379      ;
; 1.252 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.IDLE          ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.025     ; 1.379      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAIT_MC_1     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_ERASE_2 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_RD      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.ADR_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.404 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.CMD_REQ       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.533      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.FLASH_WR      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WRITE_CMD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.FLASH_INIT   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.IDLE        ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.IDLE         ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.WRITE_CMD   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.FLASH_INIT  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.DATA_LOAD    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_END   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ERASE_STATE.READY       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WAIT_ACK    ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.023     ; 1.541      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|WRITE_STATE.WRITE_DATA  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.017     ; 1.547      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[1]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[0]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[3]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[7]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[6]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.412 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[5]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.035     ; 1.529      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[15]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[14]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[13]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[12]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.422 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[19]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.024     ; 1.550      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[18]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[17]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[16]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[11]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[10]             ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[9]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.435 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[8]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.026     ; 1.561      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|READ_STATE.WAIT_ACK     ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[4]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.033     ; 1.632      ;
; 1.513 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|ADR_REG[2]              ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.033     ; 1.632      ;
; 1.562 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.008     ; 1.706      ;
; 1.562 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_VERSION  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.008     ; 1.706      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.749      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.749      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.WAITVERSION   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.749      ;
; 1.596 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|SPI_STATE.SEND_CORETYPE ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; 0.001      ; 1.749      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[23]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[22]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[20]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[21]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[17]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.006     ; 1.777      ;
; 1.631 ; RESET_CORE_Sn ; FLASHBOOT_UMASPI:I_FLASHBOOT|\P_STARTUP:TMP[19]      ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 0.000        ; -0.006     ; 1.777      ;
+-------+---------------+------------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg0  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg0  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg1  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg1  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg2  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg2  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg3  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg3  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg4  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg4  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg5  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg5  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg6  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_address_reg6  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg0   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg1   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg1   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg10  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg10  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg11  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg11  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg12  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg12  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg13  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg13  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg14  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg14  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg15  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg15  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg16  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg16  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg17  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg17  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg18  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg18  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg19  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg19  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg2   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg2   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg20  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg20  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg21  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg21  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg22  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg22  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg23  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg23  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg24  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg24  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg25  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg25  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg26  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg26  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg27  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg27  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg28  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg28  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg29  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg29  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg3   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg3   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg30  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg30  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg31  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg31  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg32  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg32  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg33  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg33  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg34  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg34  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg35  ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg35  ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg4   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg4   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg5   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg5   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg6   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg6   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg7   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg7   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg8   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg8   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg9   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_datain_reg9   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_memory_reg0   ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_we_reg        ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a0~porta_we_reg        ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a100~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a100~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a101~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a101~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a102~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a102~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a103~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a103~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a104~porta_memory_reg0 ;
; 10.568 ; 12.695       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_1t14:auto_generated|ram_block1a104~porta_memory_reg0 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                                                                                                   ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg1  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg10 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg11 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg12 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg13 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg14 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg15 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg2  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg3  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg4  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg5  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg6  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg7  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg8  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg9  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_we_reg       ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a10~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a11~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a12~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a13~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a14~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a15~porta_memory_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a1~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a2~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a3~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a4~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a5~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a6~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a7~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a8~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_HI_rtl_0|altsyncram_sa41:auto_generated|ram_block1a9~porta_memory_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg0 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg1 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg2 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg3 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg4 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg5 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg6 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_address_reg7 ;
; 13.498 ; 15.625       ; 2.127          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 13.498 ; 15.625       ; 2.127          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|altsyncram:F_PALETTE_LO_rtl_0|altsyncram_sa41:auto_generated|ram_block1a0~porta_datain_reg0  ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0'                                                                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                          ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------+
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|BIT_CLK_SM               ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|BIT_CLK_SM               ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|SAMPLE_CLK_SM            ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|SAMPLE_CLK_SM            ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[0]  ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[0]  ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[1]  ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[1]  ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[2]  ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[2]  ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[3]  ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[3]  ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[4]  ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:BITRATE_CNT[4]  ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[1]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[1]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[2]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[2]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[3]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[3]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[4]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[4]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[5]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[5]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[6]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[6]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[7]       ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; FDMA_TOP_SOC:I_DMA|PCM_CTRL:I_PCM_CTRL|\P_SNCLK:DIV128[7]       ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|DE_I                ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|DE_I                ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|EVENn_ODD_I         ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|EVENn_ODD_I         ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[0]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[1]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[2]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[3]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[3]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[4]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[4]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[5]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[5]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[6]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[7]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|HHC[8]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[0]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[0]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[1]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[1]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[2]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[2]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[3]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[3]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[4]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[4]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[5]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[5]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[6]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[6]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[7]      ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|PALETTE_SEL[7]      ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_REQ            ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_REQ            ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_STRB           ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|SHFT_STRB           ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Fall       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I         ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Fall       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_ACK_I         ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_REQ_I         ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VDATA_REQ_I         ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[0]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]             ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[10]             ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[1]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[2]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[3]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[4]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[5]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[6]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[6]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[7]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[8]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]              ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VFC[9]              ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]  ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][0]  ;
; 18.531 ; 19.531       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10] ;
; 18.531 ; 19.531       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; VIDEL_TOP:I_VIDEO|VIDEO_CORE:I_VIDEO_SYSTEM|VIDEO_BUFFER[0][10] ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0'                                                                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1'                                                                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                      ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[0]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[10]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[11]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[12]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[13]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[14]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[15]~_Duplicate_2 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[16]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[17]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[18]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[19]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]               ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_1  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[1]~_Duplicate_2  ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[20]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[21]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[22]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[23]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[24]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[25]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[26]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[27]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]              ;
; 29.231 ; 31.250       ; 2.019          ; High Pulse Width ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
; 29.231 ; 31.250       ; 2.019          ; Low Pulse Width  ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; Rise       ; WF68K30L_TOP:I_CPU|WF68K30L_ALU:I_ALU|OP1[28]~_Duplicate_1 ;
+--------+--------------+----------------+------------------+------------------------------------------------------------+------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL1'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0                            ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS                                 ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]                      ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK                           ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|inclk[0]                 ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; CLK_PLL1~clkctrl|outclk                   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_ARESET|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_FAULT~reg0|clk                        ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; PLL_LOCKS|clk                             ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[0]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[1]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[2]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[3]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_LOCK_FLT:TMP[4]|clk                  ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL1 ; Rise       ; \PLL_RESET:LOCK|clk                       ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL1 ; Rise       ; CLK_PLL1                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2'                                                                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                    ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0                                             ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]                                ;
; 30.250 ; 31.250       ; 1.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 30.250 ; 31.250       ; 1.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]                                ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; CLK_2M0|clk                                         ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; I_AUXCLOCKS|altpll_component|_clk2~clkctrl|outclk   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[0]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 ; Rise       ; \P_AUX_CLOCKS:TMP[1]|clk                            ;
+--------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLK_PLL2'                                                                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; CLK_PLL2|combout                          ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|clk[2]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CLK_PLL2 ; Rise       ; I_AUXCLOCKS|altpll_component|pll|inclk[0] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CLK_PLL2 ; Rise       ; CLK_PLL2                                  ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CRT_PIN4_CLK1'                                                                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock         ; Clock Edge ; Target                                    ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1|combout                     ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[0]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|clk[1]   ;
; 31.250 ; 31.250       ; 0.000          ; High Pulse Width ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 31.250 ; 31.250       ; 0.000          ; Low Pulse Width  ; CRT_PIN4_CLK1 ; Rise       ; I_SYSCLOCKS|altpll_component|pll|inclk[1] ;
; 60.120 ; 62.500       ; 2.380          ; Port Rate        ; CRT_PIN4_CLK1 ; Rise       ; CRT_PIN4_CLK1                             ;
+--------+--------------+----------------+------------------+---------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'altera_reserved_tck'                                                       ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock               ; Clock Edge ; Target              ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+
; 97.778 ; 100.000      ; 2.222          ; Port Rate ; altera_reserved_tck ; Rise       ; altera_reserved_tck ;
+--------+--------------+----------------+-----------+---------------------+------------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.608 ; -0.608 ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]         ; CLK_PLL1      ; 11.815 ; 11.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 11.329 ; 11.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 11.815 ; 11.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 11.074 ; 11.074 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 11.379 ; 11.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 11.560 ; 11.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 14.124 ; 14.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 3.984  ; 3.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 5.337  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 7.766  ; 7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 7.623  ; 7.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 7.628  ; 7.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 7.016  ; 7.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 7.978  ; 7.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 8.923  ; 8.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 9.931  ; 9.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 7.387  ; 7.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 15.339 ; 15.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.708  ; 8.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.577  ; 8.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 15.339 ; 15.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 7.961  ; 7.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.427  ; 7.427  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.367  ; 7.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 7.167  ; 7.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.264  ; 6.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 6.265  ; 6.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 6.511  ; 6.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.005  ; 6.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 7.239  ; 7.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 6.793  ; 6.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 6.944  ; 6.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 7.961  ; 7.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.198  ; 7.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.769  ; 5.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.780  ; 5.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 3.743  ; 3.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 8.244  ; 8.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 14.705 ; 14.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 14.705 ; 14.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 14.510 ; 14.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 14.483 ; 14.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 5.486  ; 5.486  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 2.706  ; 2.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 6.091  ; 6.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 5.244  ; 5.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 4.814  ; 4.814  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 8.810  ; 8.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 4.030  ; 4.030  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.927  ; 8.927  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 4.099  ; 4.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 13.683 ; 13.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 7.788  ; 7.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.375  ; 9.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.549  ; 7.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.498  ; 7.498  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.347  ; 7.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.740  ; 7.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 9.375  ; 9.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.070  ; 8.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.139  ; 9.139  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 8.278  ; 8.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 3.347  ; 3.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.518  ; 9.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.064  ; 9.064  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.494  ; 8.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.281  ; 8.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.204  ; 8.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.518  ; 9.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.387  ; 7.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.375  ; 8.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.938  ; 7.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.713  ; 7.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.396  ; 8.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.058  ; 9.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.036  ; 8.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.915  ; 8.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.077  ; 9.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 1.669  ; 1.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 3.718  ; 3.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 14.598 ; 14.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 5.179  ; 5.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 4.443  ; 4.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 5.245  ; 5.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.245  ; 5.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 5.165  ; 5.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 5.028  ; 5.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 4.806  ; 4.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 5.016  ; 5.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 5.016  ; 5.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 4.941  ; 4.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 4.929  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 5.181  ; 5.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 5.369  ; 5.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 5.010  ; 5.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 5.075  ; 5.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 4.658  ; 4.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 7.190  ; 7.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 4.362  ; 4.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 9.580  ; 9.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 4.519  ; 4.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 4.824  ; 4.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 4.986  ; 4.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 4.986  ; 4.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 4.850  ; 4.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 4.627  ; 4.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 3.689  ; 3.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 3.845  ; 3.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 3.863  ; 3.863  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 14.477 ; 14.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 5.787  ; 5.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 11.629 ; 11.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 11.143 ; 11.143 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 11.629 ; 11.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 10.888 ; 10.888 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 11.193 ; 11.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 11.374 ; 11.374 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 13.788 ; 13.788 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 3.964  ; 3.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 4.232  ; 4.232  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.780  ; 3.780  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 3.941  ; 3.941  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 7.858  ; 7.858  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 7.430  ; 7.430  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 7.423  ; 7.423  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 7.377  ; 7.377  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 7.858  ; 7.858  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 7.197  ; 7.197  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.699  ; 6.699  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 7.723  ; 7.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 7.815  ; 7.815  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 8.723  ; 8.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 9.574  ; 9.574  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 15.095 ; 15.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.337  ; 8.337  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.220  ; 8.220  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 15.095 ; 15.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 7.878  ; 7.878  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.091  ; 7.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.236  ; 7.236  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 7.130  ; 7.130  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.981  ; 6.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 5.833  ; 5.833  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 5.948  ; 5.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 6.091  ; 6.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 5.842  ; 5.842  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.973  ; 6.973  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 7.237  ; 7.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 6.530  ; 6.530  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 6.700  ; 6.700  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 7.878  ; 7.878  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.116  ; 7.116  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.412  ; 5.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 5.409  ; 5.409  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 7.935  ; 7.935  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 14.461 ; 14.461 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 14.461 ; 14.461 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 14.266 ; 14.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 14.239 ; 14.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 3.421  ; 3.421  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 3.996  ; 3.996  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 8.648  ; 8.648  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.765  ; 8.765  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 13.347 ; 13.347 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 7.497  ; 7.497  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 8.944  ; 8.944  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.258  ; 7.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.298  ; 7.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.110  ; 7.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.628  ; 7.628  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 8.944  ; 8.944  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 7.753  ; 7.753  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 8.719  ; 8.719  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.907  ; 7.907  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.098  ; 9.098  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 8.728  ; 8.728  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.294  ; 8.294  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 7.817  ; 7.817  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.095  ; 8.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 7.643  ; 7.643  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 7.887  ; 7.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.098  ; 9.098  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.224  ; 7.224  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.084  ; 8.084  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 7.936  ; 7.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 7.450  ; 7.450  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.152  ; 8.152  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 8.975  ; 8.975  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 7.954  ; 7.954  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.558  ; 8.558  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 8.706  ; 8.706  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 14.412 ; 14.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 7.355  ; 7.355  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 14.233 ; 14.233 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 11.815 ; 11.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 11.329 ; 11.329 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 11.815 ; 11.815 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 11.074 ; 11.074 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 11.379 ; 11.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 11.560 ; 11.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.124 ; 14.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 3.984  ; 3.984  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 5.337  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 7.766  ; 7.766  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.623  ; 7.623  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.614  ; 7.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 8.044  ; 8.044  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 7.628  ; 7.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 7.016  ; 7.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 8.143  ; 8.143  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.978  ; 7.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.923  ; 8.923  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 9.931  ; 9.931  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 7.387  ; 7.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 15.339 ; 15.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.708  ; 8.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.577  ; 8.577  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 15.339 ; 15.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.961  ; 7.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.427  ; 7.427  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.367  ; 7.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.167  ; 7.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.264  ; 6.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.265  ; 6.265  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.511  ; 6.511  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.005  ; 6.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.239  ; 7.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.793  ; 6.793  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.944  ; 6.944  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.961  ; 7.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.198  ; 7.198  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.769  ; 5.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.780  ; 5.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 3.743  ; 3.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 8.244  ; 8.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.705 ; 14.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.705 ; 14.705 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.510 ; 14.510 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.483 ; 14.483 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 5.486  ; 5.486  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 2.706  ; 2.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 6.091  ; 6.091  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 5.244  ; 5.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 4.814  ; 4.814  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.810  ; 8.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 4.030  ; 4.030  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.927  ; 8.927  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 4.099  ; 4.099  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.683 ; 13.683 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.788  ; 7.788  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.375  ; 9.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.549  ; 7.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.498  ; 7.498  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.347  ; 7.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.740  ; 7.740  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 9.375  ; 9.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.070  ; 8.070  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.139  ; 9.139  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 8.278  ; 8.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 3.347  ; 3.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.518  ; 9.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 9.064  ; 9.064  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.494  ; 8.494  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.054  ; 8.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.281  ; 8.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 8.074  ; 8.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 8.204  ; 8.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 9.518  ; 9.518  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.387  ; 7.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.375  ; 8.375  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.938  ; 7.938  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.713  ; 7.713  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.396  ; 8.396  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 9.058  ; 9.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.036  ; 8.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.915  ; 8.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.077  ; 9.077  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 1.669  ; 1.669  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.718  ; 3.718  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 14.598 ; 14.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 5.179  ; 5.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 4.443  ; 4.443  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 5.245  ; 5.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.245  ; 5.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 5.165  ; 5.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 5.028  ; 5.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 4.806  ; 4.806  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 5.016  ; 5.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 5.016  ; 5.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 4.941  ; 4.941  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 4.929  ; 4.929  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 5.181  ; 5.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 5.369  ; 5.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 5.010  ; 5.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 5.075  ; 5.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 4.658  ; 4.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 7.190  ; 7.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 4.362  ; 4.362  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.580  ; 9.580  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 4.519  ; 4.519  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 4.824  ; 4.824  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 4.986  ; 4.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 4.986  ; 4.986  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 4.850  ; 4.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 4.627  ; 4.627  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 3.689  ; 3.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 3.845  ; 3.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 3.863  ; 3.863  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 14.477 ; 14.477 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 5.787  ; 5.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 11.629 ; 11.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 11.143 ; 11.143 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 11.629 ; 11.629 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 10.888 ; 10.888 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 11.193 ; 11.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 11.374 ; 11.374 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 13.788 ; 13.788 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 3.964  ; 3.964  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 4.232  ; 4.232  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.780  ; 3.780  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 3.941  ; 3.941  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 7.858  ; 7.858  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 7.430  ; 7.430  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.423  ; 7.423  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.377  ; 7.377  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 7.858  ; 7.858  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 7.197  ; 7.197  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.699  ; 6.699  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 7.723  ; 7.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 7.815  ; 7.815  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 8.723  ; 8.723  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 9.574  ; 9.574  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 15.095 ; 15.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.337  ; 8.337  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.220  ; 8.220  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 15.095 ; 15.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 7.878  ; 7.878  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.091  ; 7.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.236  ; 7.236  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.130  ; 7.130  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.981  ; 6.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.833  ; 5.833  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 5.948  ; 5.948  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.091  ; 6.091  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.842  ; 5.842  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.973  ; 6.973  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.237  ; 7.237  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.530  ; 6.530  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.700  ; 6.700  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 7.878  ; 7.878  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.116  ; 7.116  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.412  ; 5.412  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.409  ; 5.409  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 7.935  ; 7.935  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.461 ; 14.461 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.461 ; 14.461 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.266 ; 14.266 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.239 ; 14.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 3.421  ; 3.421  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 3.996  ; 3.996  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.648  ; 8.648  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.765  ; 8.765  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.347 ; 13.347 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.497  ; 7.497  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 8.944  ; 8.944  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.258  ; 7.258  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.298  ; 7.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.110  ; 7.110  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.628  ; 7.628  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 8.944  ; 8.944  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 7.753  ; 7.753  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 8.719  ; 8.719  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.907  ; 7.907  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.098  ; 9.098  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 8.728  ; 8.728  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.294  ; 8.294  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 7.817  ; 7.817  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.095  ; 8.095  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 7.643  ; 7.643  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 7.887  ; 7.887  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 9.098  ; 9.098  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.224  ; 7.224  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.084  ; 8.084  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 7.936  ; 7.936  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 7.450  ; 7.450  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.152  ; 8.152  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 8.975  ; 8.975  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 7.954  ; 7.954  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.558  ; 8.558  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 8.706  ; 8.706  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 14.412 ; 14.412 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 7.355  ; 7.355  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 14.233 ; 14.233 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CLK_PLL1      ; 12.138 ; 12.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[1]        ; CLK_PLL1      ; 11.652 ; 11.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[2]        ; CLK_PLL1      ; 12.138 ; 12.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[3]        ; CLK_PLL1      ; 11.397 ; 11.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[4]        ; CLK_PLL1      ; 11.702 ; 11.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[5]        ; CLK_PLL1      ; 11.883 ; 11.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 14.157 ; 14.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 8.367  ; 8.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 7.799  ; 7.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 7.932  ; 7.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 8.367  ; 8.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 7.802  ; 7.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 7.051  ; 7.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 8.318  ; 8.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 8.245  ; 8.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 9.232  ; 9.232  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 8.815  ; 8.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 8.290  ; 8.290  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 8.009  ; 8.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 7.460  ; 7.460  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 7.745  ; 7.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 7.736  ; 7.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 6.438  ; 6.438  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 6.300  ; 6.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 6.686  ; 6.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 6.272  ; 6.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 7.454  ; 7.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 7.591  ; 7.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 7.092  ; 7.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.995  ; 6.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 8.009  ; 8.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 7.185  ; 7.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.482  ; 5.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 5.887  ; 5.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 14.756 ; 14.756 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 14.756 ; 14.756 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 14.561 ; 14.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 14.534 ; 14.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 8.845  ; 8.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 8.962  ; 8.962  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 13.716 ; 13.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 7.978  ; 7.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 9.549  ; 9.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; 7.716  ; 7.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; 8.063  ; 8.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; 9.549  ; 9.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; 8.105  ; 8.105  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; 9.314  ; 9.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; 8.385  ; 8.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Xn         ; CLK_PLL1      ; 2.072  ; 2.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Yn         ; CLK_PLL1      ; 2.155  ; 2.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Xn         ; CLK_PLL1      ; 2.002  ; 2.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Yn         ; CLK_PLL1      ; 2.996  ; 2.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PENn           ; CLK_PLL1      ; 3.536  ; 3.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 9.693  ; 9.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 9.097  ; 9.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 8.803  ; 8.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 8.423  ; 8.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 8.239  ; 8.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 9.693  ; 9.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 8.565  ; 8.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 8.290  ; 8.290  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 8.012  ; 8.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 8.447  ; 8.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 9.106  ; 9.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 8.023  ; 8.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 8.628  ; 8.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 9.184  ; 9.184  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 14.921 ; 14.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 9.028  ; 9.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 14.528 ; 14.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 12.138 ; 12.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 11.652 ; 11.652 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 12.138 ; 12.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 11.397 ; 11.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 11.702 ; 11.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 11.883 ; 11.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.157 ; 14.157 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 8.367  ; 8.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 7.799  ; 7.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 7.932  ; 7.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 7.983  ; 7.983  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 8.367  ; 8.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 7.802  ; 7.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 7.051  ; 7.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 8.318  ; 8.318  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 8.245  ; 8.245  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 9.232  ; 9.232  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 9.644  ; 9.644  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 8.815  ; 8.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 8.290  ; 8.290  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 15.390 ; 15.390 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 8.009  ; 8.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.460  ; 7.460  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.745  ; 7.745  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 7.736  ; 7.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 7.490  ; 7.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.438  ; 6.438  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.300  ; 6.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.686  ; 6.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.272  ; 6.272  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 7.454  ; 7.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 7.591  ; 7.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 7.092  ; 7.092  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.995  ; 6.995  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 8.009  ; 8.009  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.185  ; 7.185  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.482  ; 5.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.887  ; 5.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 14.756 ; 14.756 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 14.756 ; 14.756 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 14.561 ; 14.561 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 14.534 ; 14.534 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 8.845  ; 8.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 8.962  ; 8.962  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.716 ; 13.716 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 7.978  ; 7.978  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 9.549  ; 9.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.739  ; 7.739  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.807  ; 7.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 7.716  ; 7.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 8.063  ; 8.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 9.549  ; 9.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 8.105  ; 8.105  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 9.314  ; 9.314  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 8.385  ; 8.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 2.072  ; 2.072  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 2.155  ; 2.155  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 2.002  ; 2.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 2.996  ; 2.996  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 3.536  ; 3.536  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 9.693  ; 9.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 9.097  ; 9.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 8.803  ; 8.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 8.423  ; 8.423  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 8.604  ; 8.604  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 8.248  ; 8.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 8.239  ; 8.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 9.693  ; 9.693  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 7.654  ; 7.654  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 8.565  ; 8.565  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 8.290  ; 8.290  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 8.012  ; 8.012  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 8.447  ; 8.447  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 9.106  ; 9.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 8.023  ; 8.023  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 8.628  ; 8.628  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 9.184  ; 9.184  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 14.921 ; 14.921 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 9.028  ; 9.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 14.528 ; 14.528 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.744  ; 0.744  ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]         ; CLK_PLL1      ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; -4.719 ; -4.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; -5.054 ; -5.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; -4.801 ; -4.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; -4.755 ; -4.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.864 ; -3.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.764 ; -3.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.540 ; -3.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.377 ; -3.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.567 ; -3.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.394 ; -3.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.391 ; -3.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.285 ; -3.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -4.560 ; -4.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -4.614 ; -4.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -5.308 ; -5.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -6.978 ; -6.978 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -6.877 ; -6.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.570 ; -4.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.565 ; -4.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.621 ; -4.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.529 ; -4.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.365 ; -4.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.791 ; -4.791 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.379 ; -4.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.069 ; -4.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -3.623 ; -3.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.931 ; -4.931 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.439 ; -4.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -3.309 ; -3.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.338 ; -1.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -3.849 ; -3.849 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -4.047 ; -4.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -5.086 ; -5.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -3.910 ; -3.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -5.203 ; -5.203 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.979 ; -3.979 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.345 ; -4.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -3.460 ; -3.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.631 ; -5.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -5.720 ; -5.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.004 ; -6.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.181 ; -7.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -5.786 ; -5.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.735 ; -6.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.100 ; -6.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.989 ; -3.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.260 ; -4.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.151 ; -4.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.064 ; -4.064 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.180 ; -4.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.054 ; -4.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.119 ; -4.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.162 ; -4.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.956 ; -3.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.549 ; -1.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -3.598 ; -3.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.693 ; -4.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.517 ; -3.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.907 ; -3.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.715 ; -3.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.879 ; -3.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.941 ; -3.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -4.288 ; -4.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -4.476 ; -4.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -4.117 ; -4.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.929 ; -3.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.706 ; -3.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.465 ; -4.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -4.121 ; -4.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.136 ; -4.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.451 ; -4.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -4.280 ; -4.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -4.141 ; -4.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -3.448 ; -3.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -3.626 ; -3.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -5.853 ; -5.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; -5.554 ; -5.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; -5.937 ; -5.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; -5.355 ; -5.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; -5.574 ; -5.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -4.513 ; -4.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.844 ; -3.844 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -4.112 ; -4.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.660 ; -3.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.821 ; -3.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -6.366 ; -6.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -6.370 ; -6.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -6.381 ; -6.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -6.936 ; -6.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -7.138 ; -7.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -7.151 ; -7.151 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -7.637 ; -7.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -8.182 ; -8.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.537 ; -7.537 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.494 ; -7.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.737 ; -4.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.947 ; -4.947 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.895 ; -4.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.956 ; -4.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -5.506 ; -5.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -5.178 ; -5.178 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -5.820 ; -5.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -5.428 ; -5.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.987 ; -4.987 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.715 ; -4.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -5.053 ; -5.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.686 ; -4.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.609 ; -4.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.223 ; -4.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.336 ; -5.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.141 ; -5.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -3.301 ; -3.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.876 ; -3.876 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -7.481 ; -7.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.598 ; -7.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -5.641 ; -5.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -6.349 ; -6.349 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.110 ; -6.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.632 ; -6.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.850 ; -7.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.460 ; -6.460 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.352 ; -7.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.804 ; -6.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.568 ; -7.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.452 ; -7.452 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.821 ; -6.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.173 ; -7.173 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.766 ; -6.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.875 ; -6.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.481 ; -8.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.318 ; -7.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.154 ; -7.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.833 ; -6.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.370 ; -7.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -8.238 ; -8.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.202 ; -7.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.832 ; -7.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.906 ; -7.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.678 ; -5.678 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -6.661 ; -6.661 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -4.719 ; -4.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -5.054 ; -5.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -4.801 ; -4.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -4.755 ; -4.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.864 ; -3.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.764 ; -3.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.540 ; -3.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.377 ; -3.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.567 ; -3.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.394 ; -3.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.391 ; -3.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.285 ; -3.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -4.560 ; -4.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -4.614 ; -4.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -5.308 ; -5.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -6.978 ; -6.978 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -6.877 ; -6.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.570 ; -4.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.565 ; -4.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.621 ; -4.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.529 ; -4.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.365 ; -4.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.791 ; -4.791 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.379 ; -4.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.069 ; -4.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -3.623 ; -3.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.931 ; -4.931 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.439 ; -4.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -3.309 ; -3.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.338 ; -1.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -3.849 ; -3.849 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -4.047 ; -4.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -5.086 ; -5.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -3.910 ; -3.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -5.203 ; -5.203 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.979 ; -3.979 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.345 ; -4.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -3.460 ; -3.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.631 ; -5.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -5.720 ; -5.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.004 ; -6.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.181 ; -7.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -5.786 ; -5.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.735 ; -6.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.100 ; -6.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.989 ; -3.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.260 ; -4.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.151 ; -4.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.064 ; -4.064 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.180 ; -4.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.054 ; -4.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.119 ; -4.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.162 ; -4.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.956 ; -3.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.549 ; -1.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -3.598 ; -3.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.693 ; -4.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.517 ; -3.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.907 ; -3.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.715 ; -3.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.879 ; -3.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.941 ; -3.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -4.288 ; -4.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -4.476 ; -4.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -4.117 ; -4.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.929 ; -3.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.706 ; -3.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.465 ; -4.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -4.121 ; -4.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.136 ; -4.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.451 ; -4.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -4.280 ; -4.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -4.141 ; -4.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -3.448 ; -3.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -3.626 ; -3.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.853 ; -5.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -5.554 ; -5.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -5.937 ; -5.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -5.355 ; -5.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -5.574 ; -5.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.513 ; -4.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.844 ; -3.844 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -4.112 ; -4.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.660 ; -3.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.821 ; -3.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.366 ; -6.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.370 ; -6.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -6.381 ; -6.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.936 ; -6.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -7.138 ; -7.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -7.151 ; -7.151 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.637 ; -7.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -8.182 ; -8.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.537 ; -7.537 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.494 ; -7.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.737 ; -4.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.947 ; -4.947 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.895 ; -4.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.956 ; -4.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -5.506 ; -5.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -5.178 ; -5.178 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -5.820 ; -5.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -5.428 ; -5.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.987 ; -4.987 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.715 ; -4.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -5.053 ; -5.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.686 ; -4.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.609 ; -4.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.223 ; -4.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.336 ; -5.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.141 ; -5.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -3.301 ; -3.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.876 ; -3.876 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.481 ; -7.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.598 ; -7.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.641 ; -5.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.349 ; -6.349 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.110 ; -6.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.632 ; -6.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.850 ; -7.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.460 ; -6.460 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.352 ; -7.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.804 ; -6.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.568 ; -7.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.452 ; -7.452 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.821 ; -6.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.173 ; -7.173 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.766 ; -6.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.875 ; -6.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.481 ; -8.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.318 ; -7.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.154 ; -7.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.833 ; -6.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.370 ; -7.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -8.238 ; -8.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.202 ; -7.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.832 ; -7.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.906 ; -7.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.678 ; -5.678 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -6.661 ; -6.661 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CLK_PLL1      ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[1]        ; CLK_PLL1      ; -6.743 ; -6.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[2]        ; CLK_PLL1      ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[3]        ; CLK_PLL1      ; -6.608 ; -6.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[4]        ; CLK_PLL1      ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[5]        ; CLK_PLL1      ; -6.628 ; -6.628 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; -6.288 ; -6.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; -6.266 ; -6.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; -6.465 ; -6.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; -6.907 ; -6.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; -6.388 ; -6.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; -6.575 ; -6.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; -6.781 ; -6.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -7.425 ; -7.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -7.619 ; -7.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.205 ; -7.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.971 ; -4.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -5.275 ; -5.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -5.032 ; -5.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.866 ; -4.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -5.024 ; -5.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -5.020 ; -5.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.943 ; -4.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -5.562 ; -5.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; -5.128 ; -5.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; -4.805 ; -4.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; -4.579 ; -4.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -4.585 ; -4.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -4.638 ; -4.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.539 ; -7.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.698 ; -4.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -6.271 ; -6.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.032 ; -6.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.159 ; -6.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.453 ; -6.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.609 ; -7.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; -5.986 ; -5.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.063 ; -7.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.434 ; -6.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Xn         ; CLK_PLL1      ; -1.607 ; -1.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Yn         ; CLK_PLL1      ; -1.690 ; -1.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Xn         ; CLK_PLL1      ; -1.473 ; -1.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Yn         ; CLK_PLL1      ; -2.531 ; -2.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PENn           ; CLK_PLL1      ; -2.352 ; -2.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.884 ; -3.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.976 ; -3.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.104 ; -4.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.004 ; -4.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.307 ; -4.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.081 ; -4.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.048 ; -4.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.878 ; -3.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.161 ; -4.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.076 ; -4.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.939 ; -3.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -4.748 ; -4.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -5.231 ; -5.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -6.743 ; -6.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -6.608 ; -6.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -6.628 ; -6.628 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.288 ; -6.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.266 ; -6.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -6.465 ; -6.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.907 ; -6.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.388 ; -6.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -6.575 ; -6.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -6.781 ; -6.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.425 ; -7.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -7.619 ; -7.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.205 ; -7.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.971 ; -4.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -5.275 ; -5.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -5.032 ; -5.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.866 ; -4.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -5.024 ; -5.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.943 ; -4.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -5.562 ; -5.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -5.128 ; -5.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.805 ; -4.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.579 ; -4.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.585 ; -4.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.638 ; -4.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.539 ; -7.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.698 ; -4.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.271 ; -6.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.032 ; -6.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.159 ; -6.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.453 ; -6.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.609 ; -7.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -5.986 ; -5.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.063 ; -7.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.434 ; -6.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.607 ; -1.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.690 ; -1.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -1.473 ; -1.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -2.531 ; -2.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -2.352 ; -2.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.884 ; -3.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.976 ; -3.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.104 ; -4.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.004 ; -4.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.307 ; -4.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.081 ; -4.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.048 ; -4.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.878 ; -3.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.161 ; -4.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.076 ; -4.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.939 ; -3.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.748 ; -4.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.231 ; -5.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; PLL_FAULT      ; CLK_PLL1      ; 3.910  ; 3.910  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 4.222  ; 4.222  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_RDn       ; CLK_PLL1      ; 12.031 ; 12.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 12.021 ; 12.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 9.843  ; 9.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 8.606  ; 8.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 7.810  ; 7.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 8.156  ; 8.156  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 7.958  ; 7.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 8.134  ; 8.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 8.244  ; 8.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 8.433  ; 8.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 8.748  ; 8.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 8.390  ; 8.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 8.953  ; 8.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 8.641  ; 8.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 8.458  ; 8.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 8.201  ; 8.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 9.843  ; 9.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 8.935  ; 8.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 9.101  ; 9.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 9.098  ; 9.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 9.036  ; 9.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 9.402  ; 9.402  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 9.246  ; 9.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 9.762  ; 9.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 9.177  ; 9.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 5.850  ; 5.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 4.525  ; 4.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 4.468  ; 4.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 11.335 ; 11.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 11.066 ; 11.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 14.726 ; 14.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 14.201 ; 14.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 13.971 ; 13.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 13.747 ; 13.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 14.397 ; 14.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 13.925 ; 13.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 13.574 ; 13.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 14.726 ; 14.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 13.784 ; 13.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 3.653  ; 3.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 4.857  ; 4.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL1      ; 9.764  ; 9.764  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL1      ; 9.176  ; 9.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL1      ; 9.764  ; 9.764  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL1      ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL1      ; 9.170  ; 9.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL1      ; 11.182 ; 11.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL1      ; 11.182 ; 11.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL1      ; 9.845  ; 9.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL1      ; 9.539  ; 9.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL1      ; 9.781  ; 9.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL1      ; 8.033  ; 8.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL1      ; 10.526 ; 10.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL1      ; 8.813  ; 8.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL1      ; 10.526 ; 10.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL1      ; 8.539  ; 8.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL1      ; 8.906  ; 8.906  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 19.690 ; 19.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 18.447 ; 18.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 18.342 ; 18.342 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 17.938 ; 17.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 18.003 ; 18.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 17.323 ; 17.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 18.983 ; 18.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 17.671 ; 17.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 17.860 ; 17.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 17.418 ; 17.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 18.115 ; 18.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 18.133 ; 18.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 19.690 ; 19.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 17.730 ; 17.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 18.439 ; 18.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 17.786 ; 17.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 17.820 ; 17.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 2.825  ; 2.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 2.289  ; 2.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 2.716  ; 2.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 8.181  ; 8.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 2.599  ; 2.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 2.512  ; 2.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 2.229  ; 2.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 2.097  ; 2.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 9.206  ; 9.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 9.191  ; 9.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 12.238 ; 12.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 12.736 ; 12.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 3.567  ; 3.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 2.918  ; 2.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.746  ; 3.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.849  ; 3.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 8.381  ; 8.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 11.581 ; 11.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 11.251 ; 11.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 11.388 ; 11.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 11.296 ; 11.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 10.997 ; 10.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 12.168 ; 12.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 11.194 ; 11.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 12.101 ; 12.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 12.073 ; 12.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 10.915 ; 10.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.906  ; 3.906  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 4.140  ; 4.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 4.140  ; 4.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.770  ; 3.770  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.683  ; 3.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 3.569  ; 3.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 8.258  ; 8.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.221  ; 3.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.136  ; 3.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.990  ; 2.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.153  ; 3.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 2.896  ; 2.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 2.977  ; 2.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 3.059  ; 3.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 11.613 ; 11.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 11.011 ; 11.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 11.056 ; 11.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 11.484 ; 11.484 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 11.027 ; 11.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 10.936 ; 10.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 11.613 ; 11.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 10.644 ; 10.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 11.387 ; 11.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 10.614 ; 10.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 8.935  ; 8.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 8.767  ; 8.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 8.596  ; 8.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 8.684  ; 8.684  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 10.496 ; 10.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 9.178  ; 9.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 10.496 ; 10.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 10.078 ; 10.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 9.666  ; 9.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 16.626 ; 16.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 17.427 ; 17.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.095 ; 17.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 17.100 ; 17.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.452 ; 17.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.642 ; 17.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 17.502 ; 17.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 17.542 ; 17.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 17.029 ; 17.029 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.486 ; 17.486 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.055 ; 18.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 17.794 ; 17.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 17.290 ; 17.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 16.902 ; 16.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 16.778 ; 16.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 10.440 ; 10.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 10.013 ; 10.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 10.596 ; 10.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 10.003 ; 10.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 10.862 ; 10.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 10.704 ; 10.704 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_WEn        ; CLK_PLL1      ; 5.108  ; 5.108  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 3.550  ; 3.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 11.220 ; 11.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 12.051 ; 12.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 11.412 ; 11.412 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 12.519 ; 12.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 12.327 ; 12.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 11.900 ; 11.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 12.754 ; 12.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 4.754  ; 4.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.457  ; 3.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.738  ; 3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 3.174  ; 3.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 4.111  ; 4.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.625  ; 2.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.653  ; 2.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.765  ; 2.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.197  ; 2.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.882  ; 2.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.181  ; 2.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 3.199  ; 3.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 3.074  ; 3.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 2.347  ; 2.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 3.179  ; 3.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 4.058  ; 4.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 3.790  ; 3.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 2.955  ; 2.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 2.719  ; 2.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 3.744  ; 3.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 3.309  ; 3.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.692  ; 3.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.744  ; 3.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 8.200  ; 8.200  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 2.671  ; 2.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 5.839  ; 5.839  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 7.249  ; 7.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 7.524  ; 7.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 7.283  ; 7.283  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 7.273  ; 7.273  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 5.151  ; 5.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 6.587  ; 6.587  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 6.318  ; 6.318  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 9.978  ; 9.978  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 9.453  ; 9.453  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 9.223  ; 9.223  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 8.999  ; 8.999  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 9.649  ; 9.649  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 9.177  ; 9.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 8.826  ; 8.826  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 9.978  ; 9.978  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 9.036  ; 9.036  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 14.964 ; 14.964 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 13.699 ; 13.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 13.616 ; 13.616 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 13.237 ; 13.237 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 13.277 ; 13.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 12.768 ; 12.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 14.257 ; 14.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 13.116 ; 13.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 13.218 ; 13.218 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 12.858 ; 12.858 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 13.389 ; 13.389 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 13.407 ; 13.407 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 14.964 ; 14.964 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 13.004 ; 13.004 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 13.691 ; 13.691 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 12.989 ; 12.989 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 13.265 ; 13.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 4.306  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 8.077  ; 8.077  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 8.575  ; 8.575  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 7.064  ; 7.064  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 6.734  ; 6.734  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 6.871  ; 6.871  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 6.779  ; 6.779  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 6.480  ; 6.480  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 7.651  ; 7.651  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 6.446  ; 6.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 7.353  ; 7.353  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 7.325  ; 7.325  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 6.167  ; 6.167  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 6.863  ; 6.863  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 7.272  ; 7.272  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 7.526  ; 7.526  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 7.514  ; 7.514  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 7.293  ; 7.293  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 7.905  ; 7.905  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.954  ; 6.954  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 7.706  ; 7.706  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.592  ; 6.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.991  ; 4.991  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 4.512  ; 4.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.082  ; 4.082  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 4.108  ; 4.108  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 5.467  ; 5.515  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.548  ; 4.548  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 5.467  ; 5.515  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 7.170  ; 7.170  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 6.756  ; 6.756  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 13.544 ; 13.544 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 11.878 ; 11.878 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 12.701 ; 12.701 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.394 ; 12.394 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 12.374 ; 12.374 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 12.897 ; 12.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 12.916 ; 12.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 12.947 ; 12.947 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 12.900 ; 12.900 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 12.469 ; 12.469 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 12.760 ; 12.760 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 13.544 ; 13.544 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.068 ; 13.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 12.542 ; 12.542 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.105 ; 12.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 12.223 ; 12.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 8.925  ; 8.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 8.344  ; 8.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 9.081  ; 9.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 8.334  ; 8.334  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 6.135  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 6.025  ; 5.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 6.449  ; 6.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 7.280  ; 7.232  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 7.251  ; 7.251  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 7.831  ; 7.783  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 7.639  ; 7.591  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 7.129  ; 7.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 8.066  ; 8.018  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 6.803  ; 6.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 12.031 ; 12.031 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 12.021 ; 12.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 9.843  ; 9.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 8.606  ; 8.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 7.810  ; 7.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 8.156  ; 8.156  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 7.958  ; 7.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 8.134  ; 8.134  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 8.244  ; 8.244  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 8.433  ; 8.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 8.430  ; 8.430  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 8.748  ; 8.748  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 8.390  ; 8.390  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 8.953  ; 8.953  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 8.641  ; 8.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 8.458  ; 8.458  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 8.201  ; 8.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 9.843  ; 9.843  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 8.935  ; 8.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 9.101  ; 9.101  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 9.098  ; 9.098  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 9.036  ; 9.036  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 9.402  ; 9.402  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 9.246  ; 9.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 9.762  ; 9.762  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 9.177  ; 9.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 5.850  ; 5.850  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 4.525  ; 4.525  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 4.468  ; 4.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 11.335 ; 11.335 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 11.066 ; 11.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 14.726 ; 14.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 14.201 ; 14.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 13.971 ; 13.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 13.747 ; 13.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 14.397 ; 14.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 13.925 ; 13.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 13.574 ; 13.574 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 14.726 ; 14.726 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 13.784 ; 13.784 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 3.653  ; 3.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 4.857  ; 4.857  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 9.764  ; 9.764  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 9.176  ; 9.176  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 9.764  ; 9.764  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 8.300  ; 8.300  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 9.170  ; 9.170  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 11.182 ; 11.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 11.182 ; 11.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 9.845  ; 9.845  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 9.539  ; 9.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 9.781  ; 9.781  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 8.033  ; 8.033  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 10.526 ; 10.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 8.813  ; 8.813  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 10.526 ; 10.526 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 8.539  ; 8.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 8.906  ; 8.906  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 19.690 ; 19.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 18.447 ; 18.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 18.342 ; 18.342 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 17.938 ; 17.938 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 18.003 ; 18.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 17.323 ; 17.323 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 18.983 ; 18.983 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 17.671 ; 17.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 17.860 ; 17.860 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 17.418 ; 17.418 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 18.115 ; 18.115 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 18.133 ; 18.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 19.690 ; 19.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 17.730 ; 17.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 18.439 ; 18.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 17.786 ; 17.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 17.820 ; 17.820 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 2.825  ; 2.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 2.289  ; 2.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 2.716  ; 2.716  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 8.181  ; 8.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 8.202  ; 8.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 8.532  ; 8.532  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 2.599  ; 2.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 2.512  ; 2.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 2.229  ; 2.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 2.097  ; 2.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 9.206  ; 9.206  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 9.191  ; 9.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 12.238 ; 12.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 12.736 ; 12.736 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 3.567  ; 3.567  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 2.918  ; 2.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.746  ; 3.746  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.849  ; 3.849  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 8.381  ; 8.381  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 11.581 ; 11.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 11.251 ; 11.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 11.388 ; 11.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 11.296 ; 11.296 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 10.997 ; 10.997 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 12.168 ; 12.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 11.194 ; 11.194 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 12.101 ; 12.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 12.073 ; 12.073 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 10.915 ; 10.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.906  ; 3.906  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 4.140  ; 4.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 4.140  ; 4.140  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.770  ; 3.770  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.683  ; 3.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 3.569  ; 3.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 8.258  ; 8.258  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.221  ; 3.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.136  ; 3.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.990  ; 2.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.153  ; 3.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 2.896  ; 2.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 2.977  ; 2.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 3.059  ; 3.059  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 11.613 ; 11.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 11.011 ; 11.011 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 11.056 ; 11.056 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 11.484 ; 11.484 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 11.027 ; 11.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 10.936 ; 10.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 11.613 ; 11.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 10.644 ; 10.644 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 11.387 ; 11.387 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 10.614 ; 10.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 8.935  ; 8.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 8.767  ; 8.767  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 8.596  ; 8.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 8.684  ; 8.684  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 10.496 ; 10.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 9.178  ; 9.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 10.496 ; 10.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 10.078 ; 10.078 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 9.666  ; 9.666  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 16.626 ; 16.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 17.427 ; 17.427 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.095 ; 17.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 17.100 ; 17.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.452 ; 17.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.642 ; 17.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 17.502 ; 17.502 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 17.542 ; 17.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 17.029 ; 17.029 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.486 ; 17.486 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 18.270 ; 18.270 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.055 ; 18.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 17.794 ; 17.794 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 17.290 ; 17.290 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 16.902 ; 16.902 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 16.778 ; 16.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 10.440 ; 10.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 10.013 ; 10.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 10.596 ; 10.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 10.003 ; 10.003 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 10.862 ; 10.862 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 10.704 ; 10.704 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 5.108  ; 5.108  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.550  ; 3.550  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 11.220 ; 11.220 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 12.051 ; 12.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 11.412 ; 11.412 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 12.519 ; 12.519 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 12.327 ; 12.327 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 11.900 ; 11.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 12.754 ; 12.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 4.754  ; 4.754  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.457  ; 3.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.738  ; 3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 3.174  ; 3.174  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 4.111  ; 4.111  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.625  ; 2.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.653  ; 2.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.765  ; 2.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.197  ; 2.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.882  ; 2.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.181  ; 2.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 3.199  ; 3.199  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 3.074  ; 3.074  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 2.347  ; 2.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 3.179  ; 3.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 4.058  ; 4.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 3.790  ; 3.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 2.955  ; 2.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 2.719  ; 2.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 3.744  ; 3.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 3.309  ; 3.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.692  ; 3.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.744  ; 3.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 8.200  ; 8.200  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 2.671  ; 2.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 5.839  ; 5.839  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 7.249  ; 7.249  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 6.915  ; 6.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 7.524  ; 7.524  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 7.283  ; 7.283  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 7.273  ; 7.273  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 5.151  ; 5.151  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 6.587  ; 6.587  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 6.318  ; 6.318  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 9.978  ; 9.978  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 9.453  ; 9.453  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 9.223  ; 9.223  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 8.999  ; 8.999  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 9.649  ; 9.649  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.177  ; 9.177  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 8.826  ; 8.826  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 9.978  ; 9.978  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 9.036  ; 9.036  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 14.964 ; 14.964 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 13.699 ; 13.699 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 13.616 ; 13.616 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 13.237 ; 13.237 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 13.277 ; 13.277 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.768 ; 12.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.257 ; 14.257 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 13.116 ; 13.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.218 ; 13.218 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 12.858 ; 12.858 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 13.389 ; 13.389 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 13.407 ; 13.407 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.964 ; 14.964 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.004 ; 13.004 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 13.691 ; 13.691 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 12.989 ; 12.989 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 13.265 ; 13.265 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 4.306  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 8.077  ; 8.077  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 8.575  ; 8.575  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 7.064  ; 7.064  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 6.734  ; 6.734  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 6.871  ; 6.871  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 6.779  ; 6.779  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 6.480  ; 6.480  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 7.651  ; 7.651  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 6.446  ; 6.446  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 7.325  ; 7.325  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 6.167  ; 6.167  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 6.863  ; 6.863  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 7.272  ; 7.272  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 7.526  ; 7.526  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 8.012  ; 8.012  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 7.514  ; 7.514  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 7.293  ; 7.293  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 7.905  ; 7.905  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.954  ; 6.954  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 7.706  ; 7.706  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.592  ; 6.592  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.991  ; 4.991  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 4.512  ; 4.512  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.082  ; 4.082  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 4.108  ; 4.108  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 5.467  ; 5.515  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.548  ; 4.548  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 5.467  ; 5.515  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 7.170  ; 7.170  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 6.756  ; 6.756  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 13.544 ; 13.544 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 11.878 ; 11.878 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 12.701 ; 12.701 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.394 ; 12.394 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 12.374 ; 12.374 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 12.897 ; 12.897 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 12.916 ; 12.916 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 12.947 ; 12.947 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 12.900 ; 12.900 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 12.469 ; 12.469 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 12.760 ; 12.760 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 13.544 ; 13.544 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 13.329 ; 13.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.068 ; 13.068 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 12.542 ; 12.542 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.105 ; 12.105 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.223 ; 12.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 8.925  ; 8.925  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 8.344  ; 8.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 9.081  ; 9.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 8.334  ; 8.334  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 6.135  ; 6.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 6.025  ; 5.977  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 6.449  ; 6.401  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 7.280  ; 7.232  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 7.251  ; 7.251  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 7.831  ; 7.783  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 7.639  ; 7.591  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 7.129  ; 7.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 8.066  ; 8.018  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 6.803  ; 6.803  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 8.016  ; 8.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 8.006  ; 8.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 5.186  ; 5.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BERRn          ; CLK_PLL1      ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BUTTONn        ; CLK_PLL1      ; 7.320  ; 7.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 7.051  ; 7.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 10.711 ; 10.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 10.186 ; 10.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 9.956  ; 9.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 9.732  ; 9.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 10.382 ; 10.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 9.910  ; 9.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 9.559  ; 9.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 10.711 ; 10.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 9.769  ; 9.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 10.280 ; 10.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 9.692  ; 9.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 10.280 ; 10.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 8.816  ; 8.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 9.686  ; 9.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 11.698 ; 11.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 11.698 ; 11.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 10.361 ; 10.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 10.055 ; 10.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 10.297 ; 10.297 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 8.549  ; 8.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 11.042 ; 11.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 9.329  ; 9.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 11.042 ; 11.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 9.055  ; 9.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 9.422  ; 9.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.405  ; 3.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SCLK       ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SYNCn      ; CLK_PLL1      ; 2.492  ; 2.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 15.584 ; 15.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 14.432 ; 14.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 14.236 ; 14.236 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 13.832 ; 13.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 13.897 ; 13.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 13.288 ; 13.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 14.877 ; 14.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 13.636 ; 13.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 13.754 ; 13.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 14.009 ; 14.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 14.027 ; 14.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 15.584 ; 15.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 13.624 ; 13.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 14.424 ; 14.424 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 13.680 ; 13.680 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 13.785 ; 13.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 2.535  ; 2.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_CEn      ; CLK_PLL1      ; 8.312  ; 8.312  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_OEn      ; CLK_PLL1      ; 8.810  ; 8.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC          ; CLK_PLL1      ; 8.897  ; 8.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS0n       ; CLK_PLL1      ; 7.655  ; 7.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS1n       ; CLK_PLL1      ; 7.325  ; 7.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 7.462  ; 7.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 7.370  ; 7.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IORDn      ; CLK_PLL1      ; 7.071  ; 7.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IOWRn      ; CLK_PLL1      ; 8.242  ; 8.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RHn        ; CLK_PLL1      ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RLn        ; CLK_PLL1      ; 8.086  ; 8.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WEn        ; CLK_PLL1      ; 8.058  ; 8.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WL         ; CLK_PLL1      ; 6.900  ; 6.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.405  ; 2.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.182  ; 2.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PADRSTn        ; CLK_PLL1      ; 2.780  ; 2.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 7.207  ; 7.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 6.977  ; 6.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 7.365  ; 7.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.816  ; 6.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 7.025  ; 7.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 6.535  ; 6.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 6.397  ; 6.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 6.063  ; 6.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 6.298  ; 6.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 6.277  ; 6.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.886  ; 4.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 6.277  ; 6.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 7.205  ; 7.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 14.164 ; 14.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 12.611 ; 12.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 13.321 ; 13.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 12.989 ; 12.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 12.994 ; 12.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 13.417 ; 13.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 13.536 ; 13.536 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 13.467 ; 13.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 13.436 ; 13.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 12.989 ; 12.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 13.380 ; 13.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 14.164 ; 14.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 13.949 ; 13.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 13.688 ; 13.688 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 13.275 ; 13.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 12.796 ; 12.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 12.743 ; 12.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 8.960  ; 8.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 8.379  ; 8.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 9.116  ; 9.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 8.369  ; 8.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 6.945  ; 6.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 5.541  ; 5.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 3.883  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM0n          ; CLK_PLL1      ; 7.211  ; 7.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM1n          ; CLK_PLL1      ; 8.042  ; 8.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM2n          ; CLK_PLL1      ; 7.486  ; 7.486  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM3n          ; CLK_PLL1      ; 8.593  ; 8.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM4n          ; CLK_PLL1      ; 8.401  ; 8.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM5n          ; CLK_PLL1      ; 7.891  ; 7.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM6n          ; CLK_PLL1      ; 8.828  ; 8.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 5.364  ; 5.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC          ; CLK_PLL1      ; 6.355  ; 6.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.909  ; 3.909  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 3.909  ; 3.909  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 8.016  ; 8.016  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 8.006  ; 8.006  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 5.186  ; 5.186  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 7.320  ; 7.320  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 7.051  ; 7.051  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 10.711 ; 10.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 10.186 ; 10.186 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 9.956  ; 9.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 9.732  ; 9.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 10.382 ; 10.382 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 9.910  ; 9.910  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 9.559  ; 9.559  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 10.711 ; 10.711 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 9.769  ; 9.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 10.280 ; 10.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 9.692  ; 9.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 10.280 ; 10.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 8.816  ; 8.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 9.686  ; 9.686  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 11.698 ; 11.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 11.698 ; 11.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 10.361 ; 10.361 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 10.055 ; 10.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 10.297 ; 10.297 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 8.549  ; 8.549  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 11.042 ; 11.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 9.329  ; 9.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 11.042 ; 11.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 9.055  ; 9.055  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 9.422  ; 9.422  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.405  ; 3.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 2.492  ; 2.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 15.584 ; 15.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 14.432 ; 14.432 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 14.236 ; 14.236 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 13.832 ; 13.832 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 13.897 ; 13.897 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.288 ; 13.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 14.877 ; 14.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 13.636 ; 13.636 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 13.754 ; 13.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 13.378 ; 13.378 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 14.009 ; 14.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.027 ; 14.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.584 ; 15.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 13.624 ; 13.624 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 14.424 ; 14.424 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 13.680 ; 13.680 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 13.785 ; 13.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 2.535  ; 2.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 8.312  ; 8.312  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 8.810  ; 8.810  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 8.897  ; 8.897  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 7.655  ; 7.655  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 7.325  ; 7.325  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 7.462  ; 7.462  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 7.370  ; 7.370  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 7.071  ; 7.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 8.242  ; 8.242  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 7.179  ; 7.179  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 8.086  ; 8.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 8.058  ; 8.058  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 6.900  ; 6.900  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.405  ; 2.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.182  ; 2.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 2.890  ; 2.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 2.780  ; 2.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 7.207  ; 7.207  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 6.977  ; 6.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 7.365  ; 7.365  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 7.694  ; 7.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.816  ; 6.816  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 7.264  ; 7.264  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.861  ; 6.861  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 7.025  ; 7.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 6.535  ; 6.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 6.397  ; 6.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 6.063  ; 6.063  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 6.667  ; 6.667  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 6.298  ; 6.298  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 6.277  ; 6.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.886  ; 4.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 6.277  ; 6.277  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 7.205  ; 7.205  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 6.791  ; 6.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 14.164 ; 14.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 12.611 ; 12.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 13.321 ; 13.321 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 12.989 ; 12.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 12.994 ; 12.994 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 13.417 ; 13.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 13.536 ; 13.536 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 13.467 ; 13.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 13.436 ; 13.436 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 12.989 ; 12.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 13.380 ; 13.380 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 14.164 ; 14.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 13.949 ; 13.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 13.688 ; 13.688 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 13.275 ; 13.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 12.796 ; 12.796 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 12.743 ; 12.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 8.960  ; 8.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 8.379  ; 8.379  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 9.116  ; 9.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 8.369  ; 8.369  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 6.945  ; 6.945  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 6.787  ; 6.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 5.541  ; 5.541  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.883  ; 3.883  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 7.211  ; 7.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 8.042  ; 8.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 7.486  ; 7.486  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 8.593  ; 8.593  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 8.401  ; 8.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 7.891  ; 7.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 8.828  ; 8.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 5.364  ; 5.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 6.355  ; 6.355  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.909  ; 3.909  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 3.909  ; 3.909  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CLK_AUX        ; CLK_PLL2      ; 1.223  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL2      ; 10.142 ; 10.142 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL2      ; 9.554  ; 9.554  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL2      ; 10.142 ; 10.142 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL2      ; 8.678  ; 8.678  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL2      ; 9.548  ; 9.548  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL2      ; 11.560 ; 11.560 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL2      ; 11.560 ; 11.560 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL2      ; 10.223 ; 10.223 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL2      ; 9.917  ; 9.917  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL2      ; 10.159 ; 10.159 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL2      ; 8.411  ; 8.411  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL2      ; 10.904 ; 10.904 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL2      ; 9.191  ; 9.191  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL2      ; 10.904 ; 10.904 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL2      ; 8.917  ; 8.917  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL2      ; 9.284  ; 9.284  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL2      ; 2.759  ; 2.759  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ; 2.686  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL2      ; 10.238 ; 10.238 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL2      ; 10.238 ; 10.238 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL2      ; 10.138 ; 10.138 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL2      ; 9.535  ; 9.535  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL2      ; 9.589  ; 9.589  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL2      ; 8.862  ; 8.862  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL2      ; 10.227 ; 10.227 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL2      ; 8.965  ; 8.965  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL2      ; 9.782  ; 9.782  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL2      ; 9.162  ; 9.162  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL2      ; 9.866  ; 9.866  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL2      ; 9.451  ; 9.451  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL2      ; 8.759  ; 8.759  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL2      ; 9.588  ; 9.588  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL2      ; 8.417  ; 8.417  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL2      ; 9.223  ; 9.223  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL2      ; 8.692  ; 8.692  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL2      ; 8.686  ; 8.686  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL2      ; 8.991  ; 8.991  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL2      ; 8.886  ; 8.886  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL2      ; 8.796  ; 8.796  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL2      ; 9.464  ; 9.464  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL2      ; 8.773  ; 8.773  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL2      ; 9.237  ; 9.237  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL2      ; 9.588  ; 9.588  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL2      ; 6.217  ; 6.217  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ; 3.441  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ; 3.441  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL2      ;        ; 1.223  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ;        ; 2.686  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ;        ; 3.441  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ;        ; 3.441  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; PLL_FAULT      ; CLK_PLL1      ; 3.910  ; 3.910  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 4.222  ; 4.222  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_RDn       ; CLK_PLL1      ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 3.651  ; 3.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 4.815  ; 4.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 4.191  ; 4.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 4.169  ; 4.169  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 4.310  ; 4.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 4.398  ; 4.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 4.709  ; 4.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 4.323  ; 4.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 4.421  ; 4.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 4.142  ; 4.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 4.046  ; 4.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 4.683  ; 4.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 4.439  ; 4.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 4.316  ; 4.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 4.597  ; 4.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 5.187  ; 5.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 4.319  ; 4.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.457  ; 3.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.520  ; 3.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.431  ; 3.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.087  ; 4.087  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 2.742  ; 2.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 3.653  ; 3.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL1      ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL1      ; 5.129  ; 5.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL1      ; 5.902  ; 5.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL1      ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL1      ; 6.024  ; 6.024  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL1      ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL1      ; 5.283  ; 5.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL1      ; 5.516  ; 5.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL1      ; 4.887  ; 4.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL1      ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL1      ; 5.818  ; 5.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL1      ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL1      ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL1      ; 5.505  ; 5.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL1      ; 5.677  ; 5.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL1      ; 5.768  ; 5.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 4.373  ; 4.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 4.692  ; 4.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 3.966  ; 3.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 4.504  ; 4.504  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 4.123  ; 4.123  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 3.884  ; 3.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 4.744  ; 4.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 3.971  ; 3.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 3.981  ; 3.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 2.747  ; 2.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 3.020  ; 3.020  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 2.796  ; 2.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 2.608  ; 2.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 2.289  ; 2.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 2.506  ; 2.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.596  ; 3.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 2.599  ; 2.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 2.512  ; 2.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 2.229  ; 2.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 2.097  ; 2.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 4.306  ; 4.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 4.013  ; 4.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 3.958  ; 3.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 4.387  ; 4.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 2.918  ; 2.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.364  ; 3.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 3.702  ; 3.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 3.595  ; 3.656  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 3.830  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 3.610  ; 3.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 3.631  ; 3.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 3.641  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 3.476  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.363  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.542  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.384  ; 3.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.189  ; 3.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.609  ; 3.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.097  ; 3.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.270  ; 3.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.221  ; 3.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.136  ; 3.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.990  ; 2.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.153  ; 3.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 2.896  ; 2.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 2.977  ; 2.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 2.606  ; 2.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 6.360  ; 6.360  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 6.333  ; 6.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.181  ; 6.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.028  ; 6.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.858  ; 6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.337  ; 6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.281  ; 4.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.935  ; 3.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.777  ; 3.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.183  ; 4.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.643  ; 4.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.866  ; 4.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.159  ; 5.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 4.859  ; 4.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.349  ; 5.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 4.219  ; 4.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 4.570  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.380  ; 5.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.374  ; 4.374  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.590  ; 4.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.505  ; 4.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.968  ; 3.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.661  ; 4.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.958  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.436  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.913  ; 5.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_WEn        ; CLK_PLL1      ; 4.894  ; 4.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 3.204  ; 3.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.960  ; 3.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.792  ; 4.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.502  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.053  ; 4.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.723  ; 4.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.431  ; 4.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.571  ; 3.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.738  ; 3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.820  ; 2.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.625  ; 2.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.653  ; 2.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.765  ; 2.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.197  ; 2.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.882  ; 2.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.181  ; 2.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 2.779  ; 2.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 2.441  ; 2.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 2.347  ; 2.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 2.760  ; 2.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.591  ; 3.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 3.790  ; 3.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 2.496  ; 2.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.034  ; 3.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.279  ; 3.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 2.671  ; 2.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 5.046  ; 5.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 3.859  ; 3.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 5.448  ; 5.448  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.438  ; 5.438  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.457  ; 3.457  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.211  ; 4.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 4.483  ; 4.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.289  ; 6.289  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.985  ; 5.985  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.298  ; 6.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 6.158  ; 6.158  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.070  ; 6.070  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 6.085  ; 6.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.411  ; 7.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.142  ; 7.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 6.846  ; 6.846  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.961  ; 6.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.344  ; 6.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.503  ; 7.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 6.189  ; 6.189  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.449  ; 6.449  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.472  ; 6.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.863  ; 6.745  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 6.646  ; 6.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.902  ; 7.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.362  ; 6.362  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.614  ; 7.533  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 6.004  ; 6.004  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 4.306  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.562  ; 5.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 6.060  ; 5.826  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 3.763  ; 3.702  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 3.656  ; 3.595  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 3.891  ; 3.830  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 3.671  ; 3.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 3.715  ; 3.631  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 3.720  ; 3.641  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 3.663  ; 3.476  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.570  ; 4.363  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.335  ; 4.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.116  ; 3.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.267  ; 3.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 6.613  ; 6.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 6.584  ; 6.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.305  ; 6.305  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.394  ; 6.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 7.067  ; 7.067  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.065  ; 6.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 5.899  ; 5.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.281  ; 4.281  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.935  ; 3.935  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.777  ; 3.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.179  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.183  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.179  ; 4.768  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.278  ; 4.643  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.231  ; 3.866  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.590  ; 5.590  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.227  ; 6.166  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.003  ; 6.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.058  ; 6.058  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.473  ; 6.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.162  ; 6.162  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 6.020  ; 6.020  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 6.131  ; 6.131  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.083  ; 5.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.234  ; 6.116  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.783  ; 6.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.267  ; 6.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.426  ; 6.426  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.465  ; 6.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.962  ; 4.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.774  ; 4.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.904  ; 3.968  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.930  ; 4.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.894  ; 3.958  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.071  ; 5.436  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.278  ; 4.913  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 4.005  ; 4.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.832  ; 4.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.736  ; 4.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.351  ; 4.351  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.086  ; 4.086  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.279  ; 3.279  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 3.651  ; 3.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 4.815  ; 4.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 4.191  ; 4.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 4.169  ; 4.169  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 4.310  ; 4.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 4.398  ; 4.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 4.709  ; 4.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 4.323  ; 4.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 4.421  ; 4.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 4.142  ; 4.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 4.046  ; 4.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 4.683  ; 4.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 4.439  ; 4.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 4.316  ; 4.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 4.597  ; 4.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 5.187  ; 5.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 4.319  ; 4.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.457  ; 3.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.520  ; 3.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.431  ; 3.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.087  ; 4.087  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 2.742  ; 2.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 3.653  ; 3.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 5.129  ; 5.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 5.902  ; 5.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 6.024  ; 6.024  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 5.283  ; 5.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 5.516  ; 5.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 4.887  ; 4.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 5.818  ; 5.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 5.505  ; 5.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 5.677  ; 5.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 5.768  ; 5.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.373  ; 4.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 4.692  ; 4.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 3.966  ; 3.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 4.504  ; 4.504  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.123  ; 4.123  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 3.884  ; 3.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 4.744  ; 4.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 3.971  ; 3.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 3.981  ; 3.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 2.747  ; 2.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 3.020  ; 3.020  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 2.796  ; 2.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 2.608  ; 2.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 2.289  ; 2.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 2.506  ; 2.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.596  ; 3.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 2.599  ; 2.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 2.512  ; 2.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 2.229  ; 2.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 2.097  ; 2.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 4.306  ; 4.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 4.013  ; 4.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 3.958  ; 3.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 4.387  ; 4.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 2.918  ; 2.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.364  ; 3.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 3.702  ; 3.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 3.595  ; 3.656  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 3.830  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 3.610  ; 3.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 3.631  ; 3.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 3.641  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 3.476  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.363  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.542  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.384  ; 3.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.189  ; 3.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.609  ; 3.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.097  ; 3.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.270  ; 3.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.221  ; 3.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.136  ; 3.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.990  ; 2.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.153  ; 3.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 2.896  ; 2.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 2.977  ; 2.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 2.606  ; 2.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 6.360  ; 6.360  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 6.333  ; 6.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.181  ; 6.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.028  ; 6.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.858  ; 6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.337  ; 6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.281  ; 4.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.935  ; 3.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.777  ; 3.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.183  ; 4.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.643  ; 4.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.866  ; 4.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.159  ; 5.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 4.859  ; 4.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.349  ; 5.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 4.219  ; 4.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 4.570  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.380  ; 5.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.374  ; 4.374  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.590  ; 4.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.505  ; 4.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.968  ; 3.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.661  ; 4.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.958  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.436  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.913  ; 5.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 4.894  ; 4.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.204  ; 3.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.960  ; 3.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.792  ; 4.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.502  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.053  ; 4.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.723  ; 4.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.431  ; 4.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.571  ; 3.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.738  ; 3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.820  ; 2.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.625  ; 2.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.653  ; 2.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.765  ; 2.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.197  ; 2.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.882  ; 2.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.181  ; 2.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 2.779  ; 2.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 2.441  ; 2.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 2.347  ; 2.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 2.760  ; 2.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.591  ; 3.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 3.790  ; 3.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 2.496  ; 2.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.034  ; 3.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.279  ; 3.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 2.671  ; 2.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 5.046  ; 5.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 3.859  ; 3.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.448  ; 5.448  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.438  ; 5.438  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.457  ; 3.457  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.483  ; 4.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.289  ; 6.289  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.985  ; 5.985  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.298  ; 6.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.158  ; 6.158  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.070  ; 6.070  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 6.085  ; 6.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.411  ; 7.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.142  ; 7.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.846  ; 6.846  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.961  ; 6.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.344  ; 6.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.503  ; 7.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.189  ; 6.189  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.449  ; 6.449  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.472  ; 6.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.863  ; 6.745  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.646  ; 6.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.902  ; 7.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.362  ; 6.362  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.614  ; 7.533  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.004  ; 6.004  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 4.306  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.562  ; 5.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 6.060  ; 5.826  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 3.763  ; 3.702  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 3.656  ; 3.595  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 3.891  ; 3.830  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 3.671  ; 3.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 3.715  ; 3.631  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 3.720  ; 3.641  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 3.663  ; 3.476  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.570  ; 4.363  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.335  ; 4.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.116  ; 3.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.267  ; 3.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 6.613  ; 6.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 6.584  ; 6.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.305  ; 6.305  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.394  ; 6.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 7.067  ; 7.067  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.065  ; 6.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 5.899  ; 5.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.281  ; 4.281  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.935  ; 3.935  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.777  ; 3.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.179  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.183  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.179  ; 4.768  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.278  ; 4.643  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.231  ; 3.866  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.590  ; 5.590  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.227  ; 6.166  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.003  ; 6.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.058  ; 6.058  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.473  ; 6.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.162  ; 6.162  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 6.020  ; 6.020  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 6.131  ; 6.131  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.083  ; 5.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.234  ; 6.116  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.783  ; 6.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.267  ; 6.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.426  ; 6.426  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.465  ; 6.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.962  ; 4.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.774  ; 4.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.904  ; 3.968  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.930  ; 4.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.894  ; 3.958  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.071  ; 5.436  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.278  ; 4.913  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 4.005  ; 4.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.832  ; 4.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.736  ; 4.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.351  ; 4.351  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.086  ; 4.086  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.279  ; 3.279  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.157  ; 5.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 4.620  ; 4.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BERRn          ; CLK_PLL1      ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BUTTONn        ; CLK_PLL1      ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 4.202  ; 4.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 5.704  ; 5.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 5.877  ; 5.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 5.789  ; 5.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 5.804  ; 5.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 5.681  ; 5.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.769  ; 3.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 3.823  ; 3.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 4.261  ; 4.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 3.433  ; 3.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.405  ; 3.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SCLK       ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SYNCn      ; CLK_PLL1      ; 2.492  ; 2.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 5.387  ; 5.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 5.803  ; 5.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 6.588  ; 6.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 5.787  ; 5.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 5.337  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 5.924  ; 5.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.670  ; 5.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.704  ; 6.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.288  ; 5.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.211  ; 5.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 2.535  ; 2.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.828  ; 5.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_OEn      ; CLK_PLL1      ; 6.326  ; 6.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC          ; CLK_PLL1      ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS0n       ; CLK_PLL1      ; 3.870  ; 3.870  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS1n       ; CLK_PLL1      ; 3.907  ; 3.907  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.225  ; 4.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.005  ; 4.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.049  ; 4.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IOWRn      ; CLK_PLL1      ; 4.054  ; 4.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RHn        ; CLK_PLL1      ; 3.802  ; 3.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RLn        ; CLK_PLL1      ; 4.719  ; 4.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WEn        ; CLK_PLL1      ; 4.691  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WL         ; CLK_PLL1      ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.405  ; 2.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.182  ; 2.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 2.219  ; 2.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PADRSTn        ; CLK_PLL1      ; 2.538  ; 2.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.029  ; 4.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.600  ; 4.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.253  ; 4.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.419  ; 4.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.201  ; 4.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.104  ; 4.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.137  ; 4.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 4.075  ; 4.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.479  ; 4.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 3.597  ; 3.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.183  ; 3.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.472  ; 4.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.960  ; 4.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.057  ; 5.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.481  ; 5.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.247  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 4.866  ; 4.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.469  ; 5.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 4.948  ; 4.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.807  ; 5.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 5.086  ; 5.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.572  ; 4.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 4.523  ; 4.523  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.280  ; 5.280  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 3.454  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM0n          ; CLK_PLL1      ; 3.737  ; 3.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM1n          ; CLK_PLL1      ; 4.569  ; 4.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM2n          ; CLK_PLL1      ; 5.002  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM3n          ; CLK_PLL1      ; 4.165  ; 4.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM4n          ; CLK_PLL1      ; 3.901  ; 3.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM5n          ; CLK_PLL1      ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM6n          ; CLK_PLL1      ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 4.798  ; 4.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC          ; CLK_PLL1      ; 3.188  ; 3.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.157  ; 5.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.620  ; 4.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.202  ; 4.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.704  ; 5.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.877  ; 5.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.789  ; 5.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.804  ; 5.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.681  ; 5.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.769  ; 3.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 3.823  ; 3.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 4.261  ; 4.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.405  ; 3.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 2.492  ; 2.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.387  ; 5.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.803  ; 5.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.588  ; 6.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.787  ; 5.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 5.337  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.924  ; 5.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.670  ; 5.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.704  ; 6.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.288  ; 5.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.211  ; 5.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 2.535  ; 2.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.828  ; 5.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 6.326  ; 6.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 3.870  ; 3.870  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 3.907  ; 3.907  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.225  ; 4.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.005  ; 4.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.049  ; 4.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 4.054  ; 4.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 3.802  ; 3.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.719  ; 4.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.691  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.405  ; 2.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.182  ; 2.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 2.219  ; 2.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 2.538  ; 2.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.029  ; 4.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.600  ; 4.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.253  ; 4.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.419  ; 4.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.201  ; 4.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.104  ; 4.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.137  ; 4.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 4.075  ; 4.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.479  ; 4.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 3.597  ; 3.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.183  ; 3.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.472  ; 4.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.960  ; 4.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.057  ; 5.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.481  ; 5.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.247  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 4.866  ; 4.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.469  ; 5.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 4.948  ; 4.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.807  ; 5.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.086  ; 5.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.572  ; 4.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 4.523  ; 4.523  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.280  ; 5.280  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 3.454  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.737  ; 3.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.569  ; 4.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 5.002  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.165  ; 4.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.901  ; 3.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.798  ; 4.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.188  ; 3.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CLK_AUX        ; CLK_PLL2      ; 1.223  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL2      ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL2      ; 5.507  ; 5.507  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL2      ; 6.280  ; 6.280  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL2      ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL2      ; 6.402  ; 6.402  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL2      ; 5.151  ; 5.151  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL2      ; 5.661  ; 5.661  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL2      ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL2      ; 5.265  ; 5.265  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL2      ; 5.151  ; 5.151  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL2      ; 6.196  ; 6.196  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL2      ; 5.775  ; 5.775  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL2      ; 5.775  ; 5.775  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL2      ; 5.883  ; 5.883  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL2      ; 6.055  ; 6.055  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL2      ; 6.146  ; 6.146  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL2      ; 2.759  ; 2.759  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ; 2.686  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL2      ; 8.756  ; 8.756  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL2      ; 10.107 ; 10.107 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL2      ; 9.663  ; 9.663  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL2      ; 8.913  ; 8.913  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL2      ; 9.284  ; 9.284  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL2      ; 8.756  ; 8.756  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL2      ; 10.114 ; 10.114 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL2      ; 8.954  ; 8.954  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL2      ; 9.458  ; 9.458  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL2      ; 9.150  ; 9.150  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL2      ; 9.866  ; 9.866  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL2      ; 9.451  ; 9.451  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL2      ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL2      ; 8.070  ; 8.070  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL2      ; 8.286  ; 8.286  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL2      ; 8.748  ; 8.748  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL2      ; 8.070  ; 8.070  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL2      ; 8.381  ; 8.381  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL2      ; 8.885  ; 8.885  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL2      ; 8.773  ; 8.773  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL2      ; 8.785  ; 8.785  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL2      ; 9.140  ; 9.140  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL2      ; 8.761  ; 8.761  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL2      ; 9.237  ; 9.237  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL2      ; 9.588  ; 9.588  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL2      ; 5.424  ; 5.424  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ; 3.441  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ; 3.441  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL2      ;        ; 1.223  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ;        ; 2.686  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ;        ; 3.441  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ;        ; 3.441  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Propagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ADR[1]       ; DATA[0]       ; 13.589 ; 13.589 ; 13.589 ; 13.589 ;
; ADR[1]       ; DATA[1]       ; 13.486 ; 13.486 ; 13.486 ; 13.486 ;
; ADR[1]       ; DATA[2]       ; 13.069 ; 12.990 ; 12.990 ; 13.069 ;
; ADR[1]       ; DATA[3]       ; 14.090 ; 14.090 ; 14.090 ; 14.090 ;
; ADR[1]       ; DATA[4]       ; 12.575 ; 12.575 ; 12.575 ; 12.575 ;
; ADR[1]       ; DATA[5]       ; 13.629 ; 13.629 ; 13.629 ; 13.629 ;
; ADR[1]       ; DATA[6]       ; 12.508 ; 12.508 ; 12.508 ; 12.508 ;
; ADR[1]       ; DATA[7]       ; 13.473 ; 13.473 ; 13.473 ; 13.473 ;
; ADR[1]       ; DATA[8]       ; 12.786 ; 12.786 ; 12.786 ; 12.786 ;
; ADR[1]       ; DATA[9]       ; 13.089 ; 13.089 ; 13.089 ; 13.089 ;
; ADR[1]       ; DATA[10]      ; 13.050 ; 12.971 ; 12.971 ; 13.050 ;
; ADR[1]       ; DATA[11]      ; 14.128 ; 14.128 ; 14.128 ; 14.128 ;
; ADR[1]       ; DATA[12]      ; 13.300 ; 13.300 ; 13.300 ; 13.300 ;
; ADR[1]       ; DATA[13]      ; 13.523 ; 13.481 ; 13.481 ; 13.523 ;
; ADR[1]       ; DATA[14]      ; 13.221 ; 13.221 ; 13.221 ; 13.221 ;
; ADR[1]       ; DATA[15]      ; 13.488 ; 13.488 ; 13.488 ; 13.488 ;
; ADR[1]       ; RAM_DATA[0]   ; 11.768 ; 11.768 ; 11.768 ; 11.768 ;
; ADR[1]       ; RAM_DATA[1]   ; 12.571 ; 12.571 ; 12.571 ; 12.571 ;
; ADR[1]       ; RAM_DATA[2]   ; 12.226 ; 12.147 ; 12.147 ; 12.226 ;
; ADR[1]       ; RAM_DATA[3]   ; 13.187 ; 13.187 ; 13.187 ; 13.187 ;
; ADR[1]       ; RAM_DATA[4]   ; 12.704 ; 12.704 ; 12.704 ; 12.704 ;
; ADR[1]       ; RAM_DATA[5]   ; 12.288 ; 12.288 ; 12.288 ; 12.288 ;
; ADR[1]       ; RAM_DATA[6]   ; 12.339 ; 12.339 ; 12.339 ; 12.339 ;
; ADR[1]       ; RAM_DATA[7]   ; 13.155 ; 13.155 ; 13.155 ; 13.155 ;
; ADR[1]       ; RAM_DATA[8]   ; 12.397 ; 12.397 ; 12.397 ; 12.397 ;
; ADR[1]       ; RAM_DATA[9]   ; 12.460 ; 12.460 ; 12.460 ; 12.460 ;
; ADR[1]       ; RAM_DATA[10]  ; 13.187 ; 13.108 ; 13.108 ; 13.187 ;
; ADR[1]       ; RAM_DATA[11]  ; 12.493 ; 12.493 ; 12.493 ; 12.493 ;
; ADR[1]       ; RAM_DATA[12]  ; 13.364 ; 13.364 ; 13.364 ; 13.364 ;
; ADR[1]       ; RAM_DATA[13]  ; 12.374 ; 12.332 ; 12.332 ; 12.374 ;
; ADR[1]       ; RAM_DATA[14]  ; 12.337 ; 12.337 ; 12.337 ; 12.337 ;
; ADR[1]       ; RAM_DATA[15]  ; 12.446 ; 12.446 ; 12.446 ; 12.446 ;
; ADR[2]       ; DATA[0]       ; 13.956 ; 13.995 ; 13.995 ; 13.956 ;
; ADR[2]       ; DATA[1]       ; 13.853 ; 13.891 ; 13.891 ; 13.853 ;
; ADR[2]       ; DATA[2]       ; 13.357 ; 13.551 ; 13.551 ; 13.357 ;
; ADR[2]       ; DATA[3]       ; 14.576 ; 14.576 ; 14.576 ; 14.576 ;
; ADR[2]       ; DATA[4]       ; 13.061 ; 13.061 ; 13.061 ; 13.061 ;
; ADR[2]       ; DATA[5]       ; 14.111 ; 14.111 ; 14.111 ; 14.111 ;
; ADR[2]       ; DATA[6]       ; 12.963 ; 12.963 ; 12.963 ; 12.963 ;
; ADR[2]       ; DATA[7]       ; 13.959 ; 13.959 ; 13.959 ; 13.959 ;
; ADR[2]       ; DATA[8]       ; 13.153 ; 13.192 ; 13.192 ; 13.153 ;
; ADR[2]       ; DATA[9]       ; 13.456 ; 13.494 ; 13.494 ; 13.456 ;
; ADR[2]       ; DATA[10]      ; 13.338 ; 13.532 ; 13.532 ; 13.338 ;
; ADR[2]       ; DATA[11]      ; 14.614 ; 14.614 ; 14.614 ; 14.614 ;
; ADR[2]       ; DATA[12]      ; 13.786 ; 13.786 ; 13.786 ; 13.786 ;
; ADR[2]       ; DATA[13]      ; 13.967 ; 14.005 ; 14.005 ; 13.967 ;
; ADR[2]       ; DATA[14]      ; 13.707 ; 13.707 ; 13.707 ; 13.707 ;
; ADR[2]       ; DATA[15]      ; 13.974 ; 13.974 ; 13.974 ; 13.974 ;
; ADR[2]       ; RAM_DATA[0]   ; 12.135 ; 12.174 ; 12.174 ; 12.135 ;
; ADR[2]       ; RAM_DATA[1]   ; 12.938 ; 12.976 ; 12.976 ; 12.938 ;
; ADR[2]       ; RAM_DATA[2]   ; 12.514 ; 12.708 ; 12.708 ; 12.514 ;
; ADR[2]       ; RAM_DATA[3]   ; 13.673 ; 13.673 ; 13.673 ; 13.673 ;
; ADR[2]       ; RAM_DATA[4]   ; 13.190 ; 13.190 ; 13.190 ; 13.190 ;
; ADR[2]       ; RAM_DATA[5]   ; 12.770 ; 12.770 ; 12.770 ; 12.770 ;
; ADR[2]       ; RAM_DATA[6]   ; 12.794 ; 12.794 ; 12.794 ; 12.794 ;
; ADR[2]       ; RAM_DATA[7]   ; 13.641 ; 13.641 ; 13.641 ; 13.641 ;
; ADR[2]       ; RAM_DATA[8]   ; 12.764 ; 12.803 ; 12.803 ; 12.764 ;
; ADR[2]       ; RAM_DATA[9]   ; 12.827 ; 12.865 ; 12.865 ; 12.827 ;
; ADR[2]       ; RAM_DATA[10]  ; 13.475 ; 13.669 ; 13.669 ; 13.475 ;
; ADR[2]       ; RAM_DATA[11]  ; 12.979 ; 12.979 ; 12.979 ; 12.979 ;
; ADR[2]       ; RAM_DATA[12]  ; 13.850 ; 13.850 ; 13.850 ; 13.850 ;
; ADR[2]       ; RAM_DATA[13]  ; 12.818 ; 12.856 ; 12.856 ; 12.818 ;
; ADR[2]       ; RAM_DATA[14]  ; 12.823 ; 12.823 ; 12.823 ; 12.823 ;
; ADR[2]       ; RAM_DATA[15]  ; 12.932 ; 12.932 ; 12.932 ; 12.932 ;
; ADR[3]       ; DATA[0]       ; 13.483 ; 13.389 ; 13.389 ; 13.483 ;
; ADR[3]       ; DATA[1]       ; 13.379 ; 13.286 ; 13.286 ; 13.379 ;
; ADR[3]       ; DATA[2]       ; 12.883 ; 12.790 ; 12.790 ; 12.883 ;
; ADR[3]       ; DATA[3]       ; 13.835 ; 13.835 ; 13.835 ; 13.835 ;
; ADR[3]       ; DATA[4]       ; 12.382 ; 12.382 ; 12.382 ; 12.382 ;
; ADR[3]       ; DATA[5]       ; 13.433 ; 13.433 ; 13.433 ; 13.433 ;
; ADR[3]       ; DATA[6]       ; 12.471 ; 12.471 ; 12.471 ; 12.471 ;
; ADR[3]       ; DATA[7]       ; 13.218 ; 13.218 ; 13.218 ; 13.218 ;
; ADR[3]       ; DATA[8]       ; 12.680 ; 12.586 ; 12.586 ; 12.680 ;
; ADR[3]       ; DATA[9]       ; 12.982 ; 12.889 ; 12.889 ; 12.982 ;
; ADR[3]       ; DATA[10]      ; 12.864 ; 12.771 ; 12.771 ; 12.864 ;
; ADR[3]       ; DATA[11]      ; 13.873 ; 13.873 ; 13.873 ; 13.873 ;
; ADR[3]       ; DATA[12]      ; 13.045 ; 13.045 ; 13.045 ; 13.045 ;
; ADR[3]       ; DATA[13]      ; 13.226 ; 13.226 ; 13.226 ; 13.226 ;
; ADR[3]       ; DATA[14]      ; 12.966 ; 12.966 ; 12.966 ; 12.966 ;
; ADR[3]       ; DATA[15]      ; 13.233 ; 13.233 ; 13.233 ; 13.233 ;
; ADR[3]       ; RAM_DATA[0]   ; 11.662 ; 11.568 ; 11.568 ; 11.662 ;
; ADR[3]       ; RAM_DATA[1]   ; 12.464 ; 12.371 ; 12.371 ; 12.464 ;
; ADR[3]       ; RAM_DATA[2]   ; 12.040 ; 11.947 ; 11.947 ; 12.040 ;
; ADR[3]       ; RAM_DATA[3]   ; 12.932 ; 12.932 ; 12.932 ; 12.932 ;
; ADR[3]       ; RAM_DATA[4]   ; 12.511 ; 12.511 ; 12.511 ; 12.511 ;
; ADR[3]       ; RAM_DATA[5]   ; 12.092 ; 12.092 ; 12.092 ; 12.092 ;
; ADR[3]       ; RAM_DATA[6]   ; 12.302 ; 12.302 ; 12.302 ; 12.302 ;
; ADR[3]       ; RAM_DATA[7]   ; 12.900 ; 12.900 ; 12.900 ; 12.900 ;
; ADR[3]       ; RAM_DATA[8]   ; 12.291 ; 12.197 ; 12.197 ; 12.291 ;
; ADR[3]       ; RAM_DATA[9]   ; 12.353 ; 12.260 ; 12.260 ; 12.353 ;
; ADR[3]       ; RAM_DATA[10]  ; 13.001 ; 12.908 ; 12.908 ; 13.001 ;
; ADR[3]       ; RAM_DATA[11]  ; 12.238 ; 12.238 ; 12.238 ; 12.238 ;
; ADR[3]       ; RAM_DATA[12]  ; 13.109 ; 13.109 ; 13.109 ; 13.109 ;
; ADR[3]       ; RAM_DATA[13]  ; 12.077 ; 12.077 ; 12.077 ; 12.077 ;
; ADR[3]       ; RAM_DATA[14]  ; 12.082 ; 12.082 ; 12.082 ; 12.082 ;
; ADR[3]       ; RAM_DATA[15]  ; 12.191 ; 12.191 ; 12.191 ; 12.191 ;
; ADR[4]       ; DATA[0]       ; 13.556 ; 13.559 ; 13.559 ; 13.556 ;
; ADR[4]       ; DATA[1]       ; 13.453 ; 13.455 ; 13.455 ; 13.453 ;
; ADR[4]       ; DATA[2]       ; 13.041 ; 12.959 ; 12.959 ; 13.041 ;
; ADR[4]       ; DATA[3]       ; 14.140 ; 14.140 ; 14.140 ; 14.140 ;
; ADR[4]       ; DATA[4]       ; 12.625 ; 12.625 ; 12.625 ; 12.625 ;
; ADR[4]       ; DATA[5]       ; 13.637 ; 13.637 ; 13.637 ; 13.637 ;
; ADR[4]       ; DATA[6]       ; 12.435 ; 12.435 ; 12.435 ; 12.435 ;
; ADR[4]       ; DATA[7]       ; 13.523 ; 13.523 ; 13.523 ; 13.523 ;
; ADR[4]       ; DATA[8]       ; 12.753 ; 12.756 ; 12.756 ; 12.753 ;
; ADR[4]       ; DATA[9]       ; 13.056 ; 13.058 ; 13.058 ; 13.056 ;
; ADR[4]       ; DATA[10]      ; 13.022 ; 12.940 ; 12.940 ; 13.022 ;
; ADR[4]       ; DATA[11]      ; 14.178 ; 14.178 ; 14.178 ; 14.178 ;
; ADR[4]       ; DATA[12]      ; 13.350 ; 13.350 ; 13.350 ; 13.350 ;
; ADR[4]       ; DATA[13]      ; 13.531 ; 13.531 ; 13.531 ; 13.531 ;
; ADR[4]       ; DATA[14]      ; 13.271 ; 13.271 ; 13.271 ; 13.271 ;
; ADR[4]       ; DATA[15]      ; 13.538 ; 13.538 ; 13.538 ; 13.538 ;
; ADR[4]       ; RAM_DATA[0]   ; 11.735 ; 11.738 ; 11.738 ; 11.735 ;
; ADR[4]       ; RAM_DATA[1]   ; 12.538 ; 12.540 ; 12.540 ; 12.538 ;
; ADR[4]       ; RAM_DATA[2]   ; 12.198 ; 12.116 ; 12.116 ; 12.198 ;
; ADR[4]       ; RAM_DATA[3]   ; 13.237 ; 13.237 ; 13.237 ; 13.237 ;
; ADR[4]       ; RAM_DATA[4]   ; 12.754 ; 12.754 ; 12.754 ; 12.754 ;
; ADR[4]       ; RAM_DATA[5]   ; 12.296 ; 12.296 ; 12.296 ; 12.296 ;
; ADR[4]       ; RAM_DATA[6]   ; 12.266 ; 12.266 ; 12.266 ; 12.266 ;
; ADR[4]       ; RAM_DATA[7]   ; 13.205 ; 13.205 ; 13.205 ; 13.205 ;
; ADR[4]       ; RAM_DATA[8]   ; 12.364 ; 12.367 ; 12.367 ; 12.364 ;
; ADR[4]       ; RAM_DATA[9]   ; 12.427 ; 12.429 ; 12.429 ; 12.427 ;
; ADR[4]       ; RAM_DATA[10]  ; 13.159 ; 13.077 ; 13.077 ; 13.159 ;
; ADR[4]       ; RAM_DATA[11]  ; 12.543 ; 12.543 ; 12.543 ; 12.543 ;
; ADR[4]       ; RAM_DATA[12]  ; 13.414 ; 13.414 ; 13.414 ; 13.414 ;
; ADR[4]       ; RAM_DATA[13]  ; 12.382 ; 12.382 ; 12.382 ; 12.382 ;
; ADR[4]       ; RAM_DATA[14]  ; 12.387 ; 12.387 ; 12.387 ; 12.387 ;
; ADR[4]       ; RAM_DATA[15]  ; 12.496 ; 12.496 ; 12.496 ; 12.496 ;
; ADR[5]       ; DATA[0]       ; 13.740 ; 13.600 ; 13.600 ; 13.740 ;
; ADR[5]       ; DATA[1]       ; 13.636 ; 13.497 ; 13.497 ; 13.636 ;
; ADR[5]       ; DATA[2]       ; 13.333 ; 13.001 ; 13.001 ; 13.333 ;
; ADR[5]       ; DATA[3]       ; 14.321 ; 14.321 ; 14.321 ; 14.321 ;
; ADR[5]       ; DATA[4]       ; 12.806 ; 12.806 ; 12.806 ; 12.806 ;
; ADR[5]       ; DATA[5]       ; 13.893 ; 13.893 ; 13.893 ; 13.893 ;
; ADR[5]       ; DATA[6]       ; 12.616 ; 12.616 ; 12.616 ; 12.616 ;
; ADR[5]       ; DATA[7]       ; 13.704 ; 13.704 ; 13.704 ; 13.704 ;
; ADR[5]       ; DATA[8]       ; 12.937 ; 12.797 ; 12.797 ; 12.937 ;
; ADR[5]       ; DATA[9]       ; 13.239 ; 13.100 ; 13.100 ; 13.239 ;
; ADR[5]       ; DATA[10]      ; 13.314 ; 12.982 ; 12.982 ; 13.314 ;
; ADR[5]       ; DATA[11]      ; 14.359 ; 14.359 ; 14.359 ; 14.359 ;
; ADR[5]       ; DATA[12]      ; 13.531 ; 13.531 ; 13.531 ; 13.531 ;
; ADR[5]       ; DATA[13]      ; 13.787 ; 13.712 ; 13.712 ; 13.787 ;
; ADR[5]       ; DATA[14]      ; 13.452 ; 13.452 ; 13.452 ; 13.452 ;
; ADR[5]       ; DATA[15]      ; 13.719 ; 13.719 ; 13.719 ; 13.719 ;
; ADR[5]       ; RAM_DATA[0]   ; 11.919 ; 11.779 ; 11.779 ; 11.919 ;
; ADR[5]       ; RAM_DATA[1]   ; 12.721 ; 12.582 ; 12.582 ; 12.721 ;
; ADR[5]       ; RAM_DATA[2]   ; 12.490 ; 12.158 ; 12.158 ; 12.490 ;
; ADR[5]       ; RAM_DATA[3]   ; 13.418 ; 13.418 ; 13.418 ; 13.418 ;
; ADR[5]       ; RAM_DATA[4]   ; 12.935 ; 12.935 ; 12.935 ; 12.935 ;
; ADR[5]       ; RAM_DATA[5]   ; 12.552 ; 12.552 ; 12.552 ; 12.552 ;
; ADR[5]       ; RAM_DATA[6]   ; 12.447 ; 12.447 ; 12.447 ; 12.447 ;
; ADR[5]       ; RAM_DATA[7]   ; 13.386 ; 13.386 ; 13.386 ; 13.386 ;
; ADR[5]       ; RAM_DATA[8]   ; 12.548 ; 12.408 ; 12.408 ; 12.548 ;
; ADR[5]       ; RAM_DATA[9]   ; 12.610 ; 12.471 ; 12.471 ; 12.610 ;
; ADR[5]       ; RAM_DATA[10]  ; 13.451 ; 13.119 ; 13.119 ; 13.451 ;
; ADR[5]       ; RAM_DATA[11]  ; 12.724 ; 12.724 ; 12.724 ; 12.724 ;
; ADR[5]       ; RAM_DATA[12]  ; 13.595 ; 13.595 ; 13.595 ; 13.595 ;
; ADR[5]       ; RAM_DATA[13]  ; 12.638 ; 12.563 ; 12.563 ; 12.638 ;
; ADR[5]       ; RAM_DATA[14]  ; 12.568 ; 12.568 ; 12.568 ; 12.568 ;
; ADR[5]       ; RAM_DATA[15]  ; 12.677 ; 12.677 ; 12.677 ; 12.677 ;
; ASn          ; ACSI_RDn      ; 10.109 ; 10.109 ; 10.109 ; 10.109 ;
; ASn          ; ACSI_WRn      ; 10.099 ; 10.099 ; 10.099 ; 10.099 ;
; ASn          ; ASn           ; 12.860 ; 12.860 ; 12.860 ; 12.860 ;
; ASn          ; BUTTONn       ; 8.032  ;        ;        ; 8.032  ;
; ASn          ; CA1_OUT       ; 9.144  ;        ;        ; 9.144  ;
; ASn          ; CD[0]         ; 12.279 ; 12.279 ; 12.279 ; 12.279 ;
; ASn          ; CD[1]         ; 12.049 ; 12.049 ; 12.049 ; 12.049 ;
; ASn          ; CD[2]         ; 11.825 ; 11.825 ; 11.825 ; 11.825 ;
; ASn          ; CD[3]         ; 12.475 ; 12.475 ; 12.475 ; 12.475 ;
; ASn          ; CD[4]         ; 12.003 ; 12.003 ; 12.003 ; 12.003 ;
; ASn          ; CD[5]         ; 11.652 ; 11.652 ; 11.652 ; 11.652 ;
; ASn          ; CD[6]         ; 12.804 ; 12.804 ; 12.804 ; 12.804 ;
; ASn          ; CD[7]         ; 11.862 ; 11.862 ; 11.862 ; 11.862 ;
; ASn          ; DATA[0]       ; 16.883 ; 16.883 ; 16.883 ; 16.883 ;
; ASn          ; DATA[1]       ; 15.934 ; 15.934 ; 15.934 ; 15.934 ;
; ASn          ; DATA[2]       ; 16.069 ; 16.175 ; 16.175 ; 16.069 ;
; ASn          ; DATA[3]       ; 16.366 ; 16.366 ; 16.366 ; 16.366 ;
; ASn          ; DATA[4]       ; 15.634 ; 15.634 ; 15.634 ; 15.634 ;
; ASn          ; DATA[5]       ; 16.575 ; 16.575 ; 16.575 ; 16.575 ;
; ASn          ; DATA[6]       ; 15.434 ; 15.434 ; 15.434 ; 15.434 ;
; ASn          ; DATA[7]       ; 16.260 ; 16.260 ; 16.260 ; 16.260 ;
; ASn          ; DATA[8]       ; 15.745 ; 15.745 ; 15.745 ; 15.745 ;
; ASn          ; DATA[9]       ; 15.839 ; 16.028 ; 16.028 ; 15.839 ;
; ASn          ; DATA[10]      ; 15.725 ; 15.725 ; 15.725 ; 15.725 ;
; ASn          ; DATA[11]      ; 17.282 ; 16.909 ; 16.909 ; 17.282 ;
; ASn          ; DATA[12]      ; 15.773 ; 15.933 ; 15.933 ; 15.773 ;
; ASn          ; DATA[13]      ; 16.139 ; 16.382 ; 16.382 ; 16.139 ;
; ASn          ; DATA[14]      ; 15.263 ; 15.263 ; 15.263 ; 15.263 ;
; ASn          ; DATA[15]      ; 15.583 ; 15.583 ; 15.583 ; 15.583 ;
; ASn          ; DTACKn        ; 13.132 ; 13.132 ; 13.132 ; 13.132 ;
; ASn          ; FC[0]         ; 13.141 ; 13.141 ; 13.141 ; 13.141 ;
; ASn          ; FC[1]         ; 12.949 ; 12.949 ; 12.949 ; 12.949 ;
; ASn          ; FC[2]         ; 12.949 ; 12.949 ; 12.949 ; 12.949 ;
; ASn          ; FLASH_CEn     ; 9.331  ;        ;        ; 9.331  ;
; ASn          ; FLASH_OEn     ; 9.829  ;        ;        ; 9.829  ;
; ASn          ; IDE_CS0n      ; 7.334  ;        ;        ; 7.334  ;
; ASn          ; IDE_CS1n      ; 7.227  ;        ;        ; 7.227  ;
; ASn          ; IDE_D_EN_INn  ; 7.462  ;        ;        ; 7.462  ;
; ASn          ; IDE_D_EN_OUTn ; 7.242  ;        ;        ; 7.242  ;
; ASn          ; IDE_IORDn     ; 7.286  ;        ;        ; 7.286  ;
; ASn          ; IDE_IOWRn     ; 7.291  ;        ;        ; 7.291  ;
; ASn          ; JOY_RHn       ; 7.234  ;        ;        ; 7.234  ;
; ASn          ; JOY_RLn       ; 8.141  ;        ;        ; 8.141  ;
; ASn          ; JOY_WEn       ;        ; 8.113  ; 8.113  ;        ;
; ASn          ; JOY_WL        ;        ; 6.955  ; 6.955  ;        ;
; ASn          ; LDSn          ; 13.327 ; 13.327 ; 13.327 ; 13.327 ;
; ASn          ; RAM_DATA[0]   ; 15.062 ; 15.062 ; 15.062 ; 15.062 ;
; ASn          ; RAM_DATA[1]   ; 15.019 ; 15.019 ; 15.019 ; 15.019 ;
; ASn          ; RAM_DATA[2]   ; 15.226 ; 15.332 ; 15.332 ; 15.226 ;
; ASn          ; RAM_DATA[3]   ; 15.463 ; 15.463 ; 15.463 ; 15.463 ;
; ASn          ; RAM_DATA[4]   ; 15.763 ; 15.763 ; 15.763 ; 15.763 ;
; ASn          ; RAM_DATA[5]   ; 15.234 ; 15.234 ; 15.234 ; 15.234 ;
; ASn          ; RAM_DATA[6]   ; 15.265 ; 15.265 ; 15.265 ; 15.265 ;
; ASn          ; RAM_DATA[7]   ; 15.942 ; 15.942 ; 15.942 ; 15.942 ;
; ASn          ; RAM_DATA[8]   ; 15.356 ; 15.356 ; 15.356 ; 15.356 ;
; ASn          ; RAM_DATA[9]   ; 15.210 ; 15.399 ; 15.399 ; 15.210 ;
; ASn          ; RAM_DATA[10]  ; 15.862 ; 15.862 ; 15.862 ; 15.862 ;
; ASn          ; RAM_DATA[11]  ; 15.647 ; 15.274 ; 15.274 ; 15.647 ;
; ASn          ; RAM_DATA[12]  ; 15.837 ; 15.997 ; 15.997 ; 15.837 ;
; ASn          ; RAM_DATA[13]  ; 14.990 ; 15.233 ; 15.233 ; 14.990 ;
; ASn          ; RAM_DATA[14]  ; 14.379 ; 14.379 ; 14.379 ; 14.379 ;
; ASn          ; RAM_DATA[15]  ; 14.541 ; 14.541 ; 14.541 ; 14.541 ;
; ASn          ; ROM0n         ; 8.356  ;        ;        ; 8.356  ;
; ASn          ; ROM1n         ; 9.187  ;        ;        ; 9.187  ;
; ASn          ; ROM2n         ; 8.505  ;        ;        ; 8.505  ;
; ASn          ; ROM3n         ; 8.015  ;        ;        ; 8.015  ;
; ASn          ; ROM4n         ; 7.827  ;        ;        ; 7.827  ;
; ASn          ; ROM5n         ; 9.036  ;        ;        ; 9.036  ;
; ASn          ; ROM6n         ; 8.250  ;        ;        ; 8.250  ;
; ASn          ; RWn           ; 13.423 ; 13.423 ; 13.423 ; 13.423 ;
; ASn          ; UDSn          ; 13.327 ; 13.327 ; 13.327 ; 13.327 ;
; CD[0]        ; DATA[0]       ; 10.525 ;        ;        ; 10.525 ;
; CD[0]        ; RAM_DATA[0]   ; 8.704  ;        ;        ; 8.704  ;
; CD[1]        ; DATA[1]       ; 10.216 ;        ;        ; 10.216 ;
; CD[1]        ; RAM_DATA[1]   ; 9.301  ;        ;        ; 9.301  ;
; CD[2]        ; DATA[2]       ; 10.162 ;        ;        ; 10.162 ;
; CD[2]        ; RAM_DATA[2]   ; 9.319  ;        ;        ; 9.319  ;
; CD[3]        ; DATA[3]       ; 10.805 ;        ;        ; 10.805 ;
; CD[3]        ; RAM_DATA[3]   ; 9.902  ;        ;        ; 9.902  ;
; CD[4]        ; DATA[4]       ; 9.384  ; 9.384  ; 9.384  ; 9.384  ;
; CD[4]        ; RAM_DATA[4]   ; 9.513  ; 9.513  ; 9.513  ; 9.513  ;
; CD[5]        ; DATA[5]       ; 10.227 ; 10.227 ; 10.227 ; 10.227 ;
; CD[5]        ; RAM_DATA[5]   ; 8.886  ; 8.886  ; 8.886  ; 8.886  ;
; CD[6]        ; DATA[6]       ; 10.225 ; 10.225 ; 10.225 ; 10.225 ;
; CD[6]        ; RAM_DATA[6]   ; 10.056 ; 10.056 ; 10.056 ; 10.056 ;
; CD[7]        ; DATA[7]       ; 10.825 ; 10.825 ; 10.825 ; 10.825 ;
; CD[7]        ; RAM_DATA[7]   ; 10.507 ; 10.507 ; 10.507 ; 10.507 ;
; COM_DCD      ; DATA[1]       ;        ; 11.516 ; 11.516 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 11.119 ; 11.119 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 10.601 ; 10.601 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 10.490 ; 10.490 ;        ;
; COM_RI       ; DATA[6]       ; 11.269 ; 11.269 ; 11.269 ; 11.269 ;
; COM_RI       ; DATA[14]      ; 12.105 ; 12.105 ; 12.105 ; 12.105 ;
; COM_RI       ; RAM_DATA[6]   ; 11.100 ; 11.100 ; 11.100 ; 11.100 ;
; COM_RI       ; RAM_DATA[14]  ; 11.221 ; 11.221 ; 11.221 ; 11.221 ;
; CONFIG[1]    ; DATA[15]      ; 11.093 ; 11.093 ; 11.093 ; 11.093 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 10.051 ; 10.051 ; 10.051 ; 10.051 ;
; CONFIG[2]    ; DATA[14]      ; 10.751 ; 10.751 ; 10.751 ; 10.751 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 9.867  ; 9.867  ; 9.867  ; 9.867  ;
; CONFIG[5]    ; ACSI_RDn      ; 11.097 ; 11.097 ; 11.097 ; 11.097 ;
; CONFIG[5]    ; ACSI_WRn      ; 11.087 ; 11.087 ; 11.087 ; 11.087 ;
; CONFIG[5]    ; ASn           ; 13.419 ; 13.419 ; 13.419 ; 13.419 ;
; CONFIG[5]    ; BUTTONn       ; 10.401 ; 9.445  ; 9.445  ; 10.401 ;
; CONFIG[5]    ; CA1_OUT       ; 10.132 ; 9.176  ; 9.176  ; 10.132 ;
; CONFIG[5]    ; CD[0]         ; 13.267 ; 13.267 ; 13.267 ; 13.267 ;
; CONFIG[5]    ; CD[1]         ; 13.037 ; 13.037 ; 13.037 ; 13.037 ;
; CONFIG[5]    ; CD[2]         ; 12.813 ; 12.813 ; 12.813 ; 12.813 ;
; CONFIG[5]    ; CD[3]         ; 13.463 ; 13.463 ; 13.463 ; 13.463 ;
; CONFIG[5]    ; CD[4]         ; 12.991 ; 12.991 ; 12.991 ; 12.991 ;
; CONFIG[5]    ; CD[5]         ; 12.640 ; 12.640 ; 12.640 ; 12.640 ;
; CONFIG[5]    ; CD[6]         ; 13.792 ; 13.792 ; 13.792 ; 13.792 ;
; CONFIG[5]    ; CD[7]         ; 12.850 ; 12.850 ; 12.850 ; 12.850 ;
; CONFIG[5]    ; DATA[0]       ; 17.513 ; 17.511 ; 17.511 ; 17.513 ;
; CONFIG[5]    ; DATA[1]       ; 17.365 ; 17.365 ; 17.365 ; 17.365 ;
; CONFIG[5]    ; DATA[2]       ; 16.961 ; 16.887 ; 16.887 ; 16.961 ;
; CONFIG[5]    ; DATA[3]       ; 16.902 ; 17.026 ; 17.026 ; 16.902 ;
; CONFIG[5]    ; DATA[4]       ; 16.369 ; 16.369 ; 16.369 ; 16.369 ;
; CONFIG[5]    ; DATA[5]       ; 18.006 ; 18.006 ; 18.006 ; 18.006 ;
; CONFIG[5]    ; DATA[6]       ; 16.717 ; 16.717 ; 16.717 ; 16.717 ;
; CONFIG[5]    ; DATA[7]       ; 16.883 ; 16.883 ; 16.883 ; 16.883 ;
; CONFIG[5]    ; DATA[8]       ; 16.459 ; 16.459 ; 16.459 ; 16.459 ;
; CONFIG[5]    ; DATA[9]       ; 17.138 ; 16.901 ; 16.901 ; 17.138 ;
; CONFIG[5]    ; DATA[10]      ; 17.156 ; 17.156 ; 17.156 ; 17.156 ;
; CONFIG[5]    ; DATA[11]      ; 18.713 ; 18.192 ; 18.192 ; 18.713 ;
; CONFIG[5]    ; DATA[12]      ; 16.753 ; 16.384 ; 16.384 ; 16.753 ;
; CONFIG[5]    ; DATA[13]      ; 17.505 ; 17.148 ; 17.148 ; 17.505 ;
; CONFIG[5]    ; DATA[14]      ; 16.809 ; 16.809 ; 16.809 ; 16.809 ;
; CONFIG[5]    ; DATA[15]      ; 16.866 ; 16.866 ; 16.866 ; 16.866 ;
; CONFIG[5]    ; DTACKn        ; 14.905 ; 14.905 ; 14.905 ; 14.905 ;
; CONFIG[5]    ; FC[0]         ; 13.700 ; 13.700 ; 13.700 ; 13.700 ;
; CONFIG[5]    ; FC[1]         ; 13.508 ; 13.508 ; 13.508 ; 13.508 ;
; CONFIG[5]    ; FC[2]         ; 13.508 ; 13.508 ; 13.508 ; 13.508 ;
; CONFIG[5]    ; FLASH_CEn     ; 11.393 ; 11.324 ; 11.324 ; 11.393 ;
; CONFIG[5]    ; FLASH_OEn     ; 11.891 ; 11.822 ; 11.822 ; 11.891 ;
; CONFIG[5]    ; IDE_CS0n      ; 10.736 ; 9.706  ; 9.706  ; 10.736 ;
; CONFIG[5]    ; IDE_CS1n      ; 10.406 ; 9.376  ; 9.376  ; 10.406 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 10.543 ; 9.513  ; 9.513  ; 10.543 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 10.451 ; 9.421  ; 9.421  ; 10.451 ;
; CONFIG[5]    ; IDE_IORDn     ; 10.152 ; 9.122  ; 9.122  ; 10.152 ;
; CONFIG[5]    ; IDE_IOWRn     ; 11.323 ; 10.293 ; 10.293 ; 11.323 ;
; CONFIG[5]    ; JOY_RHn       ; 10.260 ; 9.304  ; 9.304  ; 10.260 ;
; CONFIG[5]    ; JOY_RLn       ; 11.167 ; 10.211 ; 10.211 ; 11.167 ;
; CONFIG[5]    ; JOY_WEn       ; 10.183 ; 11.139 ; 11.139 ; 10.183 ;
; CONFIG[5]    ; JOY_WL        ; 9.025  ; 9.981  ; 9.981  ; 9.025  ;
; CONFIG[5]    ; LDSn          ; 13.886 ; 13.886 ; 13.886 ; 13.886 ;
; CONFIG[5]    ; RAM_BA[1]     ; 8.326  ; 9.785  ; 9.785  ; 8.326  ;
; CONFIG[5]    ; RAM_CAS0n     ; 8.188  ; 9.011  ; 9.011  ; 8.188  ;
; CONFIG[5]    ; RAM_CAS1n     ; 8.599  ; 7.776  ; 7.776  ; 8.599  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 15.692 ; 15.690 ; 15.690 ; 15.692 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 16.450 ; 16.450 ; 16.450 ; 16.450 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 16.118 ; 16.044 ; 16.044 ; 16.118 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 15.999 ; 16.123 ; 16.123 ; 15.999 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 16.498 ; 16.498 ; 16.498 ; 16.498 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 16.665 ; 16.665 ; 16.665 ; 16.665 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 16.548 ; 16.548 ; 16.548 ; 16.548 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 16.565 ; 16.565 ; 16.565 ; 16.565 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 16.070 ; 16.070 ; 16.070 ; 16.070 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 16.509 ; 16.272 ; 16.272 ; 16.509 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 17.293 ; 17.293 ; 17.293 ; 17.293 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 17.078 ; 16.557 ; 16.557 ; 17.078 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 16.817 ; 16.448 ; 16.448 ; 16.817 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 16.356 ; 15.999 ; 15.999 ; 16.356 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 15.925 ; 15.925 ; 15.925 ; 15.925 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 15.824 ; 15.824 ; 15.824 ; 15.824 ;
; CONFIG[5]    ; RAM_RAS0n     ; 8.996  ; 10.026 ; 10.026 ; 8.996  ;
; CONFIG[5]    ; RAM_RAS1n     ; 9.868  ; 8.838  ; 8.838  ; 9.868  ;
; CONFIG[5]    ; ROM0n         ; 10.368 ; 9.330  ; 9.330  ; 10.368 ;
; CONFIG[5]    ; ROM1n         ; 11.199 ; 10.161 ; 10.161 ; 11.199 ;
; CONFIG[5]    ; ROM2n         ; 10.567 ; 10.498 ; 10.498 ; 10.567 ;
; CONFIG[5]    ; ROM3n         ; 11.674 ; 10.644 ; 10.644 ; 11.674 ;
; CONFIG[5]    ; ROM4n         ; 11.482 ; 10.452 ; 10.452 ; 11.482 ;
; CONFIG[5]    ; ROM5n         ; 11.048 ; 10.010 ; 10.010 ; 11.048 ;
; CONFIG[5]    ; ROM6n         ; 11.909 ; 10.879 ; 10.879 ; 11.909 ;
; CONFIG[5]    ; RWn           ; 13.982 ; 13.982 ; 13.982 ; 13.982 ;
; CONFIG[5]    ; UDSn          ; 13.886 ; 13.886 ; 13.886 ; 13.886 ;
; DATA[0]      ; DATA[0]       ; 10.186 ;        ;        ; 10.186 ;
; DATA[0]      ; RAM_DATA[0]   ; 8.365  ;        ;        ; 8.365  ;
; DATA[1]      ; DATA[1]       ; 10.029 ;        ;        ; 10.029 ;
; DATA[1]      ; RAM_DATA[1]   ; 9.114  ;        ;        ; 9.114  ;
; DATA[2]      ; DATA[2]       ; 9.915  ;        ;        ; 9.915  ;
; DATA[2]      ; RAM_DATA[2]   ; 9.072  ;        ;        ; 9.072  ;
; DATA[3]      ; DATA[3]       ; 9.928  ;        ;        ; 9.928  ;
; DATA[3]      ; RAM_DATA[3]   ; 9.025  ;        ;        ; 9.025  ;
; DATA[4]      ; DATA[4]       ; 8.020  ; 8.020  ; 8.020  ; 8.020  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.149  ; 8.149  ; 8.149  ; 8.149  ;
; DATA[5]      ; DATA[5]       ; 9.476  ;        ;        ; 9.476  ;
; DATA[5]      ; RAM_DATA[5]   ; 8.135  ;        ;        ; 8.135  ;
; DATA[6]      ; DATA[6]       ; 8.593  ; 8.593  ; 8.593  ; 8.593  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.424  ; 8.424  ; 8.424  ; 8.424  ;
; DATA[7]      ; DATA[7]       ; 8.852  ;        ;        ; 8.852  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.534  ;        ;        ; 8.534  ;
; DATA[8]      ; DATA[8]       ; 9.181  ;        ;        ; 9.181  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.792  ;        ;        ; 8.792  ;
; DATA[9]      ; DATA[9]       ; 9.777  ;        ;        ; 9.777  ;
; DATA[9]      ; RAM_DATA[9]   ; 9.148  ;        ;        ; 9.148  ;
; DATA[10]     ; DATA[10]      ; 9.285  ;        ;        ; 9.285  ;
; DATA[10]     ; RAM_DATA[10]  ; 9.422  ;        ;        ; 9.422  ;
; DATA[11]     ; DATA[11]      ; 10.318 ;        ;        ; 10.318 ;
; DATA[11]     ; RAM_DATA[11]  ; 8.683  ;        ;        ; 8.683  ;
; DATA[12]     ; DATA[12]      ; 10.150 ;        ;        ; 10.150 ;
; DATA[12]     ; RAM_DATA[12]  ; 10.214 ;        ;        ; 10.214 ;
; DATA[13]     ; DATA[13]      ; 10.383 ;        ;        ; 10.383 ;
; DATA[13]     ; RAM_DATA[13]  ; 9.234  ;        ;        ; 9.234  ;
; DATA[14]     ; DATA[14]      ; 7.943  ;        ;        ; 7.943  ;
; DATA[14]     ; RAM_DATA[14]  ; 7.059  ;        ;        ; 7.059  ;
; DATA[15]     ; DATA[15]      ; 8.165  ;        ;        ; 8.165  ;
; DATA[15]     ; RAM_DATA[15]  ; 7.123  ;        ;        ; 7.123  ;
; FC[0]        ; ACSI_RDn      ; 9.938  ; 9.938  ; 9.938  ; 9.938  ;
; FC[0]        ; ACSI_WRn      ; 9.928  ; 9.928  ; 9.928  ; 9.928  ;
; FC[0]        ; ASn           ; 12.689 ; 12.689 ; 12.689 ; 12.689 ;
; FC[0]        ; BUTTONn       ; 8.829  ; 8.544  ; 8.544  ; 8.829  ;
; FC[0]        ; CA1_OUT       ; 8.973  ; 7.843  ; 7.843  ; 8.973  ;
; FC[0]        ; CD[0]         ; 12.108 ; 12.108 ; 12.108 ; 12.108 ;
; FC[0]        ; CD[1]         ; 11.878 ; 11.878 ; 11.878 ; 11.878 ;
; FC[0]        ; CD[2]         ; 11.654 ; 11.654 ; 11.654 ; 11.654 ;
; FC[0]        ; CD[3]         ; 12.304 ; 12.304 ; 12.304 ; 12.304 ;
; FC[0]        ; CD[4]         ; 11.832 ; 11.832 ; 11.832 ; 11.832 ;
; FC[0]        ; CD[5]         ; 11.481 ; 11.481 ; 11.481 ; 11.481 ;
; FC[0]        ; CD[6]         ; 12.633 ; 12.633 ; 12.633 ; 12.633 ;
; FC[0]        ; CD[7]         ; 11.691 ; 11.691 ; 11.691 ; 11.691 ;
; FC[0]        ; DATA[0]       ; 16.712 ; 16.712 ; 16.712 ; 16.712 ;
; FC[0]        ; DATA[1]       ; 16.731 ; 16.731 ; 16.731 ; 16.731 ;
; FC[0]        ; DATA[2]       ; 16.352 ; 16.352 ; 16.352 ; 16.352 ;
; FC[0]        ; DATA[3]       ; 16.352 ; 16.392 ; 16.392 ; 16.352 ;
; FC[0]        ; DATA[4]       ; 15.883 ; 15.883 ; 15.883 ; 15.883 ;
; FC[0]        ; DATA[5]       ; 17.372 ; 17.372 ; 17.372 ; 17.372 ;
; FC[0]        ; DATA[6]       ; 16.231 ; 16.231 ; 16.231 ; 16.231 ;
; FC[0]        ; DATA[7]       ; 16.333 ; 16.333 ; 16.333 ; 16.333 ;
; FC[0]        ; DATA[8]       ; 15.973 ; 15.973 ; 15.973 ; 15.973 ;
; FC[0]        ; DATA[9]       ; 16.504 ; 16.464 ; 16.464 ; 16.504 ;
; FC[0]        ; DATA[10]      ; 16.522 ; 16.522 ; 16.522 ; 16.522 ;
; FC[0]        ; DATA[11]      ; 18.079 ; 18.039 ; 18.039 ; 18.079 ;
; FC[0]        ; DATA[12]      ; 16.119 ; 16.079 ; 16.079 ; 16.119 ;
; FC[0]        ; DATA[13]      ; 16.638 ; 16.598 ; 16.598 ; 16.638 ;
; FC[0]        ; DATA[14]      ; 16.060 ; 16.060 ; 16.060 ; 16.060 ;
; FC[0]        ; DATA[15]      ; 16.380 ; 16.380 ; 16.380 ; 16.380 ;
; FC[0]        ; DTACKn        ; 12.961 ; 12.961 ; 12.961 ; 12.961 ;
; FC[0]        ; FC[0]         ; 12.970 ; 12.970 ; 12.970 ; 12.970 ;
; FC[0]        ; FC[1]         ; 12.778 ; 12.778 ; 12.778 ; 12.778 ;
; FC[0]        ; FC[2]         ; 12.778 ; 12.778 ; 12.778 ; 12.778 ;
; FC[0]        ; FLASH_CEn     ; 10.128 ; 10.027 ; 10.027 ; 10.128 ;
; FC[0]        ; FLASH_OEn     ; 10.626 ; 10.525 ; 10.525 ; 10.626 ;
; FC[0]        ; IDE_CS0n      ; 8.131  ;        ;        ; 8.131  ;
; FC[0]        ; IDE_CS1n      ; 8.024  ;        ;        ; 8.024  ;
; FC[0]        ; IDE_D_EN_INn  ; 8.259  ;        ;        ; 8.259  ;
; FC[0]        ; IDE_D_EN_OUTn ; 8.039  ;        ;        ; 8.039  ;
; FC[0]        ; IDE_IORDn     ; 8.083  ;        ;        ; 8.083  ;
; FC[0]        ; IDE_IOWRn     ; 8.088  ;        ;        ; 8.088  ;
; FC[0]        ; JOY_RHn       ; 8.430  ; 8.430  ; 8.430  ; 8.430  ;
; FC[0]        ; JOY_RLn       ; 9.347  ; 9.347  ; 9.347  ; 9.347  ;
; FC[0]        ; JOY_WEn       ; 9.319  ; 9.319  ; 9.319  ; 9.319  ;
; FC[0]        ; JOY_WL        ; 8.096  ; 8.096  ; 8.096  ; 8.096  ;
; FC[0]        ; LDSn          ; 13.156 ; 13.156 ; 13.156 ; 13.156 ;
; FC[0]        ; RAM_DATA[0]   ; 14.891 ; 14.891 ; 14.891 ; 14.891 ;
; FC[0]        ; RAM_DATA[1]   ; 15.816 ; 15.816 ; 15.816 ; 15.816 ;
; FC[0]        ; RAM_DATA[2]   ; 15.509 ; 15.509 ; 15.509 ; 15.509 ;
; FC[0]        ; RAM_DATA[3]   ; 15.449 ; 15.489 ; 15.489 ; 15.449 ;
; FC[0]        ; RAM_DATA[4]   ; 16.012 ; 16.012 ; 16.012 ; 16.012 ;
; FC[0]        ; RAM_DATA[5]   ; 16.031 ; 16.031 ; 16.031 ; 16.031 ;
; FC[0]        ; RAM_DATA[6]   ; 16.062 ; 16.062 ; 16.062 ; 16.062 ;
; FC[0]        ; RAM_DATA[7]   ; 16.015 ; 16.015 ; 16.015 ; 16.015 ;
; FC[0]        ; RAM_DATA[8]   ; 15.584 ; 15.584 ; 15.584 ; 15.584 ;
; FC[0]        ; RAM_DATA[9]   ; 15.875 ; 15.835 ; 15.835 ; 15.875 ;
; FC[0]        ; RAM_DATA[10]  ; 16.659 ; 16.659 ; 16.659 ; 16.659 ;
; FC[0]        ; RAM_DATA[11]  ; 16.444 ; 16.404 ; 16.404 ; 16.444 ;
; FC[0]        ; RAM_DATA[12]  ; 16.183 ; 16.143 ; 16.143 ; 16.183 ;
; FC[0]        ; RAM_DATA[13]  ; 15.489 ; 15.449 ; 15.449 ; 15.489 ;
; FC[0]        ; RAM_DATA[14]  ; 15.176 ; 15.176 ; 15.176 ; 15.176 ;
; FC[0]        ; RAM_DATA[15]  ; 15.338 ; 15.338 ; 15.338 ; 15.338 ;
; FC[0]        ; ROM0n         ; 9.153  ; 8.927  ; 8.927  ; 9.153  ;
; FC[0]        ; ROM1n         ; 9.984  ; 9.758  ; 9.758  ; 9.984  ;
; FC[0]        ; ROM2n         ; 9.302  ; 9.201  ; 9.201  ; 9.302  ;
; FC[0]        ; ROM3n         ; 8.812  ; 8.711  ; 8.711  ; 8.812  ;
; FC[0]        ; ROM4n         ; 8.624  ; 8.523  ; 8.523  ; 8.624  ;
; FC[0]        ; ROM5n         ; 9.833  ; 9.607  ; 9.607  ; 9.833  ;
; FC[0]        ; ROM6n         ; 9.047  ; 8.946  ; 8.946  ; 9.047  ;
; FC[0]        ; RWn           ; 13.252 ; 13.252 ; 13.252 ; 13.252 ;
; FC[0]        ; UDSn          ; 13.156 ; 13.156 ; 13.156 ; 13.156 ;
; FC[1]        ; ACSI_RDn      ; 10.060 ; 10.060 ; 10.060 ; 10.060 ;
; FC[1]        ; ACSI_WRn      ; 10.050 ; 10.050 ; 10.050 ; 10.050 ;
; FC[1]        ; ASn           ; 12.811 ; 12.811 ; 12.811 ; 12.811 ;
; FC[1]        ; BUTTONn       ; 8.634  ; 7.774  ; 7.774  ; 8.634  ;
; FC[1]        ; CA1_OUT       ; 9.095  ; 7.972  ; 7.972  ; 9.095  ;
; FC[1]        ; CD[0]         ; 12.230 ; 12.230 ; 12.230 ; 12.230 ;
; FC[1]        ; CD[1]         ; 12.000 ; 12.000 ; 12.000 ; 12.000 ;
; FC[1]        ; CD[2]         ; 11.776 ; 11.776 ; 11.776 ; 11.776 ;
; FC[1]        ; CD[3]         ; 12.426 ; 12.426 ; 12.426 ; 12.426 ;
; FC[1]        ; CD[4]         ; 11.954 ; 11.954 ; 11.954 ; 11.954 ;
; FC[1]        ; CD[5]         ; 11.603 ; 11.603 ; 11.603 ; 11.603 ;
; FC[1]        ; CD[6]         ; 12.755 ; 12.755 ; 12.755 ; 12.755 ;
; FC[1]        ; CD[7]         ; 11.813 ; 11.813 ; 11.813 ; 11.813 ;
; FC[1]        ; DATA[0]       ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; FC[1]        ; DATA[1]       ; 16.536 ; 16.536 ; 16.536 ; 16.536 ;
; FC[1]        ; DATA[2]       ; 16.157 ; 16.157 ; 16.157 ; 16.157 ;
; FC[1]        ; DATA[3]       ; 16.317 ; 16.317 ; 16.317 ; 16.317 ;
; FC[1]        ; DATA[4]       ; 15.688 ; 15.688 ; 15.688 ; 15.688 ;
; FC[1]        ; DATA[5]       ; 17.177 ; 17.177 ; 17.177 ; 17.177 ;
; FC[1]        ; DATA[6]       ; 16.036 ; 16.036 ; 16.036 ; 16.036 ;
; FC[1]        ; DATA[7]       ; 16.211 ; 16.211 ; 16.211 ; 16.211 ;
; FC[1]        ; DATA[8]       ; 15.778 ; 15.778 ; 15.778 ; 15.778 ;
; FC[1]        ; DATA[9]       ; 16.309 ; 16.269 ; 16.269 ; 16.309 ;
; FC[1]        ; DATA[10]      ; 16.327 ; 16.327 ; 16.327 ; 16.327 ;
; FC[1]        ; DATA[11]      ; 17.884 ; 17.844 ; 17.844 ; 17.884 ;
; FC[1]        ; DATA[12]      ; 15.924 ; 15.884 ; 15.884 ; 15.924 ;
; FC[1]        ; DATA[13]      ; 16.443 ; 16.403 ; 16.403 ; 16.443 ;
; FC[1]        ; DATA[14]      ; 15.865 ; 15.865 ; 15.865 ; 15.865 ;
; FC[1]        ; DATA[15]      ; 16.185 ; 16.185 ; 16.185 ; 16.185 ;
; FC[1]        ; DTACKn        ; 13.083 ; 13.083 ; 13.083 ; 13.083 ;
; FC[1]        ; FC[0]         ; 13.092 ; 13.092 ; 13.092 ; 13.092 ;
; FC[1]        ; FC[1]         ; 12.900 ; 12.900 ; 12.900 ; 12.900 ;
; FC[1]        ; FC[2]         ; 12.900 ; 12.900 ; 12.900 ; 12.900 ;
; FC[1]        ; FLASH_CEn     ; 9.933  ; 9.257  ; 9.257  ; 9.933  ;
; FC[1]        ; FLASH_OEn     ; 10.431 ; 9.755  ; 9.755  ; 10.431 ;
; FC[1]        ; IDE_CS0n      ; 7.936  ;        ;        ; 7.936  ;
; FC[1]        ; IDE_CS1n      ; 7.829  ;        ;        ; 7.829  ;
; FC[1]        ; IDE_D_EN_INn  ; 8.064  ;        ;        ; 8.064  ;
; FC[1]        ; IDE_D_EN_OUTn ; 7.844  ;        ;        ; 7.844  ;
; FC[1]        ; IDE_IORDn     ; 7.888  ;        ;        ; 7.888  ;
; FC[1]        ; IDE_IOWRn     ; 7.893  ;        ;        ; 7.893  ;
; FC[1]        ; JOY_RHn       ; 8.235  ; 8.235  ; 8.235  ; 8.235  ;
; FC[1]        ; JOY_RLn       ; 9.152  ; 9.152  ; 9.152  ; 9.152  ;
; FC[1]        ; JOY_WEn       ; 9.124  ; 9.124  ; 9.124  ; 9.124  ;
; FC[1]        ; JOY_WL        ; 7.901  ; 7.901  ; 7.901  ; 7.901  ;
; FC[1]        ; LDSn          ; 13.278 ; 13.278 ; 13.278 ; 13.278 ;
; FC[1]        ; RAM_DATA[0]   ; 15.013 ; 15.013 ; 15.013 ; 15.013 ;
; FC[1]        ; RAM_DATA[1]   ; 15.621 ; 15.621 ; 15.621 ; 15.621 ;
; FC[1]        ; RAM_DATA[2]   ; 15.314 ; 15.314 ; 15.314 ; 15.314 ;
; FC[1]        ; RAM_DATA[3]   ; 15.414 ; 15.414 ; 15.414 ; 15.414 ;
; FC[1]        ; RAM_DATA[4]   ; 15.817 ; 15.817 ; 15.817 ; 15.817 ;
; FC[1]        ; RAM_DATA[5]   ; 15.836 ; 15.836 ; 15.836 ; 15.836 ;
; FC[1]        ; RAM_DATA[6]   ; 15.867 ; 15.867 ; 15.867 ; 15.867 ;
; FC[1]        ; RAM_DATA[7]   ; 15.893 ; 15.893 ; 15.893 ; 15.893 ;
; FC[1]        ; RAM_DATA[8]   ; 15.389 ; 15.389 ; 15.389 ; 15.389 ;
; FC[1]        ; RAM_DATA[9]   ; 15.680 ; 15.640 ; 15.640 ; 15.680 ;
; FC[1]        ; RAM_DATA[10]  ; 16.464 ; 16.464 ; 16.464 ; 16.464 ;
; FC[1]        ; RAM_DATA[11]  ; 16.249 ; 16.209 ; 16.209 ; 16.249 ;
; FC[1]        ; RAM_DATA[12]  ; 15.988 ; 15.948 ; 15.948 ; 15.988 ;
; FC[1]        ; RAM_DATA[13]  ; 15.294 ; 15.254 ; 15.254 ; 15.294 ;
; FC[1]        ; RAM_DATA[14]  ; 14.981 ; 14.981 ; 14.981 ; 14.981 ;
; FC[1]        ; RAM_DATA[15]  ; 15.143 ; 15.143 ; 15.143 ; 15.143 ;
; FC[1]        ; ROM0n         ; 8.958  ; 8.157  ; 8.157  ; 8.958  ;
; FC[1]        ; ROM1n         ; 9.789  ; 8.988  ; 8.988  ; 9.789  ;
; FC[1]        ; ROM2n         ; 9.107  ; 8.431  ; 8.431  ; 9.107  ;
; FC[1]        ; ROM3n         ; 8.617  ; 7.941  ; 7.941  ; 8.617  ;
; FC[1]        ; ROM4n         ; 8.429  ; 7.753  ; 7.753  ; 8.429  ;
; FC[1]        ; ROM5n         ; 9.638  ; 8.837  ; 8.837  ; 9.638  ;
; FC[1]        ; ROM6n         ; 8.852  ; 8.176  ; 8.176  ; 8.852  ;
; FC[1]        ; RWn           ; 13.374 ; 13.374 ; 13.374 ; 13.374 ;
; FC[1]        ; UDSn          ; 13.278 ; 13.278 ; 13.278 ; 13.278 ;
; FC[2]        ; ACSI_RDn      ; 10.013 ; 10.013 ; 10.013 ; 10.013 ;
; FC[2]        ; ACSI_WRn      ; 10.003 ; 10.003 ; 10.003 ; 10.003 ;
; FC[2]        ; ASn           ; 12.764 ; 12.764 ; 12.764 ; 12.764 ;
; FC[2]        ; BUTTONn       ; 8.607  ;        ;        ; 8.607  ;
; FC[2]        ; CA1_OUT       ; 9.048  ; 7.929  ; 7.929  ; 9.048  ;
; FC[2]        ; CD[0]         ; 12.183 ; 12.183 ; 12.183 ; 12.183 ;
; FC[2]        ; CD[1]         ; 11.953 ; 11.953 ; 11.953 ; 11.953 ;
; FC[2]        ; CD[2]         ; 11.729 ; 11.729 ; 11.729 ; 11.729 ;
; FC[2]        ; CD[3]         ; 12.379 ; 12.379 ; 12.379 ; 12.379 ;
; FC[2]        ; CD[4]         ; 11.907 ; 11.907 ; 11.907 ; 11.907 ;
; FC[2]        ; CD[5]         ; 11.556 ; 11.556 ; 11.556 ; 11.556 ;
; FC[2]        ; CD[6]         ; 12.708 ; 12.708 ; 12.708 ; 12.708 ;
; FC[2]        ; CD[7]         ; 11.766 ; 11.766 ; 11.766 ; 11.766 ;
; FC[2]        ; DATA[0]       ; 16.787 ; 16.787 ; 16.787 ; 16.787 ;
; FC[2]        ; DATA[1]       ; 16.509 ; 16.509 ; 16.509 ; 16.509 ;
; FC[2]        ; DATA[2]       ; 16.130 ; 16.130 ; 16.130 ; 16.130 ;
; FC[2]        ; DATA[3]       ; 16.270 ; 16.270 ; 16.270 ; 16.270 ;
; FC[2]        ; DATA[4]       ; 15.661 ; 15.661 ; 15.661 ; 15.661 ;
; FC[2]        ; DATA[5]       ; 17.150 ; 17.150 ; 17.150 ; 17.150 ;
; FC[2]        ; DATA[6]       ; 16.009 ; 16.009 ; 16.009 ; 16.009 ;
; FC[2]        ; DATA[7]       ; 16.164 ; 16.164 ; 16.164 ; 16.164 ;
; FC[2]        ; DATA[8]       ; 15.751 ; 15.751 ; 15.751 ; 15.751 ;
; FC[2]        ; DATA[9]       ; 16.282 ; 16.224 ; 16.224 ; 16.282 ;
; FC[2]        ; DATA[10]      ; 16.300 ; 16.300 ; 16.300 ; 16.300 ;
; FC[2]        ; DATA[11]      ; 17.857 ; 17.799 ; 17.799 ; 17.857 ;
; FC[2]        ; DATA[12]      ; 15.897 ; 15.839 ; 15.839 ; 15.897 ;
; FC[2]        ; DATA[13]      ; 16.416 ; 16.358 ; 16.358 ; 16.416 ;
; FC[2]        ; DATA[14]      ; 15.838 ; 15.838 ; 15.838 ; 15.838 ;
; FC[2]        ; DATA[15]      ; 16.158 ; 16.158 ; 16.158 ; 16.158 ;
; FC[2]        ; DTACKn        ; 13.036 ; 13.036 ; 13.036 ; 13.036 ;
; FC[2]        ; FC[0]         ; 13.045 ; 13.045 ; 13.045 ; 13.045 ;
; FC[2]        ; FC[1]         ; 12.853 ; 12.853 ; 12.853 ; 12.853 ;
; FC[2]        ; FC[2]         ; 12.853 ; 12.853 ; 12.853 ; 12.853 ;
; FC[2]        ; FLASH_CEn     ; 9.906  ;        ;        ; 9.906  ;
; FC[2]        ; FLASH_OEn     ; 10.404 ;        ;        ; 10.404 ;
; FC[2]        ; IDE_CS0n      ; 7.909  ;        ;        ; 7.909  ;
; FC[2]        ; IDE_CS1n      ; 7.802  ;        ;        ; 7.802  ;
; FC[2]        ; IDE_D_EN_INn  ; 8.037  ;        ;        ; 8.037  ;
; FC[2]        ; IDE_D_EN_OUTn ; 7.817  ;        ;        ; 7.817  ;
; FC[2]        ; IDE_IORDn     ; 7.861  ;        ;        ; 7.861  ;
; FC[2]        ; IDE_IOWRn     ; 7.866  ;        ;        ; 7.866  ;
; FC[2]        ; JOY_RHn       ; 7.809  ; 8.190  ; 8.190  ; 7.809  ;
; FC[2]        ; JOY_RLn       ; 8.716  ; 9.107  ; 9.107  ; 8.716  ;
; FC[2]        ; JOY_WEn       ; 9.079  ; 8.688  ; 8.688  ; 9.079  ;
; FC[2]        ; JOY_WL        ; 7.856  ; 7.530  ; 7.530  ; 7.856  ;
; FC[2]        ; LDSn          ; 13.231 ; 13.231 ; 13.231 ; 13.231 ;
; FC[2]        ; RAM_DATA[0]   ; 14.966 ; 14.966 ; 14.966 ; 14.966 ;
; FC[2]        ; RAM_DATA[1]   ; 15.594 ; 15.594 ; 15.594 ; 15.594 ;
; FC[2]        ; RAM_DATA[2]   ; 15.287 ; 15.287 ; 15.287 ; 15.287 ;
; FC[2]        ; RAM_DATA[3]   ; 15.367 ; 15.367 ; 15.367 ; 15.367 ;
; FC[2]        ; RAM_DATA[4]   ; 15.790 ; 15.790 ; 15.790 ; 15.790 ;
; FC[2]        ; RAM_DATA[5]   ; 15.809 ; 15.809 ; 15.809 ; 15.809 ;
; FC[2]        ; RAM_DATA[6]   ; 15.840 ; 15.840 ; 15.840 ; 15.840 ;
; FC[2]        ; RAM_DATA[7]   ; 15.846 ; 15.846 ; 15.846 ; 15.846 ;
; FC[2]        ; RAM_DATA[8]   ; 15.362 ; 15.362 ; 15.362 ; 15.362 ;
; FC[2]        ; RAM_DATA[9]   ; 15.653 ; 15.595 ; 15.595 ; 15.653 ;
; FC[2]        ; RAM_DATA[10]  ; 16.437 ; 16.437 ; 16.437 ; 16.437 ;
; FC[2]        ; RAM_DATA[11]  ; 16.222 ; 16.164 ; 16.164 ; 16.222 ;
; FC[2]        ; RAM_DATA[12]  ; 15.961 ; 15.903 ; 15.903 ; 15.961 ;
; FC[2]        ; RAM_DATA[13]  ; 15.267 ; 15.209 ; 15.209 ; 15.267 ;
; FC[2]        ; RAM_DATA[14]  ; 14.954 ; 14.954 ; 14.954 ; 14.954 ;
; FC[2]        ; RAM_DATA[15]  ; 15.116 ; 15.116 ; 15.116 ; 15.116 ;
; FC[2]        ; ROM0n         ; 8.931  ;        ;        ; 8.931  ;
; FC[2]        ; ROM1n         ; 9.762  ;        ;        ; 9.762  ;
; FC[2]        ; ROM2n         ; 9.080  ;        ;        ; 9.080  ;
; FC[2]        ; ROM3n         ; 8.590  ;        ;        ; 8.590  ;
; FC[2]        ; ROM4n         ; 8.402  ;        ;        ; 8.402  ;
; FC[2]        ; ROM5n         ; 9.611  ;        ;        ; 9.611  ;
; FC[2]        ; ROM6n         ; 8.825  ;        ;        ; 8.825  ;
; FC[2]        ; RWn           ; 13.327 ; 13.327 ; 13.327 ; 13.327 ;
; FC[2]        ; UDSn          ; 13.231 ; 13.231 ; 13.231 ; 13.231 ;
; HDINTn       ; DATA[5]       ; 12.021 ; 12.021 ; 12.021 ; 12.021 ;
; HDINTn       ; DATA[13]      ; 11.915 ;        ;        ; 11.915 ;
; HDINTn       ; RAM_DATA[5]   ; 10.680 ; 10.680 ; 10.680 ; 10.680 ;
; HDINTn       ; RAM_DATA[13]  ; 10.766 ;        ;        ; 10.766 ;
; IDE_INTRQ    ; DATA[5]       ; 12.138 ; 12.138 ; 12.138 ; 12.138 ;
; IDE_INTRQ    ; DATA[13]      ;        ; 12.032 ; 12.032 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ; 10.797 ; 10.797 ; 10.797 ; 10.797 ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 10.883 ; 10.883 ;        ;
; LDSn         ; ACSI_RDn      ; 7.770  ; 7.770  ; 7.770  ; 7.770  ;
; LDSn         ; ACSI_WRn      ; 7.760  ; 7.760  ; 7.760  ; 7.760  ;
; LDSn         ; ASn           ; 12.419 ; 12.419 ; 12.419 ; 12.419 ;
; LDSn         ; BUTTONn       ; 8.267  ;        ;        ; 8.267  ;
; LDSn         ; CA1_OUT       ; 6.805  ;        ;        ; 6.805  ;
; LDSn         ; CD[0]         ; 9.940  ; 9.940  ; 9.940  ; 9.940  ;
; LDSn         ; CD[1]         ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; LDSn         ; CD[2]         ; 9.486  ; 9.486  ; 9.486  ; 9.486  ;
; LDSn         ; CD[3]         ; 10.136 ; 10.136 ; 10.136 ; 10.136 ;
; LDSn         ; CD[4]         ; 9.664  ; 9.664  ; 9.664  ; 9.664  ;
; LDSn         ; CD[5]         ; 9.313  ; 9.313  ; 9.313  ; 9.313  ;
; LDSn         ; CD[6]         ; 10.465 ; 10.465 ; 10.465 ; 10.465 ;
; LDSn         ; CD[7]         ; 9.523  ; 9.523  ; 9.523  ; 9.523  ;
; LDSn         ; DATA[0]       ; 16.442 ; 16.442 ; 16.442 ; 16.442 ;
; LDSn         ; DATA[1]       ; 15.472 ; 15.472 ; 15.472 ; 15.472 ;
; LDSn         ; DATA[2]       ; 15.628 ; 15.734 ; 15.734 ; 15.628 ;
; LDSn         ; DATA[3]       ; 15.925 ; 15.925 ; 15.925 ; 15.925 ;
; LDSn         ; DATA[4]       ; 15.193 ; 15.193 ; 15.193 ; 15.193 ;
; LDSn         ; DATA[5]       ; 16.104 ; 16.104 ; 16.104 ; 16.104 ;
; LDSn         ; DATA[6]       ; 14.957 ; 14.957 ; 14.957 ; 14.957 ;
; LDSn         ; DATA[7]       ; 15.819 ; 15.819 ; 15.819 ; 15.819 ;
; LDSn         ; DATA[8]       ; 15.304 ; 15.304 ; 15.304 ; 15.304 ;
; LDSn         ; DATA[9]       ; 15.398 ; 15.587 ; 15.587 ; 15.398 ;
; LDSn         ; DATA[10]      ; 15.032 ; 15.032 ; 15.032 ; 15.032 ;
; LDSn         ; DATA[11]      ; 16.318 ; 16.589 ; 16.589 ; 16.318 ;
; LDSn         ; DATA[12]      ; 15.332 ; 15.492 ; 15.492 ; 15.332 ;
; LDSn         ; DATA[13]      ; 15.698 ; 15.941 ; 15.941 ; 15.698 ;
; LDSn         ; DATA[14]      ; 14.628 ; 14.628 ; 14.628 ; 14.628 ;
; LDSn         ; DATA[15]      ; 14.992 ; 14.992 ; 14.992 ; 14.992 ;
; LDSn         ; DTACKn        ; 12.052 ; 12.052 ; 12.052 ; 12.052 ;
; LDSn         ; FC[0]         ; 12.700 ; 12.700 ; 12.700 ; 12.700 ;
; LDSn         ; FC[1]         ; 12.508 ; 12.508 ; 12.508 ; 12.508 ;
; LDSn         ; FC[2]         ; 12.508 ; 12.508 ; 12.508 ; 12.508 ;
; LDSn         ; IDE_IORDn     ; 7.299  ;        ;        ; 7.299  ;
; LDSn         ; IDE_IOWRn     ; 7.309  ;        ;        ; 7.309  ;
; LDSn         ; JOY_RLn       ; 8.031  ;        ;        ; 8.031  ;
; LDSn         ; JOY_WEn       ;        ; 8.003  ; 8.003  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.784  ; 6.784  ;        ;
; LDSn         ; LDSn          ; 12.886 ; 12.886 ; 12.886 ; 12.886 ;
; LDSn         ; RAM_CAS0n     ; 9.685  ;        ;        ; 9.685  ;
; LDSn         ; RAM_CAS1n     ; 9.271  ;        ;        ; 9.271  ;
; LDSn         ; RAM_DATA[0]   ; 14.621 ; 14.621 ; 14.621 ; 14.621 ;
; LDSn         ; RAM_DATA[1]   ; 14.557 ; 14.557 ; 14.557 ; 14.557 ;
; LDSn         ; RAM_DATA[2]   ; 14.785 ; 14.891 ; 14.891 ; 14.785 ;
; LDSn         ; RAM_DATA[3]   ; 15.022 ; 15.022 ; 15.022 ; 15.022 ;
; LDSn         ; RAM_DATA[4]   ; 15.322 ; 15.322 ; 15.322 ; 15.322 ;
; LDSn         ; RAM_DATA[5]   ; 14.763 ; 14.763 ; 14.763 ; 14.763 ;
; LDSn         ; RAM_DATA[6]   ; 14.788 ; 14.788 ; 14.788 ; 14.788 ;
; LDSn         ; RAM_DATA[7]   ; 15.501 ; 15.501 ; 15.501 ; 15.501 ;
; LDSn         ; RAM_DATA[8]   ; 14.915 ; 14.915 ; 14.915 ; 14.915 ;
; LDSn         ; RAM_DATA[9]   ; 14.769 ; 14.958 ; 14.958 ; 14.769 ;
; LDSn         ; RAM_DATA[10]  ; 15.169 ; 15.169 ; 15.169 ; 15.169 ;
; LDSn         ; RAM_DATA[11]  ; 14.683 ; 14.954 ; 14.954 ; 14.683 ;
; LDSn         ; RAM_DATA[12]  ; 15.396 ; 15.556 ; 15.556 ; 15.396 ;
; LDSn         ; RAM_DATA[13]  ; 14.549 ; 14.792 ; 14.792 ; 14.549 ;
; LDSn         ; RAM_DATA[14]  ; 13.744 ; 13.744 ; 13.744 ; 13.744 ;
; LDSn         ; RAM_DATA[15]  ; 13.950 ; 13.950 ; 13.950 ; 13.950 ;
; LDSn         ; RAM_DQM0H     ; 11.440 ; 11.286 ; 11.286 ; 11.440 ;
; LDSn         ; RAM_DQM0L     ; 10.859 ; 10.701 ; 10.701 ; 10.859 ;
; LDSn         ; RAM_DQM1H     ; 11.596 ; 11.442 ; 11.442 ; 11.596 ;
; LDSn         ; RAM_DQM1L     ; 10.849 ; 10.691 ; 10.691 ; 10.849 ;
; LDSn         ; RWn           ; 12.982 ; 12.982 ; 12.982 ; 12.982 ;
; LDSn         ; UDSn          ; 12.886 ; 12.886 ; 12.886 ; 12.886 ;
; LPT_BSY      ; DATA[0]       ; 10.508 ;        ;        ; 10.508 ;
; LPT_BSY      ; DATA[8]       ; 9.705  ;        ;        ; 9.705  ;
; LPT_BSY      ; RAM_DATA[0]   ; 8.687  ;        ;        ; 8.687  ;
; LPT_BSY      ; RAM_DATA[8]   ; 9.316  ;        ;        ; 9.316  ;
; LPT_D[0]     ; DATA[0]       ; 10.269 ;        ;        ; 10.269 ;
; LPT_D[0]     ; DATA[8]       ; 9.466  ;        ;        ; 9.466  ;
; LPT_D[0]     ; RAM_DATA[0]   ; 8.448  ;        ;        ; 8.448  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 9.077  ;        ;        ; 9.077  ;
; LPT_D[1]     ; DATA[1]       ; 10.091 ;        ;        ; 10.091 ;
; LPT_D[1]     ; DATA[9]       ; 9.730  ;        ;        ; 9.730  ;
; LPT_D[1]     ; RAM_DATA[1]   ; 9.176  ;        ;        ; 9.176  ;
; LPT_D[1]     ; RAM_DATA[9]   ; 9.101  ;        ;        ; 9.101  ;
; LPT_D[2]     ; DATA[2]       ; 9.895  ;        ;        ; 9.895  ;
; LPT_D[2]     ; DATA[10]      ; 9.494  ;        ;        ; 9.494  ;
; LPT_D[2]     ; RAM_DATA[2]   ; 9.052  ;        ;        ; 9.052  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.631  ;        ;        ; 9.631  ;
; LPT_D[3]     ; DATA[3]       ; 10.501 ;        ;        ; 10.501 ;
; LPT_D[3]     ; DATA[11]      ; 11.246 ;        ;        ; 11.246 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 9.598  ;        ;        ; 9.598  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.611  ;        ;        ; 9.611  ;
; LPT_D[4]     ; DATA[4]       ; 11.131 ; 11.131 ; 11.131 ; 11.131 ;
; LPT_D[4]     ; DATA[12]      ; 10.859 ;        ;        ; 10.859 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 11.260 ; 11.260 ; 11.260 ; 11.260 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 10.923 ;        ;        ; 10.923 ;
; LPT_D[5]     ; DATA[5]       ; 11.281 ; 11.281 ; 11.281 ; 11.281 ;
; LPT_D[5]     ; DATA[13]      ; 10.479 ;        ;        ; 10.479 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 9.940  ; 9.940  ; 9.940  ; 9.940  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 9.330  ;        ;        ; 9.330  ;
; LPT_D[6]     ; DATA[6]       ; 11.221 ; 11.221 ; 11.221 ; 11.221 ;
; LPT_D[6]     ; DATA[14]      ; 10.609 ; 10.609 ; 10.609 ; 10.609 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 11.052 ; 11.052 ; 11.052 ; 11.052 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 9.725  ; 9.725  ; 9.725  ; 9.725  ;
; LPT_D[7]     ; DATA[7]       ; 10.478 ; 10.478 ; 10.478 ; 10.478 ;
; LPT_D[7]     ; DATA[15]      ; 10.663 ; 10.663 ; 10.663 ; 10.663 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 10.160 ; 10.160 ; 10.160 ; 10.160 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 9.621  ; 9.621  ; 9.621  ; 9.621  ;
; MIDI_IN      ; MIDI_TLR      ; 4.723  ;        ;        ; 4.723  ;
; RAM_DATA[0]  ; DATA[0]       ; 11.823 ;        ;        ; 11.823 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 10.002 ;        ;        ; 10.002 ;
; RAM_DATA[1]  ; DATA[1]       ; 11.087 ;        ;        ; 11.087 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.172 ;        ;        ; 10.172 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.602 ;        ;        ; 10.602 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 9.759  ;        ;        ; 9.759  ;
; RAM_DATA[3]  ; DATA[3]       ; 11.042 ;        ;        ; 11.042 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.139 ;        ;        ; 10.139 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.830  ; 9.830  ; 9.830  ; 9.830  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 9.959  ; 9.959  ; 9.959  ; 9.959  ;
; RAM_DATA[5]  ; DATA[5]       ; 11.415 ; 11.415 ; 11.415 ; 11.415 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 10.074 ; 10.074 ; 10.074 ; 10.074 ;
; RAM_DATA[6]  ; DATA[6]       ; 11.600 ; 11.600 ; 11.600 ; 11.600 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.431 ; 11.431 ; 11.431 ; 11.431 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.234 ; 10.234 ; 10.234 ; 10.234 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 9.916  ; 9.916  ; 9.916  ; 9.916  ;
; RAM_DATA[8]  ; DATA[8]       ; 10.292 ;        ;        ; 10.292 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 9.903  ;        ;        ; 9.903  ;
; RAM_DATA[9]  ; DATA[9]       ; 10.476 ;        ;        ; 10.476 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 9.847  ;        ;        ; 9.847  ;
; RAM_DATA[10] ; DATA[10]      ; 10.205 ;        ;        ; 10.205 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 10.342 ;        ;        ; 10.342 ;
; RAM_DATA[11] ; DATA[11]      ; 11.770 ;        ;        ; 11.770 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.135 ;        ;        ; 10.135 ;
; RAM_DATA[12] ; DATA[12]      ; 11.247 ;        ;        ; 11.247 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 11.311 ;        ;        ; 11.311 ;
; RAM_DATA[13] ; DATA[13]      ; 11.221 ;        ;        ; 11.221 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.072 ;        ;        ; 10.072 ;
; RAM_DATA[14] ; DATA[14]      ; 11.089 ; 11.089 ; 11.089 ; 11.089 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.205 ; 10.205 ; 10.205 ; 10.205 ;
; RAM_DATA[15] ; DATA[15]      ; 11.462 ; 11.462 ; 11.462 ; 11.462 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 10.420 ; 10.420 ; 10.420 ; 10.420 ;
; RWn          ; ACSI_RDn      ; 8.200  ; 8.200  ; 8.200  ; 8.200  ;
; RWn          ; ACSI_WRn      ; 8.190  ; 8.190  ; 8.190  ; 8.190  ;
; RWn          ; ASn           ; 11.451 ; 11.451 ; 11.451 ; 11.451 ;
; RWn          ; BUTTONn       ;        ; 9.805  ; 9.805  ;        ;
; RWn          ; CA1_OUT       ;        ; 7.235  ; 7.235  ;        ;
; RWn          ; CD[0]         ; 10.370 ; 10.370 ; 10.370 ; 10.370 ;
; RWn          ; CD[1]         ; 10.140 ; 10.140 ; 10.140 ; 10.140 ;
; RWn          ; CD[2]         ; 9.916  ; 9.916  ; 9.916  ; 9.916  ;
; RWn          ; CD[3]         ; 10.566 ; 10.566 ; 10.566 ; 10.566 ;
; RWn          ; CD[4]         ; 10.094 ; 10.094 ; 10.094 ; 10.094 ;
; RWn          ; CD[5]         ; 9.743  ; 9.743  ; 9.743  ; 9.743  ;
; RWn          ; CD[6]         ; 10.895 ; 10.895 ; 10.895 ; 10.895 ;
; RWn          ; CD[7]         ; 9.953  ; 9.953  ; 9.953  ; 9.953  ;
; RWn          ; DATA[0]       ; 17.006 ; 17.128 ; 17.128 ; 17.006 ;
; RWn          ; DATA[1]       ; 16.902 ; 16.902 ; 16.902 ; 16.902 ;
; RWn          ; DATA[2]       ; 16.406 ; 16.406 ; 16.406 ; 16.406 ;
; RWn          ; DATA[3]       ; 17.359 ; 17.359 ; 17.359 ; 17.359 ;
; RWn          ; DATA[4]       ; 15.844 ; 15.844 ; 15.844 ; 15.844 ;
; RWn          ; DATA[5]       ; 16.856 ; 16.856 ; 16.856 ; 16.856 ;
; RWn          ; DATA[6]       ; 15.654 ; 15.654 ; 15.654 ; 15.654 ;
; RWn          ; DATA[7]       ; 16.742 ; 16.742 ; 16.742 ; 16.742 ;
; RWn          ; DATA[8]       ; 16.203 ; 16.203 ; 16.203 ; 16.203 ;
; RWn          ; DATA[9]       ; 16.505 ; 16.505 ; 16.505 ; 16.505 ;
; RWn          ; DATA[10]      ; 16.387 ; 16.387 ; 16.387 ; 16.387 ;
; RWn          ; DATA[11]      ; 17.397 ; 17.397 ; 17.397 ; 17.397 ;
; RWn          ; DATA[12]      ; 16.569 ; 16.569 ; 16.569 ; 16.569 ;
; RWn          ; DATA[13]      ; 16.750 ; 16.881 ; 16.881 ; 16.750 ;
; RWn          ; DATA[14]      ; 16.490 ; 16.490 ; 16.490 ; 16.490 ;
; RWn          ; DATA[15]      ; 16.757 ; 16.757 ; 16.757 ; 16.757 ;
; RWn          ; DTACKn        ; 13.590 ; 13.590 ; 13.590 ; 13.590 ;
; RWn          ; FC[0]         ; 11.732 ; 11.732 ; 11.732 ; 11.732 ;
; RWn          ; FC[1]         ; 11.540 ; 11.540 ; 11.540 ; 11.540 ;
; RWn          ; FC[2]         ; 11.540 ; 11.540 ; 11.540 ; 11.540 ;
; RWn          ; FLASH_CEn     ;        ; 11.017 ; 11.017 ;        ;
; RWn          ; FLASH_OEn     ;        ; 11.515 ; 11.515 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 9.038  ; 9.038  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 8.858  ;        ;        ; 8.858  ;
; RWn          ; IDE_IORDn     ;        ; 8.940  ; 8.940  ;        ;
; RWn          ; IDE_IOWRn     ; 8.967  ;        ;        ; 8.967  ;
; RWn          ; JOY_RHn       ; 9.495  ; 9.495  ; 9.495  ; 9.495  ;
; RWn          ; JOY_RLn       ; 10.412 ; 10.412 ; 10.412 ; 10.412 ;
; RWn          ; JOY_WEn       ; 10.384 ; 10.384 ; 10.384 ; 10.384 ;
; RWn          ; JOY_WL        ; 9.161  ; 9.161  ; 9.161  ; 9.161  ;
; RWn          ; LDSn          ; 11.918 ; 11.918 ; 11.918 ; 11.918 ;
; RWn          ; RAM_DATA[0]   ; 15.185 ; 15.307 ; 15.307 ; 15.185 ;
; RWn          ; RAM_DATA[1]   ; 15.987 ; 15.987 ; 15.987 ; 15.987 ;
; RWn          ; RAM_DATA[2]   ; 15.563 ; 15.563 ; 15.563 ; 15.563 ;
; RWn          ; RAM_DATA[3]   ; 16.456 ; 16.456 ; 16.456 ; 16.456 ;
; RWn          ; RAM_DATA[4]   ; 15.973 ; 15.973 ; 15.973 ; 15.973 ;
; RWn          ; RAM_DATA[5]   ; 15.515 ; 15.515 ; 15.515 ; 15.515 ;
; RWn          ; RAM_DATA[6]   ; 15.485 ; 15.485 ; 15.485 ; 15.485 ;
; RWn          ; RAM_DATA[7]   ; 16.424 ; 16.424 ; 16.424 ; 16.424 ;
; RWn          ; RAM_DATA[8]   ; 15.814 ; 15.814 ; 15.814 ; 15.814 ;
; RWn          ; RAM_DATA[9]   ; 15.876 ; 15.876 ; 15.876 ; 15.876 ;
; RWn          ; RAM_DATA[10]  ; 16.524 ; 16.524 ; 16.524 ; 16.524 ;
; RWn          ; RAM_DATA[11]  ; 15.762 ; 15.762 ; 15.762 ; 15.762 ;
; RWn          ; RAM_DATA[12]  ; 16.633 ; 16.633 ; 16.633 ; 16.633 ;
; RWn          ; RAM_DATA[13]  ; 15.601 ; 15.732 ; 15.732 ; 15.601 ;
; RWn          ; RAM_DATA[14]  ; 15.606 ; 15.606 ; 15.606 ; 15.606 ;
; RWn          ; RAM_DATA[15]  ; 15.715 ; 15.715 ; 15.715 ; 15.715 ;
; RWn          ; RAM_DQM0H     ;        ; 8.839  ; 8.839  ;        ;
; RWn          ; RAM_DQM0L     ;        ; 8.251  ; 8.251  ;        ;
; RWn          ; RAM_DQM1H     ;        ; 8.995  ; 8.995  ;        ;
; RWn          ; RAM_DQM1L     ;        ; 8.241  ; 8.241  ;        ;
; RWn          ; RAM_WEn       ; 9.417  ;        ;        ; 9.417  ;
; RWn          ; ROM0n         ;        ; 9.796  ; 9.796  ;        ;
; RWn          ; ROM1n         ;        ; 10.627 ; 10.627 ;        ;
; RWn          ; ROM2n         ;        ; 10.191 ; 10.191 ;        ;
; RWn          ; ROM3n         ;        ; 9.701  ; 9.701  ;        ;
; RWn          ; ROM4n         ;        ; 9.513  ; 9.513  ;        ;
; RWn          ; ROM5n         ;        ; 10.476 ; 10.476 ;        ;
; RWn          ; ROM6n         ;        ; 9.936  ; 9.936  ;        ;
; RWn          ; RWn           ; 12.014 ; 12.014 ; 12.014 ; 12.014 ;
; RWn          ; UDSn          ; 11.918 ; 11.918 ; 11.918 ; 11.918 ;
; SCSI_ACKn    ; CD[0]         ; 7.951  ; 7.951  ; 7.951  ; 7.951  ;
; SCSI_ATNn    ; CD[1]         ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; SCSI_BSYn    ; CD[6]         ;        ; 7.019  ; 7.019  ;        ;
; SCSI_D[0]    ; CD[0]         ; 8.485  ; 8.485  ; 8.485  ; 8.485  ;
; SCSI_D[1]    ; CD[1]         ; 8.138  ; 8.138  ; 8.138  ; 8.138  ;
; SCSI_D[2]    ; CD[2]         ;        ; 7.702  ; 7.702  ;        ;
; SCSI_D[3]    ; CD[3]         ; 8.804  ; 8.804  ; 8.804  ; 8.804  ;
; SCSI_D[4]    ; CD[4]         ; 6.442  ; 6.442  ; 6.442  ; 6.442  ;
; SCSI_D[5]    ; CD[5]         ; 6.256  ; 6.256  ; 6.256  ; 6.256  ;
; SCSI_D[6]    ; CD[6]         ; 7.643  ; 7.643  ; 7.643  ; 7.643  ;
; SCSI_D[7]    ; CD[7]         ;        ; 7.825  ; 7.825  ;        ;
; SCSI_DCn     ; CD[3]         ; 8.965  ; 8.965  ; 8.965  ; 8.965  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 7.254  ; 7.254  ; 7.254  ; 7.254  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.983  ; 7.983  ; 7.983  ; 7.983  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.983  ; 7.983  ; 7.983  ; 7.983  ;
; SCSI_DCn     ; SCSI_DP       ; 7.860  ; 7.860  ; 7.860  ; 7.860  ;
; SCSI_DP      ; CD[0]         ; 8.140  ; 8.140  ; 8.140  ; 8.140  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.638  ; 7.638  ;        ;
; SCSI_IOn     ; CD[3]         ; 9.153  ; 9.153  ; 9.153  ; 9.153  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 7.442  ; 7.442  ; 7.442  ; 7.442  ;
; SCSI_IOn     ; SCSI_D[0]     ; 8.038  ; 8.038  ; 8.038  ; 8.038  ;
; SCSI_IOn     ; SCSI_D[1]     ; 8.038  ; 8.038  ; 8.038  ; 8.038  ;
; SCSI_IOn     ; SCSI_D[2]     ; 8.143  ; 8.143  ; 8.143  ; 8.143  ;
; SCSI_IOn     ; SCSI_D[3]     ; 8.143  ; 8.143  ; 8.143  ; 8.143  ;
; SCSI_IOn     ; SCSI_D[4]     ; 8.162  ; 8.162  ; 8.162  ; 8.162  ;
; SCSI_IOn     ; SCSI_D[5]     ; 8.162  ; 8.162  ; 8.162  ; 8.162  ;
; SCSI_IOn     ; SCSI_D[6]     ; 8.171  ; 8.171  ; 8.171  ; 8.171  ;
; SCSI_IOn     ; SCSI_D[7]     ; 8.171  ; 8.171  ; 8.171  ; 8.171  ;
; SCSI_IOn     ; SCSI_DP       ; 8.048  ; 8.048  ; 8.048  ; 8.048  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.116  ;        ;        ; 6.116  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.098  ; 6.098  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.794  ; 8.794  ; 8.794  ; 8.794  ;
; SCSI_MSGn    ; CD[4]         ;        ; 6.001  ; 6.001  ;        ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.083  ; 7.083  ; 7.083  ; 7.083  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.679  ; 7.679  ; 7.679  ; 7.679  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.679  ; 7.679  ; 7.679  ; 7.679  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.784  ; 7.784  ; 7.784  ; 7.784  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.784  ; 7.784  ; 7.784  ; 7.784  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.803  ; 7.803  ; 7.803  ; 7.803  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.803  ; 7.803  ; 7.803  ; 7.803  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.812  ; 7.812  ; 7.812  ; 7.812  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.812  ; 7.812  ; 7.812  ; 7.812  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.689  ; 7.689  ; 7.689  ; 7.689  ;
; SCSI_REQn    ; CD[3]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; SCSI_REQn    ; CD[5]         ;        ; 5.946  ; 5.946  ;        ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 7.148  ;        ;        ; 7.148  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.849  ; 7.849  ; 7.849  ; 7.849  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.849  ; 7.849  ; 7.849  ; 7.849  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.868  ; 7.868  ; 7.868  ; 7.868  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.868  ; 7.868  ; 7.868  ; 7.868  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SCSI_REQn    ; SCSI_DP       ; 7.754  ; 7.754  ; 7.754  ; 7.754  ;
; SCSI_RSTn    ; CD[7]         ;        ; 7.478  ; 7.478  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.067  ; 7.067  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 7.169  ; 7.169  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 7.212  ; 7.212  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.074  ;        ;        ; 6.074  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.273  ;        ;        ; 6.273  ;
; SD_RESETn    ; COM_TxD       ; 8.327  ; 8.327  ; 8.327  ; 8.327  ;
; UDSn         ; ACSI_RDn      ; 9.213  ; 9.213  ; 9.213  ; 9.213  ;
; UDSn         ; ACSI_WRn      ; 9.203  ; 9.203  ; 9.203  ; 9.203  ;
; UDSn         ; ASn           ; 12.232 ; 12.232 ; 12.232 ; 12.232 ;
; UDSn         ; CA1_OUT       ; 8.248  ;        ;        ; 8.248  ;
; UDSn         ; CD[0]         ; 11.383 ; 11.383 ; 11.383 ; 11.383 ;
; UDSn         ; CD[1]         ; 11.153 ; 11.153 ; 11.153 ; 11.153 ;
; UDSn         ; CD[2]         ; 10.929 ; 10.929 ; 10.929 ; 10.929 ;
; UDSn         ; CD[3]         ; 11.579 ; 11.579 ; 11.579 ; 11.579 ;
; UDSn         ; CD[4]         ; 11.107 ; 11.107 ; 11.107 ; 11.107 ;
; UDSn         ; CD[5]         ; 10.756 ; 10.756 ; 10.756 ; 10.756 ;
; UDSn         ; CD[6]         ; 11.908 ; 11.908 ; 11.908 ; 11.908 ;
; UDSn         ; CD[7]         ; 10.966 ; 10.966 ; 10.966 ; 10.966 ;
; UDSn         ; DATA[0]       ; 16.452 ; 16.452 ; 16.452 ; 16.452 ;
; UDSn         ; DATA[1]       ; 16.503 ; 16.503 ; 16.503 ; 16.503 ;
; UDSn         ; DATA[2]       ; 16.124 ; 16.124 ; 16.124 ; 16.124 ;
; UDSn         ; DATA[3]       ; 16.040 ; 16.164 ; 16.164 ; 16.040 ;
; UDSn         ; DATA[4]       ; 15.655 ; 15.655 ; 15.655 ; 15.655 ;
; UDSn         ; DATA[5]       ; 17.144 ; 17.144 ; 17.144 ; 17.144 ;
; UDSn         ; DATA[6]       ; 16.003 ; 16.003 ; 16.003 ; 16.003 ;
; UDSn         ; DATA[7]       ; 16.105 ; 16.105 ; 16.105 ; 16.105 ;
; UDSn         ; DATA[8]       ; 15.745 ; 15.745 ; 15.745 ; 15.745 ;
; UDSn         ; DATA[9]       ; 16.276 ; 16.118 ; 16.118 ; 16.276 ;
; UDSn         ; DATA[10]      ; 16.294 ; 16.294 ; 16.294 ; 16.294 ;
; UDSn         ; DATA[11]      ; 17.851 ; 17.478 ; 17.478 ; 17.851 ;
; UDSn         ; DATA[12]      ; 15.891 ; 15.305 ; 15.305 ; 15.891 ;
; UDSn         ; DATA[13]      ; 16.410 ; 15.950 ; 15.950 ; 16.410 ;
; UDSn         ; DATA[14]      ; 15.788 ; 15.788 ; 15.788 ; 15.788 ;
; UDSn         ; DATA[15]      ; 16.152 ; 16.152 ; 16.152 ; 16.152 ;
; UDSn         ; DTACKn        ; 12.305 ; 12.305 ; 12.305 ; 12.305 ;
; UDSn         ; FC[0]         ; 12.513 ; 12.513 ; 12.513 ; 12.513 ;
; UDSn         ; FC[1]         ; 12.321 ; 12.321 ; 12.321 ; 12.321 ;
; UDSn         ; FC[2]         ; 12.321 ; 12.321 ; 12.321 ; 12.321 ;
; UDSn         ; JOY_RHn       ; 7.689  ;        ;        ; 7.689  ;
; UDSn         ; LDSn          ; 12.699 ; 12.699 ; 12.699 ; 12.699 ;
; UDSn         ; RAM_CAS0n     ; 9.515  ;        ;        ; 9.515  ;
; UDSn         ; RAM_CAS1n     ; 9.101  ;        ;        ; 9.101  ;
; UDSn         ; RAM_DATA[0]   ; 14.631 ; 14.631 ; 14.631 ; 14.631 ;
; UDSn         ; RAM_DATA[1]   ; 15.588 ; 15.588 ; 15.588 ; 15.588 ;
; UDSn         ; RAM_DATA[2]   ; 15.281 ; 15.281 ; 15.281 ; 15.281 ;
; UDSn         ; RAM_DATA[3]   ; 15.137 ; 15.261 ; 15.261 ; 15.137 ;
; UDSn         ; RAM_DATA[4]   ; 15.784 ; 15.784 ; 15.784 ; 15.784 ;
; UDSn         ; RAM_DATA[5]   ; 15.803 ; 15.803 ; 15.803 ; 15.803 ;
; UDSn         ; RAM_DATA[6]   ; 15.834 ; 15.834 ; 15.834 ; 15.834 ;
; UDSn         ; RAM_DATA[7]   ; 15.787 ; 15.787 ; 15.787 ; 15.787 ;
; UDSn         ; RAM_DATA[8]   ; 15.356 ; 15.356 ; 15.356 ; 15.356 ;
; UDSn         ; RAM_DATA[9]   ; 15.647 ; 15.489 ; 15.489 ; 15.647 ;
; UDSn         ; RAM_DATA[10]  ; 16.431 ; 16.431 ; 16.431 ; 16.431 ;
; UDSn         ; RAM_DATA[11]  ; 16.216 ; 15.843 ; 15.843 ; 16.216 ;
; UDSn         ; RAM_DATA[12]  ; 15.955 ; 15.369 ; 15.369 ; 15.955 ;
; UDSn         ; RAM_DATA[13]  ; 15.261 ; 14.801 ; 14.801 ; 15.261 ;
; UDSn         ; RAM_DATA[14]  ; 14.904 ; 14.904 ; 14.904 ; 14.904 ;
; UDSn         ; RAM_DATA[15]  ; 15.110 ; 15.110 ; 15.110 ; 15.110 ;
; UDSn         ; RAM_DQM0H     ; 11.270 ; 11.116 ; 11.116 ; 11.270 ;
; UDSn         ; RAM_DQM0L     ; 10.689 ; 10.531 ; 10.531 ; 10.689 ;
; UDSn         ; RAM_DQM1H     ; 11.426 ; 11.272 ; 11.272 ; 11.426 ;
; UDSn         ; RAM_DQM1L     ; 10.679 ; 10.521 ; 10.521 ; 10.679 ;
; UDSn         ; RWn           ; 12.795 ; 12.795 ; 12.795 ; 12.795 ;
; UDSn         ; UDSn          ; 12.699 ; 12.699 ; 12.699 ; 12.699 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Propagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ADR[1]       ; DATA[0]       ; 11.432 ; 11.432 ; 11.432 ; 11.432 ;
; ADR[1]       ; DATA[1]       ; 11.044 ; 11.044 ; 11.044 ; 11.044 ;
; ADR[1]       ; DATA[2]       ; 10.838 ; 10.757 ; 10.757 ; 10.838 ;
; ADR[1]       ; DATA[3]       ; 11.211 ; 11.570 ; 11.570 ; 11.211 ;
; ADR[1]       ; DATA[4]       ; 10.228 ; 10.228 ; 10.228 ; 10.228 ;
; ADR[1]       ; DATA[5]       ; 11.343 ; 11.343 ; 11.343 ; 11.343 ;
; ADR[1]       ; DATA[6]       ; 10.463 ; 10.463 ; 10.463 ; 10.463 ;
; ADR[1]       ; DATA[7]       ; 11.040 ; 11.040 ; 11.040 ; 11.040 ;
; ADR[1]       ; DATA[8]       ; 10.629 ; 10.629 ; 10.629 ; 10.629 ;
; ADR[1]       ; DATA[9]       ; 10.487 ; 10.487 ; 10.487 ; 10.487 ;
; ADR[1]       ; DATA[10]      ; 10.819 ; 10.738 ; 10.738 ; 10.819 ;
; ADR[1]       ; DATA[11]      ; 11.902 ; 11.608 ; 11.608 ; 11.902 ;
; ADR[1]       ; DATA[12]      ; 10.953 ; 10.953 ; 10.953 ; 10.953 ;
; ADR[1]       ; DATA[13]      ; 11.237 ; 11.236 ; 11.236 ; 11.237 ;
; ADR[1]       ; DATA[14]      ; 11.299 ; 11.299 ; 11.299 ; 11.299 ;
; ADR[1]       ; DATA[15]      ; 11.380 ; 11.380 ; 11.380 ; 11.380 ;
; ADR[1]       ; RAM_DATA[0]   ; 9.611  ; 9.611  ; 9.611  ; 9.611  ;
; ADR[1]       ; RAM_DATA[1]   ; 10.129 ; 10.129 ; 10.129 ; 10.129 ;
; ADR[1]       ; RAM_DATA[2]   ; 9.995  ; 9.914  ; 9.914  ; 9.995  ;
; ADR[1]       ; RAM_DATA[3]   ; 10.308 ; 10.667 ; 10.667 ; 10.308 ;
; ADR[1]       ; RAM_DATA[4]   ; 10.357 ; 10.357 ; 10.357 ; 10.357 ;
; ADR[1]       ; RAM_DATA[5]   ; 10.002 ; 10.002 ; 10.002 ; 10.002 ;
; ADR[1]       ; RAM_DATA[6]   ; 10.294 ; 10.294 ; 10.294 ; 10.294 ;
; ADR[1]       ; RAM_DATA[7]   ; 10.722 ; 10.722 ; 10.722 ; 10.722 ;
; ADR[1]       ; RAM_DATA[8]   ; 10.240 ; 10.240 ; 10.240 ; 10.240 ;
; ADR[1]       ; RAM_DATA[9]   ; 9.858  ; 9.858  ; 9.858  ; 9.858  ;
; ADR[1]       ; RAM_DATA[10]  ; 10.956 ; 10.875 ; 10.875 ; 10.956 ;
; ADR[1]       ; RAM_DATA[11]  ; 10.267 ; 9.973  ; 9.973  ; 10.267 ;
; ADR[1]       ; RAM_DATA[12]  ; 11.017 ; 11.017 ; 11.017 ; 11.017 ;
; ADR[1]       ; RAM_DATA[13]  ; 10.088 ; 10.087 ; 10.087 ; 10.088 ;
; ADR[1]       ; RAM_DATA[14]  ; 10.415 ; 10.415 ; 10.415 ; 10.415 ;
; ADR[1]       ; RAM_DATA[15]  ; 10.338 ; 10.338 ; 10.338 ; 10.338 ;
; ADR[2]       ; DATA[0]       ; 11.523 ; 11.823 ; 11.823 ; 11.523 ;
; ADR[2]       ; DATA[1]       ; 11.513 ; 11.597 ; 11.597 ; 11.513 ;
; ADR[2]       ; DATA[2]       ; 11.280 ; 11.212 ; 11.212 ; 11.280 ;
; ADR[2]       ; DATA[3]       ; 11.665 ; 12.025 ; 12.025 ; 11.665 ;
; ADR[2]       ; DATA[4]       ; 10.606 ; 10.606 ; 10.606 ; 10.606 ;
; ADR[2]       ; DATA[5]       ; 11.095 ; 11.095 ; 11.095 ; 11.095 ;
; ADR[2]       ; DATA[6]       ; 10.707 ; 10.707 ; 10.707 ; 10.707 ;
; ADR[2]       ; DATA[7]       ; 11.494 ; 11.494 ; 11.494 ; 11.494 ;
; ADR[2]       ; DATA[8]       ; 10.720 ; 11.020 ; 11.020 ; 10.720 ;
; ADR[2]       ; DATA[9]       ; 10.956 ; 11.040 ; 11.040 ; 10.956 ;
; ADR[2]       ; DATA[10]      ; 11.261 ; 11.193 ; 11.193 ; 11.261 ;
; ADR[2]       ; DATA[11]      ; 12.254 ; 12.063 ; 12.063 ; 12.254 ;
; ADR[2]       ; DATA[12]      ; 11.331 ; 11.405 ; 11.405 ; 11.331 ;
; ADR[2]       ; DATA[13]      ; 10.989 ; 10.989 ; 10.989 ; 10.989 ;
; ADR[2]       ; DATA[14]      ; 11.543 ; 11.543 ; 11.543 ; 11.543 ;
; ADR[2]       ; DATA[15]      ; 11.744 ; 11.744 ; 11.744 ; 11.744 ;
; ADR[2]       ; RAM_DATA[0]   ; 9.702  ; 10.002 ; 10.002 ; 9.702  ;
; ADR[2]       ; RAM_DATA[1]   ; 10.598 ; 10.682 ; 10.682 ; 10.598 ;
; ADR[2]       ; RAM_DATA[2]   ; 10.437 ; 10.369 ; 10.369 ; 10.437 ;
; ADR[2]       ; RAM_DATA[3]   ; 10.762 ; 11.122 ; 11.122 ; 10.762 ;
; ADR[2]       ; RAM_DATA[4]   ; 10.735 ; 10.735 ; 10.735 ; 10.735 ;
; ADR[2]       ; RAM_DATA[5]   ; 9.754  ; 9.754  ; 9.754  ; 9.754  ;
; ADR[2]       ; RAM_DATA[6]   ; 10.538 ; 10.538 ; 10.538 ; 10.538 ;
; ADR[2]       ; RAM_DATA[7]   ; 11.176 ; 11.176 ; 11.176 ; 11.176 ;
; ADR[2]       ; RAM_DATA[8]   ; 10.331 ; 10.631 ; 10.631 ; 10.331 ;
; ADR[2]       ; RAM_DATA[9]   ; 10.327 ; 10.411 ; 10.411 ; 10.327 ;
; ADR[2]       ; RAM_DATA[10]  ; 11.398 ; 11.330 ; 11.330 ; 11.398 ;
; ADR[2]       ; RAM_DATA[11]  ; 10.619 ; 10.428 ; 10.428 ; 10.619 ;
; ADR[2]       ; RAM_DATA[12]  ; 11.395 ; 11.469 ; 11.469 ; 11.395 ;
; ADR[2]       ; RAM_DATA[13]  ; 9.840  ; 9.840  ; 9.840  ; 9.840  ;
; ADR[2]       ; RAM_DATA[14]  ; 10.659 ; 10.659 ; 10.659 ; 10.659 ;
; ADR[2]       ; RAM_DATA[15]  ; 10.702 ; 10.702 ; 10.702 ; 10.702 ;
; ADR[3]       ; DATA[0]       ; 11.456 ; 11.456 ; 11.456 ; 11.456 ;
; ADR[3]       ; DATA[1]       ; 11.370 ; 11.221 ; 11.221 ; 11.370 ;
; ADR[3]       ; DATA[2]       ; 10.776 ; 10.680 ; 10.680 ; 10.776 ;
; ADR[3]       ; DATA[3]       ; 11.173 ; 11.171 ; 11.171 ; 11.173 ;
; ADR[3]       ; DATA[4]       ; 10.226 ; 10.226 ; 10.226 ; 10.226 ;
; ADR[3]       ; DATA[5]       ; 11.330 ; 11.330 ; 11.330 ; 11.330 ;
; ADR[3]       ; DATA[6]       ; 10.258 ; 10.258 ; 10.258 ; 10.258 ;
; ADR[3]       ; DATA[7]       ; 11.000 ; 11.000 ; 11.000 ; 11.000 ;
; ADR[3]       ; DATA[8]       ; 10.653 ; 10.653 ; 10.653 ; 10.653 ;
; ADR[3]       ; DATA[9]       ; 10.859 ; 10.664 ; 10.664 ; 10.859 ;
; ADR[3]       ; DATA[10]      ; 10.757 ; 10.661 ; 10.661 ; 10.757 ;
; ADR[3]       ; DATA[11]      ; 11.646 ; 11.562 ; 11.562 ; 11.646 ;
; ADR[3]       ; DATA[12]      ; 11.042 ; 10.951 ; 10.951 ; 11.042 ;
; ADR[3]       ; DATA[13]      ; 11.196 ; 11.198 ; 11.198 ; 11.196 ;
; ADR[3]       ; DATA[14]      ; 11.094 ; 11.094 ; 11.094 ; 11.094 ;
; ADR[3]       ; DATA[15]      ; 11.182 ; 11.182 ; 11.182 ; 11.182 ;
; ADR[3]       ; RAM_DATA[0]   ; 9.635  ; 9.635  ; 9.635  ; 9.635  ;
; ADR[3]       ; RAM_DATA[1]   ; 10.455 ; 10.306 ; 10.306 ; 10.455 ;
; ADR[3]       ; RAM_DATA[2]   ; 9.933  ; 9.837  ; 9.837  ; 9.933  ;
; ADR[3]       ; RAM_DATA[3]   ; 10.270 ; 10.268 ; 10.268 ; 10.270 ;
; ADR[3]       ; RAM_DATA[4]   ; 10.355 ; 10.355 ; 10.355 ; 10.355 ;
; ADR[3]       ; RAM_DATA[5]   ; 9.989  ; 9.989  ; 9.989  ; 9.989  ;
; ADR[3]       ; RAM_DATA[6]   ; 10.089 ; 10.089 ; 10.089 ; 10.089 ;
; ADR[3]       ; RAM_DATA[7]   ; 10.682 ; 10.682 ; 10.682 ; 10.682 ;
; ADR[3]       ; RAM_DATA[8]   ; 10.264 ; 10.264 ; 10.264 ; 10.264 ;
; ADR[3]       ; RAM_DATA[9]   ; 10.230 ; 10.035 ; 10.035 ; 10.230 ;
; ADR[3]       ; RAM_DATA[10]  ; 10.894 ; 10.798 ; 10.798 ; 10.894 ;
; ADR[3]       ; RAM_DATA[11]  ; 10.011 ; 9.927  ; 9.927  ; 10.011 ;
; ADR[3]       ; RAM_DATA[12]  ; 11.106 ; 11.015 ; 11.015 ; 11.106 ;
; ADR[3]       ; RAM_DATA[13]  ; 10.047 ; 10.049 ; 10.049 ; 10.047 ;
; ADR[3]       ; RAM_DATA[14]  ; 10.210 ; 10.210 ; 10.210 ; 10.210 ;
; ADR[3]       ; RAM_DATA[15]  ; 10.140 ; 10.140 ; 10.140 ; 10.140 ;
; ADR[4]       ; DATA[0]       ; 11.605 ; 11.605 ; 11.605 ; 11.605 ;
; ADR[4]       ; DATA[1]       ; 11.150 ; 11.250 ; 11.250 ; 11.150 ;
; ADR[4]       ; DATA[2]       ; 10.561 ; 10.829 ; 10.829 ; 10.561 ;
; ADR[4]       ; DATA[3]       ; 11.265 ; 11.053 ; 11.053 ; 11.265 ;
; ADR[4]       ; DATA[4]       ; 10.388 ; 10.388 ; 10.388 ; 10.388 ;
; ADR[4]       ; DATA[5]       ; 11.334 ; 11.334 ; 11.334 ; 11.334 ;
; ADR[4]       ; DATA[6]       ; 10.267 ; 10.267 ; 10.267 ; 10.267 ;
; ADR[4]       ; DATA[7]       ; 10.882 ; 10.882 ; 10.882 ; 10.882 ;
; ADR[4]       ; DATA[8]       ; 10.802 ; 10.776 ; 10.776 ; 10.802 ;
; ADR[4]       ; DATA[9]       ; 10.593 ; 10.773 ; 10.773 ; 10.593 ;
; ADR[4]       ; DATA[10]      ; 10.542 ; 10.806 ; 10.806 ; 10.542 ;
; ADR[4]       ; DATA[11]      ; 11.412 ; 11.706 ; 11.706 ; 11.412 ;
; ADR[4]       ; DATA[12]      ; 10.924 ; 11.090 ; 11.090 ; 10.924 ;
; ADR[4]       ; DATA[13]      ; 11.078 ; 11.216 ; 11.216 ; 11.078 ;
; ADR[4]       ; DATA[14]      ; 11.103 ; 11.103 ; 11.103 ; 11.103 ;
; ADR[4]       ; DATA[15]      ; 11.222 ; 11.222 ; 11.222 ; 11.222 ;
; ADR[4]       ; RAM_DATA[0]   ; 9.784  ; 9.784  ; 9.784  ; 9.784  ;
; ADR[4]       ; RAM_DATA[1]   ; 10.235 ; 10.335 ; 10.335 ; 10.235 ;
; ADR[4]       ; RAM_DATA[2]   ; 9.718  ; 9.986  ; 9.986  ; 9.718  ;
; ADR[4]       ; RAM_DATA[3]   ; 10.362 ; 10.150 ; 10.150 ; 10.362 ;
; ADR[4]       ; RAM_DATA[4]   ; 10.517 ; 10.517 ; 10.517 ; 10.517 ;
; ADR[4]       ; RAM_DATA[5]   ; 9.993  ; 9.993  ; 9.993  ; 9.993  ;
; ADR[4]       ; RAM_DATA[6]   ; 10.098 ; 10.098 ; 10.098 ; 10.098 ;
; ADR[4]       ; RAM_DATA[7]   ; 10.564 ; 10.564 ; 10.564 ; 10.564 ;
; ADR[4]       ; RAM_DATA[8]   ; 10.413 ; 10.387 ; 10.387 ; 10.413 ;
; ADR[4]       ; RAM_DATA[9]   ; 9.964  ; 10.144 ; 10.144 ; 9.964  ;
; ADR[4]       ; RAM_DATA[10]  ; 10.679 ; 10.943 ; 10.943 ; 10.679 ;
; ADR[4]       ; RAM_DATA[11]  ; 9.777  ; 10.071 ; 10.071 ; 9.777  ;
; ADR[4]       ; RAM_DATA[12]  ; 10.988 ; 11.154 ; 11.154 ; 10.988 ;
; ADR[4]       ; RAM_DATA[13]  ; 9.929  ; 10.067 ; 10.067 ; 9.929  ;
; ADR[4]       ; RAM_DATA[14]  ; 10.219 ; 10.219 ; 10.219 ; 10.219 ;
; ADR[4]       ; RAM_DATA[15]  ; 10.180 ; 10.180 ; 10.180 ; 10.180 ;
; ADR[5]       ; DATA[0]       ; 11.722 ; 11.832 ; 11.832 ; 11.722 ;
; ADR[5]       ; DATA[1]       ; 11.293 ; 11.508 ; 11.508 ; 11.293 ;
; ADR[5]       ; DATA[2]       ; 11.040 ; 10.919 ; 10.919 ; 11.040 ;
; ADR[5]       ; DATA[3]       ; 11.096 ; 11.463 ; 11.463 ; 11.096 ;
; ADR[5]       ; DATA[4]       ; 10.703 ; 10.703 ; 10.703 ; 10.703 ;
; ADR[5]       ; DATA[5]       ; 11.405 ; 11.405 ; 11.405 ; 11.405 ;
; ADR[5]       ; DATA[6]       ; 10.558 ; 10.558 ; 10.558 ; 10.558 ;
; ADR[5]       ; DATA[7]       ; 10.925 ; 10.925 ; 10.925 ; 10.925 ;
; ADR[5]       ; DATA[8]       ; 10.819 ; 11.029 ; 11.029 ; 10.819 ;
; ADR[5]       ; DATA[9]       ; 11.131 ; 10.951 ; 10.951 ; 11.131 ;
; ADR[5]       ; DATA[10]      ; 10.849 ; 10.900 ; 10.900 ; 10.849 ;
; ADR[5]       ; DATA[11]      ; 12.064 ; 11.770 ; 11.770 ; 12.064 ;
; ADR[5]       ; DATA[12]      ; 11.133 ; 10.967 ; 10.967 ; 11.133 ;
; ADR[5]       ; DATA[13]      ; 11.259 ; 11.121 ; 11.121 ; 11.259 ;
; ADR[5]       ; DATA[14]      ; 11.240 ; 11.240 ; 11.240 ; 11.240 ;
; ADR[5]       ; DATA[15]      ; 11.265 ; 11.265 ; 11.265 ; 11.265 ;
; ADR[5]       ; RAM_DATA[0]   ; 9.901  ; 10.011 ; 10.011 ; 9.901  ;
; ADR[5]       ; RAM_DATA[1]   ; 10.378 ; 10.593 ; 10.593 ; 10.378 ;
; ADR[5]       ; RAM_DATA[2]   ; 10.197 ; 10.076 ; 10.076 ; 10.197 ;
; ADR[5]       ; RAM_DATA[3]   ; 10.193 ; 10.560 ; 10.560 ; 10.193 ;
; ADR[5]       ; RAM_DATA[4]   ; 10.832 ; 10.832 ; 10.832 ; 10.832 ;
; ADR[5]       ; RAM_DATA[5]   ; 10.064 ; 10.064 ; 10.064 ; 10.064 ;
; ADR[5]       ; RAM_DATA[6]   ; 10.389 ; 10.389 ; 10.389 ; 10.389 ;
; ADR[5]       ; RAM_DATA[7]   ; 10.607 ; 10.607 ; 10.607 ; 10.607 ;
; ADR[5]       ; RAM_DATA[8]   ; 10.430 ; 10.640 ; 10.640 ; 10.430 ;
; ADR[5]       ; RAM_DATA[9]   ; 10.502 ; 10.322 ; 10.322 ; 10.502 ;
; ADR[5]       ; RAM_DATA[10]  ; 10.986 ; 11.037 ; 11.037 ; 10.986 ;
; ADR[5]       ; RAM_DATA[11]  ; 10.429 ; 10.135 ; 10.135 ; 10.429 ;
; ADR[5]       ; RAM_DATA[12]  ; 11.197 ; 11.031 ; 11.031 ; 11.197 ;
; ADR[5]       ; RAM_DATA[13]  ; 10.110 ; 9.972  ; 9.972  ; 10.110 ;
; ADR[5]       ; RAM_DATA[14]  ; 10.356 ; 10.356 ; 10.356 ; 10.356 ;
; ADR[5]       ; RAM_DATA[15]  ; 10.223 ; 10.223 ; 10.223 ; 10.223 ;
; ASn          ; ACSI_RDn      ; 10.109 ; 10.109 ; 10.109 ; 10.109 ;
; ASn          ; ACSI_WRn      ; 10.099 ; 10.099 ; 10.099 ; 10.099 ;
; ASn          ; ASn           ; 10.471 ; 10.471 ; 10.471 ; 10.471 ;
; ASn          ; BUTTONn       ; 8.032  ;        ;        ; 8.032  ;
; ASn          ; CA1_OUT       ; 9.144  ;        ;        ; 9.144  ;
; ASn          ; CD[0]         ; 10.190 ; 10.190 ; 10.190 ; 10.190 ;
; ASn          ; CD[1]         ; 10.182 ; 10.182 ; 10.182 ; 10.182 ;
; ASn          ; CD[2]         ; 10.024 ; 10.024 ; 10.024 ; 10.024 ;
; ASn          ; CD[3]         ; 10.182 ; 10.182 ; 10.182 ; 10.182 ;
; ASn          ; CD[4]         ; 10.031 ; 10.031 ; 10.031 ; 10.031 ;
; ASn          ; CD[5]         ; 10.031 ; 10.031 ; 10.031 ; 10.031 ;
; ASn          ; CD[6]         ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; ASn          ; CD[7]         ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; ASn          ; DATA[0]       ; 10.533 ; 10.533 ; 10.533 ; 10.533 ;
; ASn          ; DATA[1]       ; 10.533 ; 10.533 ; 10.533 ; 10.533 ;
; ASn          ; DATA[2]       ; 10.513 ; 10.513 ; 10.513 ; 10.513 ;
; ASn          ; DATA[3]       ; 10.513 ; 10.513 ; 10.513 ; 10.513 ;
; ASn          ; DATA[4]       ; 9.976  ; 9.976  ; 9.976  ; 9.976  ;
; ASn          ; DATA[5]       ; 10.427 ; 10.427 ; 10.427 ; 10.427 ;
; ASn          ; DATA[6]       ; 9.821  ; 9.821  ; 9.821  ; 9.821  ;
; ASn          ; DATA[7]       ; 10.081 ; 10.081 ; 10.081 ; 10.081 ;
; ASn          ; DATA[8]       ; 10.225 ; 10.225 ; 10.225 ; 10.225 ;
; ASn          ; DATA[9]       ; 10.346 ; 10.346 ; 10.346 ; 10.346 ;
; ASn          ; DATA[10]      ; 10.369 ; 10.371 ; 10.371 ; 10.369 ;
; ASn          ; DATA[11]      ; 10.371 ; 10.371 ; 10.371 ; 10.371 ;
; ASn          ; DATA[12]      ; 10.007 ; 10.007 ; 10.007 ; 10.007 ;
; ASn          ; DATA[13]      ; 10.376 ; 10.376 ; 10.376 ; 10.376 ;
; ASn          ; DATA[14]      ; 9.579  ; 9.579  ; 9.579  ; 9.579  ;
; ASn          ; DATA[15]      ; 9.748  ; 9.748  ; 9.748  ; 9.748  ;
; ASn          ; DTACKn        ; 8.850  ; 8.850  ; 8.850  ; 8.850  ;
; ASn          ; FC[0]         ; 10.752 ; 10.752 ; 10.752 ; 10.752 ;
; ASn          ; FC[1]         ; 10.560 ; 10.560 ; 10.560 ; 10.560 ;
; ASn          ; FC[2]         ; 10.560 ; 10.560 ; 10.560 ; 10.560 ;
; ASn          ; FLASH_CEn     ; 9.331  ;        ;        ; 9.331  ;
; ASn          ; FLASH_OEn     ; 9.829  ;        ;        ; 9.829  ;
; ASn          ; IDE_CS0n      ; 7.334  ;        ;        ; 7.334  ;
; ASn          ; IDE_CS1n      ; 7.227  ;        ;        ; 7.227  ;
; ASn          ; IDE_D_EN_INn  ; 7.462  ;        ;        ; 7.462  ;
; ASn          ; IDE_D_EN_OUTn ; 7.242  ;        ;        ; 7.242  ;
; ASn          ; IDE_IORDn     ; 7.286  ;        ;        ; 7.286  ;
; ASn          ; IDE_IOWRn     ; 7.291  ;        ;        ; 7.291  ;
; ASn          ; JOY_RHn       ; 7.234  ;        ;        ; 7.234  ;
; ASn          ; JOY_RLn       ; 8.141  ;        ;        ; 8.141  ;
; ASn          ; JOY_WEn       ;        ; 8.113  ; 8.113  ;        ;
; ASn          ; JOY_WL        ;        ; 6.955  ; 6.955  ;        ;
; ASn          ; LDSn          ; 10.938 ; 10.938 ; 10.938 ; 10.938 ;
; ASn          ; RAM_DATA[0]   ; 9.240  ; 9.056  ; 9.056  ; 9.240  ;
; ASn          ; RAM_DATA[1]   ; 9.798  ; 9.630  ; 9.630  ; 9.798  ;
; ASn          ; RAM_DATA[2]   ; 9.762  ; 9.762  ; 9.762  ; 9.762  ;
; ASn          ; RAM_DATA[3]   ; 9.769  ; 9.769  ; 9.769  ; 9.769  ;
; ASn          ; RAM_DATA[4]   ; 10.105 ; 10.105 ; 10.105 ; 10.105 ;
; ASn          ; RAM_DATA[5]   ; 9.794  ; 9.794  ; 9.794  ; 9.794  ;
; ASn          ; RAM_DATA[6]   ; 9.652  ; 9.652  ; 9.652  ; 9.652  ;
; ASn          ; RAM_DATA[7]   ; 9.763  ; 9.763  ; 9.763  ; 9.763  ;
; ASn          ; RAM_DATA[8]   ; 9.836  ; 9.836  ; 9.836  ; 9.836  ;
; ASn          ; RAM_DATA[9]   ; 9.905  ; 9.889  ; 9.889  ; 9.905  ;
; ASn          ; RAM_DATA[10]  ; 10.506 ; 10.558 ; 10.558 ; 10.506 ;
; ASn          ; RAM_DATA[11]  ; 9.912  ; 9.912  ; 9.912  ; 9.912  ;
; ASn          ; RAM_DATA[12]  ; 10.071 ; 10.071 ; 10.071 ; 10.071 ;
; ASn          ; RAM_DATA[13]  ; 10.110 ; 10.110 ; 10.110 ; 10.110 ;
; ASn          ; RAM_DATA[14]  ; 8.695  ; 8.695  ; 8.695  ; 8.695  ;
; ASn          ; RAM_DATA[15]  ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; ASn          ; ROM0n         ; 8.356  ;        ;        ; 8.356  ;
; ASn          ; ROM1n         ; 9.187  ;        ;        ; 9.187  ;
; ASn          ; ROM2n         ; 8.505  ;        ;        ; 8.505  ;
; ASn          ; ROM3n         ; 8.015  ;        ;        ; 8.015  ;
; ASn          ; ROM4n         ; 7.827  ;        ;        ; 7.827  ;
; ASn          ; ROM5n         ; 9.036  ;        ;        ; 9.036  ;
; ASn          ; ROM6n         ; 8.250  ;        ;        ; 8.250  ;
; ASn          ; RWn           ; 11.034 ; 11.034 ; 11.034 ; 11.034 ;
; ASn          ; UDSn          ; 10.938 ; 10.938 ; 10.938 ; 10.938 ;
; CD[0]        ; DATA[0]       ; 10.525 ;        ;        ; 10.525 ;
; CD[0]        ; RAM_DATA[0]   ; 8.704  ;        ;        ; 8.704  ;
; CD[1]        ; DATA[1]       ; 10.005 ;        ;        ; 10.005 ;
; CD[1]        ; RAM_DATA[1]   ; 9.090  ;        ;        ; 9.090  ;
; CD[2]        ; DATA[2]       ; 10.162 ;        ;        ; 10.162 ;
; CD[2]        ; RAM_DATA[2]   ; 9.319  ;        ;        ; 9.319  ;
; CD[3]        ; DATA[3]       ; 10.805 ;        ;        ; 10.805 ;
; CD[3]        ; RAM_DATA[3]   ; 9.902  ;        ;        ; 9.902  ;
; CD[4]        ; DATA[4]       ; 9.384  ; 9.384  ; 9.384  ; 9.384  ;
; CD[4]        ; RAM_DATA[4]   ; 9.513  ; 9.513  ; 9.513  ; 9.513  ;
; CD[5]        ; DATA[5]       ; 10.227 ; 10.227 ; 10.227 ; 10.227 ;
; CD[5]        ; RAM_DATA[5]   ; 8.886  ; 8.886  ; 8.886  ; 8.886  ;
; CD[6]        ; DATA[6]       ; 10.225 ; 10.225 ; 10.225 ; 10.225 ;
; CD[6]        ; RAM_DATA[6]   ; 10.056 ; 10.056 ; 10.056 ; 10.056 ;
; CD[7]        ; DATA[7]       ; 10.825 ; 10.825 ; 10.825 ; 10.825 ;
; CD[7]        ; RAM_DATA[7]   ; 10.507 ; 10.507 ; 10.507 ; 10.507 ;
; COM_DCD      ; DATA[1]       ;        ; 11.516 ; 11.516 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 10.959 ; 10.959 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 10.601 ; 10.601 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 10.330 ; 10.330 ;        ;
; COM_RI       ; DATA[6]       ; 11.269 ; 11.269 ; 11.269 ; 11.269 ;
; COM_RI       ; DATA[14]      ; 12.105 ; 12.105 ; 12.105 ; 12.105 ;
; COM_RI       ; RAM_DATA[6]   ; 11.100 ; 11.100 ; 11.100 ; 11.100 ;
; COM_RI       ; RAM_DATA[14]  ; 11.221 ; 11.221 ; 11.221 ; 11.221 ;
; CONFIG[1]    ; DATA[15]      ; 11.093 ; 11.093 ; 11.093 ; 11.093 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 10.051 ; 10.051 ; 10.051 ; 10.051 ;
; CONFIG[2]    ; DATA[14]      ; 10.751 ; 10.751 ; 10.751 ; 10.751 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 9.867  ; 9.867  ; 9.867  ; 9.867  ;
; CONFIG[5]    ; ACSI_RDn      ; 9.675  ; 9.675  ; 9.675  ; 9.675  ;
; CONFIG[5]    ; ACSI_WRn      ; 9.665  ; 9.665  ; 9.665  ; 9.665  ;
; CONFIG[5]    ; ASn           ; 10.822 ; 10.822 ; 10.822 ; 10.822 ;
; CONFIG[5]    ; BUTTONn       ; 8.979  ; 9.116  ; 9.116  ; 8.979  ;
; CONFIG[5]    ; CA1_OUT       ; 8.710  ; 8.847  ; 8.847  ; 8.710  ;
; CONFIG[5]    ; CD[0]         ; 9.756  ; 9.756  ; 9.756  ; 9.756  ;
; CONFIG[5]    ; CD[1]         ; 9.748  ; 9.748  ; 9.748  ; 9.748  ;
; CONFIG[5]    ; CD[2]         ; 9.590  ; 9.590  ; 9.590  ; 9.590  ;
; CONFIG[5]    ; CD[3]         ; 9.748  ; 9.748  ; 9.748  ; 9.748  ;
; CONFIG[5]    ; CD[4]         ; 9.597  ; 9.597  ; 9.597  ; 9.597  ;
; CONFIG[5]    ; CD[5]         ; 9.597  ; 9.597  ; 9.597  ; 9.597  ;
; CONFIG[5]    ; CD[6]         ; 9.566  ; 9.566  ; 9.566  ; 9.566  ;
; CONFIG[5]    ; CD[7]         ; 9.566  ; 9.566  ; 9.566  ; 9.566  ;
; CONFIG[5]    ; DATA[0]       ; 11.208 ; 11.208 ; 11.208 ; 11.208 ;
; CONFIG[5]    ; DATA[1]       ; 11.208 ; 11.208 ; 11.208 ; 11.208 ;
; CONFIG[5]    ; DATA[2]       ; 11.063 ; 11.063 ; 11.063 ; 11.063 ;
; CONFIG[5]    ; DATA[3]       ; 11.178 ; 11.178 ; 11.178 ; 11.178 ;
; CONFIG[5]    ; DATA[4]       ; 11.082 ; 11.082 ; 11.082 ; 11.082 ;
; CONFIG[5]    ; DATA[5]       ; 11.102 ; 11.102 ; 11.102 ; 11.102 ;
; CONFIG[5]    ; DATA[6]       ; 10.927 ; 10.927 ; 10.927 ; 10.927 ;
; CONFIG[5]    ; DATA[7]       ; 11.002 ; 11.002 ; 11.002 ; 11.002 ;
; CONFIG[5]    ; DATA[8]       ; 10.926 ; 10.926 ; 10.926 ; 10.926 ;
; CONFIG[5]    ; DATA[9]       ; 11.021 ; 11.021 ; 11.021 ; 11.021 ;
; CONFIG[5]    ; DATA[10]      ; 10.863 ; 10.863 ; 10.863 ; 10.863 ;
; CONFIG[5]    ; DATA[11]      ; 11.046 ; 11.046 ; 11.046 ; 11.046 ;
; CONFIG[5]    ; DATA[12]      ; 11.051 ; 11.051 ; 11.051 ; 11.051 ;
; CONFIG[5]    ; DATA[13]      ; 11.051 ; 11.051 ; 11.051 ; 11.051 ;
; CONFIG[5]    ; DATA[14]      ; 10.968 ; 10.968 ; 10.968 ; 10.968 ;
; CONFIG[5]    ; DATA[15]      ; 11.137 ; 11.137 ; 11.137 ; 11.137 ;
; CONFIG[5]    ; DTACKn        ; 9.063  ; 9.063  ; 9.063  ; 9.063  ;
; CONFIG[5]    ; FC[0]         ; 11.103 ; 11.103 ; 11.103 ; 11.103 ;
; CONFIG[5]    ; FC[1]         ; 10.911 ; 10.911 ; 10.911 ; 10.911 ;
; CONFIG[5]    ; FC[2]         ; 10.911 ; 10.911 ; 10.911 ; 10.911 ;
; CONFIG[5]    ; FLASH_CEn     ; 9.545  ; 9.545  ; 9.545  ; 9.545  ;
; CONFIG[5]    ; FLASH_OEn     ; 10.043 ; 10.043 ; 10.043 ; 10.043 ;
; CONFIG[5]    ; IDE_CS0n      ; 9.044  ; 9.044  ; 9.044  ; 9.044  ;
; CONFIG[5]    ; IDE_CS1n      ; 8.714  ; 8.714  ; 8.714  ; 8.714  ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 8.851  ; 8.851  ; 8.851  ; 8.851  ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 8.759  ; 8.759  ; 8.759  ; 8.759  ;
; CONFIG[5]    ; IDE_IORDn     ; 8.460  ; 8.460  ; 8.460  ; 8.460  ;
; CONFIG[5]    ; IDE_IOWRn     ; 9.631  ; 9.631  ; 9.631  ; 9.631  ;
; CONFIG[5]    ; JOY_RHn       ; 8.838  ; 8.975  ; 8.975  ; 8.838  ;
; CONFIG[5]    ; JOY_RLn       ; 9.745  ; 9.882  ; 9.882  ; 9.745  ;
; CONFIG[5]    ; JOY_WEn       ; 9.854  ; 9.717  ; 9.717  ; 9.854  ;
; CONFIG[5]    ; JOY_WL        ; 8.696  ; 8.559  ; 8.559  ; 8.696  ;
; CONFIG[5]    ; LDSn          ; 11.289 ; 11.289 ; 11.289 ; 11.289 ;
; CONFIG[5]    ; RAM_BA[1]     ; 8.326  ; 8.630  ; 8.630  ; 8.326  ;
; CONFIG[5]    ; RAM_CAS0n     ; 8.188  ; 8.188  ; 8.188  ; 8.188  ;
; CONFIG[5]    ; RAM_CAS1n     ; 7.776  ; 7.776  ; 7.776  ; 7.776  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 9.807  ; 9.807  ; 9.807  ; 9.807  ;
; CONFIG[5]    ; RAM_DATA[1]   ; 10.846 ; 10.938 ; 10.938 ; 10.846 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 10.220 ; 10.220 ; 10.220 ; 10.220 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 10.275 ; 10.275 ; 10.275 ; 10.275 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 11.211 ; 11.211 ; 11.211 ; 11.211 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 10.849 ; 10.849 ; 10.849 ; 10.849 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 10.758 ; 10.758 ; 10.758 ; 10.758 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 10.869 ; 10.869 ; 10.869 ; 10.869 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 10.537 ; 10.537 ; 10.537 ; 10.537 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 10.561 ; 10.561 ; 10.561 ; 10.561 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 11.000 ; 11.000 ; 11.000 ; 11.000 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 10.773 ; 10.773 ; 10.773 ; 10.773 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 11.149 ; 11.149 ; 11.149 ; 11.149 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 10.601 ; 10.601 ; 10.601 ; 10.601 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 10.084 ; 10.084 ; 10.084 ; 10.084 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 10.095 ; 10.095 ; 10.095 ; 10.095 ;
; CONFIG[5]    ; RAM_RAS0n     ; 8.996  ; 8.996  ; 8.996  ; 8.996  ;
; CONFIG[5]    ; RAM_RAS1n     ; 8.838  ; 8.838  ; 8.838  ; 8.838  ;
; CONFIG[5]    ; ROM0n         ; 8.344  ; 8.417  ; 8.417  ; 8.344  ;
; CONFIG[5]    ; ROM1n         ; 9.171  ; 9.244  ; 9.244  ; 9.171  ;
; CONFIG[5]    ; ROM2n         ; 8.719  ; 8.719  ; 8.719  ; 8.719  ;
; CONFIG[5]    ; ROM3n         ; 8.896  ; 8.896  ; 8.896  ; 8.896  ;
; CONFIG[5]    ; ROM4n         ; 8.704  ; 8.704  ; 8.704  ; 8.704  ;
; CONFIG[5]    ; ROM5n         ; 9.328  ; 9.328  ; 9.328  ; 9.328  ;
; CONFIG[5]    ; ROM6n         ; 9.131  ; 9.131  ; 9.131  ; 9.131  ;
; CONFIG[5]    ; RWn           ; 11.385 ; 11.385 ; 11.385 ; 11.385 ;
; CONFIG[5]    ; UDSn          ; 11.289 ; 11.289 ; 11.289 ; 11.289 ;
; DATA[0]      ; DATA[0]       ; 9.208  ;        ;        ; 9.208  ;
; DATA[0]      ; RAM_DATA[0]   ; 7.387  ;        ;        ; 7.387  ;
; DATA[1]      ; DATA[1]       ; 9.014  ;        ;        ; 9.014  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.099  ;        ;        ; 8.099  ;
; DATA[2]      ; DATA[2]       ; 8.729  ;        ;        ; 8.729  ;
; DATA[2]      ; RAM_DATA[2]   ; 7.886  ;        ;        ; 7.886  ;
; DATA[3]      ; DATA[3]       ; 8.764  ;        ;        ; 8.764  ;
; DATA[3]      ; RAM_DATA[3]   ; 7.861  ;        ;        ; 7.861  ;
; DATA[4]      ; DATA[4]       ; 8.020  ; 8.020  ; 8.020  ; 8.020  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.149  ; 8.149  ; 8.149  ; 8.149  ;
; DATA[5]      ; DATA[5]       ; 9.476  ;        ;        ; 9.476  ;
; DATA[5]      ; RAM_DATA[5]   ; 8.135  ;        ;        ; 8.135  ;
; DATA[6]      ; DATA[6]       ; 8.593  ; 8.593  ; 8.593  ; 8.593  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.424  ; 8.424  ; 8.424  ; 8.424  ;
; DATA[7]      ; DATA[7]       ; 8.852  ;        ;        ; 8.852  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.534  ;        ;        ; 8.534  ;
; DATA[8]      ; DATA[8]       ; 8.794  ;        ;        ; 8.794  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.405  ;        ;        ; 8.405  ;
; DATA[9]      ; DATA[9]       ; 8.342  ;        ;        ; 8.342  ;
; DATA[9]      ; RAM_DATA[9]   ; 7.713  ;        ;        ; 7.713  ;
; DATA[10]     ; DATA[10]      ; 8.800  ;        ;        ; 8.800  ;
; DATA[10]     ; RAM_DATA[10]  ; 8.937  ;        ;        ; 8.937  ;
; DATA[11]     ; DATA[11]      ; 9.665  ;        ;        ; 9.665  ;
; DATA[11]     ; RAM_DATA[11]  ; 8.030  ;        ;        ; 8.030  ;
; DATA[12]     ; DATA[12]      ; 7.724  ;        ;        ; 7.724  ;
; DATA[12]     ; RAM_DATA[12]  ; 7.788  ;        ;        ; 7.788  ;
; DATA[13]     ; DATA[13]      ; 9.072  ;        ;        ; 9.072  ;
; DATA[13]     ; RAM_DATA[13]  ; 7.923  ;        ;        ; 7.923  ;
; DATA[14]     ; DATA[14]      ; 7.943  ;        ;        ; 7.943  ;
; DATA[14]     ; RAM_DATA[14]  ; 7.059  ;        ;        ; 7.059  ;
; DATA[15]     ; DATA[15]      ; 8.165  ;        ;        ; 8.165  ;
; DATA[15]     ; RAM_DATA[15]  ; 7.123  ;        ;        ; 7.123  ;
; FC[0]        ; ACSI_RDn      ; 8.808  ; 8.808  ; 8.808  ; 8.808  ;
; FC[0]        ; ACSI_WRn      ; 8.798  ; 8.798  ; 8.798  ; 8.798  ;
; FC[0]        ; ASn           ; 9.300  ; 9.300  ; 9.300  ; 9.300  ;
; FC[0]        ; BUTTONn       ; 8.544  ; 8.544  ; 8.544  ; 8.544  ;
; FC[0]        ; CA1_OUT       ; 7.843  ; 7.843  ; 7.843  ; 7.843  ;
; FC[0]        ; CD[0]         ; 8.889  ; 8.889  ; 8.889  ; 8.889  ;
; FC[0]        ; CD[1]         ; 8.881  ; 8.881  ; 8.881  ; 8.881  ;
; FC[0]        ; CD[2]         ; 8.723  ; 8.723  ; 8.723  ; 8.723  ;
; FC[0]        ; CD[3]         ; 8.881  ; 8.881  ; 8.881  ; 8.881  ;
; FC[0]        ; CD[4]         ; 8.730  ; 8.730  ; 8.730  ; 8.730  ;
; FC[0]        ; CD[5]         ; 8.730  ; 8.730  ; 8.730  ; 8.730  ;
; FC[0]        ; CD[6]         ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; FC[0]        ; CD[7]         ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; FC[0]        ; DATA[0]       ; 10.784 ; 10.706 ; 10.706 ; 10.784 ;
; FC[0]        ; DATA[1]       ; 10.684 ; 10.374 ; 10.374 ; 10.684 ;
; FC[0]        ; DATA[2]       ; 10.317 ; 10.317 ; 10.317 ; 10.317 ;
; FC[0]        ; DATA[3]       ; 10.715 ; 10.715 ; 10.715 ; 10.715 ;
; FC[0]        ; DATA[4]       ; 10.503 ; 10.503 ; 10.503 ; 10.503 ;
; FC[0]        ; DATA[5]       ; 10.678 ; 10.678 ; 10.678 ; 10.678 ;
; FC[0]        ; DATA[6]       ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; FC[0]        ; DATA[7]       ; 10.578 ; 10.578 ; 10.578 ; 10.578 ;
; FC[0]        ; DATA[8]       ; 10.131 ; 10.131 ; 10.131 ; 10.131 ;
; FC[0]        ; DATA[9]       ; 10.263 ; 10.263 ; 10.263 ; 10.263 ;
; FC[0]        ; DATA[10]      ; 10.437 ; 10.437 ; 10.437 ; 10.437 ;
; FC[0]        ; DATA[11]      ; 10.622 ; 10.622 ; 10.622 ; 10.622 ;
; FC[0]        ; DATA[12]      ; 10.584 ; 10.584 ; 10.584 ; 10.584 ;
; FC[0]        ; DATA[13]      ; 10.627 ; 10.627 ; 10.627 ; 10.627 ;
; FC[0]        ; DATA[14]      ; 10.376 ; 10.376 ; 10.376 ; 10.376 ;
; FC[0]        ; DATA[15]      ; 10.545 ; 10.545 ; 10.545 ; 10.545 ;
; FC[0]        ; DTACKn        ; 7.363  ; 7.363  ; 7.363  ; 7.363  ;
; FC[0]        ; FC[0]         ; 9.581  ; 9.581  ; 9.581  ; 9.581  ;
; FC[0]        ; FC[1]         ; 9.389  ; 9.389  ; 9.389  ; 9.389  ;
; FC[0]        ; FC[2]         ; 9.389  ; 9.389  ; 9.389  ; 9.389  ;
; FC[0]        ; FLASH_CEn     ; 10.027 ; 10.027 ; 10.027 ; 10.027 ;
; FC[0]        ; FLASH_OEn     ; 10.525 ; 10.525 ; 10.525 ; 10.525 ;
; FC[0]        ; IDE_CS0n      ; 8.131  ;        ;        ; 8.131  ;
; FC[0]        ; IDE_CS1n      ; 8.024  ;        ;        ; 8.024  ;
; FC[0]        ; IDE_D_EN_INn  ; 8.259  ;        ;        ; 8.259  ;
; FC[0]        ; IDE_D_EN_OUTn ; 8.039  ;        ;        ; 8.039  ;
; FC[0]        ; IDE_IORDn     ; 8.083  ;        ;        ; 8.083  ;
; FC[0]        ; IDE_IOWRn     ; 8.088  ;        ;        ; 8.088  ;
; FC[0]        ; JOY_RHn       ; 8.031  ; 8.396  ; 8.396  ; 8.031  ;
; FC[0]        ; JOY_RLn       ; 8.938  ; 9.313  ; 9.313  ; 8.938  ;
; FC[0]        ; JOY_WEn       ; 9.285  ; 8.910  ; 8.910  ; 9.285  ;
; FC[0]        ; JOY_WL        ; 8.062  ; 7.752  ; 7.752  ; 8.062  ;
; FC[0]        ; LDSn          ; 9.767  ; 9.767  ; 9.767  ; 9.767  ;
; FC[0]        ; RAM_DATA[0]   ; 9.069  ; 8.885  ; 8.885  ; 9.069  ;
; FC[0]        ; RAM_DATA[1]   ; 9.769  ; 9.459  ; 9.459  ; 9.769  ;
; FC[0]        ; RAM_DATA[2]   ; 9.474  ; 9.474  ; 9.474  ; 9.474  ;
; FC[0]        ; RAM_DATA[3]   ; 9.812  ; 9.812  ; 9.812  ; 9.812  ;
; FC[0]        ; RAM_DATA[4]   ; 10.632 ; 10.632 ; 10.632 ; 10.632 ;
; FC[0]        ; RAM_DATA[5]   ; 10.101 ; 10.101 ; 10.101 ; 10.101 ;
; FC[0]        ; RAM_DATA[6]   ; 10.096 ; 10.096 ; 10.096 ; 10.096 ;
; FC[0]        ; RAM_DATA[7]   ; 10.332 ; 10.332 ; 10.332 ; 10.332 ;
; FC[0]        ; RAM_DATA[8]   ; 9.742  ; 9.742  ; 9.742  ; 9.742  ;
; FC[0]        ; RAM_DATA[9]   ; 9.634  ; 9.634  ; 9.634  ; 9.634  ;
; FC[0]        ; RAM_DATA[10]  ; 10.574 ; 10.574 ; 10.574 ; 10.574 ;
; FC[0]        ; RAM_DATA[11]  ; 9.704  ; 9.704  ; 9.704  ; 9.704  ;
; FC[0]        ; RAM_DATA[12]  ; 10.648 ; 10.648 ; 10.648 ; 10.648 ;
; FC[0]        ; RAM_DATA[13]  ; 9.552  ; 9.552  ; 9.552  ; 9.552  ;
; FC[0]        ; RAM_DATA[14]  ; 9.492  ; 9.492  ; 9.492  ; 9.492  ;
; FC[0]        ; RAM_DATA[15]  ; 9.503  ; 9.503  ; 9.503  ; 9.503  ;
; FC[0]        ; ROM0n         ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[0]        ; ROM1n         ; 9.758  ; 9.758  ; 9.758  ; 9.758  ;
; FC[0]        ; ROM2n         ; 9.201  ; 9.201  ; 9.201  ; 9.201  ;
; FC[0]        ; ROM3n         ; 8.711  ; 8.711  ; 8.711  ; 8.711  ;
; FC[0]        ; ROM4n         ; 8.523  ; 8.523  ; 8.523  ; 8.523  ;
; FC[0]        ; ROM5n         ; 9.607  ; 9.607  ; 9.607  ; 9.607  ;
; FC[0]        ; ROM6n         ; 8.946  ; 8.946  ; 8.946  ; 8.946  ;
; FC[0]        ; RWn           ; 9.863  ; 9.863  ; 9.863  ; 9.863  ;
; FC[0]        ; UDSn          ; 9.767  ; 9.767  ; 9.767  ; 9.767  ;
; FC[1]        ; ACSI_RDn      ; 8.937  ; 8.937  ; 8.937  ; 8.937  ;
; FC[1]        ; ACSI_WRn      ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[1]        ; ASn           ; 9.429  ; 9.429  ; 9.429  ; 9.429  ;
; FC[1]        ; BUTTONn       ; 7.774  ; 7.774  ; 7.774  ; 7.774  ;
; FC[1]        ; CA1_OUT       ; 7.972  ; 7.972  ; 7.972  ; 7.972  ;
; FC[1]        ; CD[0]         ; 9.018  ; 9.018  ; 9.018  ; 9.018  ;
; FC[1]        ; CD[1]         ; 9.010  ; 9.010  ; 9.010  ; 9.010  ;
; FC[1]        ; CD[2]         ; 8.852  ; 8.852  ; 8.852  ; 8.852  ;
; FC[1]        ; CD[3]         ; 9.010  ; 9.010  ; 9.010  ; 9.010  ;
; FC[1]        ; CD[4]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; FC[1]        ; CD[5]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; FC[1]        ; CD[6]         ; 8.828  ; 8.828  ; 8.828  ; 8.828  ;
; FC[1]        ; CD[7]         ; 8.828  ; 8.828  ; 8.828  ; 8.828  ;
; FC[1]        ; DATA[0]       ; 10.582 ; 10.582 ; 10.582 ; 10.582 ;
; FC[1]        ; DATA[1]       ; 10.582 ; 10.496 ; 10.496 ; 10.582 ;
; FC[1]        ; DATA[2]       ; 10.446 ; 10.446 ; 10.446 ; 10.446 ;
; FC[1]        ; DATA[3]       ; 10.562 ; 10.562 ; 10.562 ; 10.562 ;
; FC[1]        ; DATA[4]       ; 10.394 ; 10.394 ; 10.394 ; 10.394 ;
; FC[1]        ; DATA[5]       ; 10.476 ; 10.476 ; 10.476 ; 10.476 ;
; FC[1]        ; DATA[6]       ; 10.070 ; 10.070 ; 10.070 ; 10.070 ;
; FC[1]        ; DATA[7]       ; 10.376 ; 10.376 ; 10.376 ; 10.376 ;
; FC[1]        ; DATA[8]       ; 10.260 ; 10.260 ; 10.260 ; 10.260 ;
; FC[1]        ; DATA[9]       ; 10.392 ; 10.392 ; 10.392 ; 10.392 ;
; FC[1]        ; DATA[10]      ; 10.401 ; 10.401 ; 10.401 ; 10.401 ;
; FC[1]        ; DATA[11]      ; 10.420 ; 10.420 ; 10.420 ; 10.420 ;
; FC[1]        ; DATA[12]      ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; FC[1]        ; DATA[13]      ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; FC[1]        ; DATA[14]      ; 10.181 ; 10.181 ; 10.181 ; 10.181 ;
; FC[1]        ; DATA[15]      ; 10.350 ; 10.350 ; 10.350 ; 10.350 ;
; FC[1]        ; DTACKn        ; 7.413  ; 7.413  ; 7.413  ; 7.413  ;
; FC[1]        ; FC[0]         ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[1]        ; FC[1]         ; 9.518  ; 9.518  ; 9.518  ; 9.518  ;
; FC[1]        ; FC[2]         ; 9.518  ; 9.518  ; 9.518  ; 9.518  ;
; FC[1]        ; FLASH_CEn     ; 9.257  ; 9.257  ; 9.257  ; 9.257  ;
; FC[1]        ; FLASH_OEn     ; 9.755  ; 9.755  ; 9.755  ; 9.755  ;
; FC[1]        ; IDE_CS0n      ; 7.936  ;        ;        ; 7.936  ;
; FC[1]        ; IDE_CS1n      ; 7.829  ;        ;        ; 7.829  ;
; FC[1]        ; IDE_D_EN_INn  ; 8.064  ;        ;        ; 8.064  ;
; FC[1]        ; IDE_D_EN_OUTn ; 7.844  ;        ;        ; 7.844  ;
; FC[1]        ; IDE_IORDn     ; 7.888  ;        ;        ; 7.888  ;
; FC[1]        ; IDE_IOWRn     ; 7.893  ;        ;        ; 7.893  ;
; FC[1]        ; JOY_RHn       ; 7.626  ; 7.626  ; 7.626  ; 7.626  ;
; FC[1]        ; JOY_RLn       ; 8.543  ; 8.543  ; 8.543  ; 8.543  ;
; FC[1]        ; JOY_WEn       ; 8.515  ; 8.515  ; 8.515  ; 8.515  ;
; FC[1]        ; JOY_WL        ; 7.292  ; 7.292  ; 7.292  ; 7.292  ;
; FC[1]        ; LDSn          ; 9.896  ; 9.896  ; 9.896  ; 9.896  ;
; FC[1]        ; RAM_DATA[0]   ; 9.191  ; 9.007  ; 9.007  ; 9.191  ;
; FC[1]        ; RAM_DATA[1]   ; 9.778  ; 9.581  ; 9.581  ; 9.778  ;
; FC[1]        ; RAM_DATA[2]   ; 9.603  ; 9.603  ; 9.603  ; 9.603  ;
; FC[1]        ; RAM_DATA[3]   ; 9.934  ; 9.934  ; 9.934  ; 9.934  ;
; FC[1]        ; RAM_DATA[4]   ; 10.523 ; 10.523 ; 10.523 ; 10.523 ;
; FC[1]        ; RAM_DATA[5]   ; 9.906  ; 9.906  ; 9.906  ; 9.906  ;
; FC[1]        ; RAM_DATA[6]   ; 9.901  ; 9.901  ; 9.901  ; 9.901  ;
; FC[1]        ; RAM_DATA[7]   ; 10.365 ; 10.365 ; 10.365 ; 10.365 ;
; FC[1]        ; RAM_DATA[8]   ; 9.871  ; 9.871  ; 9.871  ; 9.871  ;
; FC[1]        ; RAM_DATA[9]   ; 9.763  ; 9.763  ; 9.763  ; 9.763  ;
; FC[1]        ; RAM_DATA[10]  ; 10.538 ; 10.538 ; 10.538 ; 10.538 ;
; FC[1]        ; RAM_DATA[11]  ; 9.833  ; 9.833  ; 9.833  ; 9.833  ;
; FC[1]        ; RAM_DATA[12]  ; 10.673 ; 10.673 ; 10.673 ; 10.673 ;
; FC[1]        ; RAM_DATA[13]  ; 9.681  ; 9.681  ; 9.681  ; 9.681  ;
; FC[1]        ; RAM_DATA[14]  ; 9.297  ; 9.297  ; 9.297  ; 9.297  ;
; FC[1]        ; RAM_DATA[15]  ; 9.308  ; 9.308  ; 9.308  ; 9.308  ;
; FC[1]        ; ROM0n         ; 8.157  ; 8.157  ; 8.157  ; 8.157  ;
; FC[1]        ; ROM1n         ; 8.988  ; 8.988  ; 8.988  ; 8.988  ;
; FC[1]        ; ROM2n         ; 8.431  ; 8.431  ; 8.431  ; 8.431  ;
; FC[1]        ; ROM3n         ; 7.941  ; 7.941  ; 7.941  ; 7.941  ;
; FC[1]        ; ROM4n         ; 7.753  ; 7.753  ; 7.753  ; 7.753  ;
; FC[1]        ; ROM5n         ; 8.837  ; 8.837  ; 8.837  ; 8.837  ;
; FC[1]        ; ROM6n         ; 8.176  ; 8.176  ; 8.176  ; 8.176  ;
; FC[1]        ; RWn           ; 9.992  ; 9.992  ; 9.992  ; 9.992  ;
; FC[1]        ; UDSn          ; 9.896  ; 9.896  ; 9.896  ; 9.896  ;
; FC[2]        ; ACSI_RDn      ; 8.894  ; 8.894  ; 8.894  ; 8.894  ;
; FC[2]        ; ACSI_WRn      ; 8.884  ; 8.884  ; 8.884  ; 8.884  ;
; FC[2]        ; ASn           ; 9.386  ; 9.386  ; 9.386  ; 9.386  ;
; FC[2]        ; BUTTONn       ; 8.607  ;        ;        ; 8.607  ;
; FC[2]        ; CA1_OUT       ; 9.048  ; 7.929  ; 7.929  ; 9.048  ;
; FC[2]        ; CD[0]         ; 8.975  ; 8.975  ; 8.975  ; 8.975  ;
; FC[2]        ; CD[1]         ; 8.967  ; 8.967  ; 8.967  ; 8.967  ;
; FC[2]        ; CD[2]         ; 8.809  ; 8.809  ; 8.809  ; 8.809  ;
; FC[2]        ; CD[3]         ; 8.967  ; 8.967  ; 8.967  ; 8.967  ;
; FC[2]        ; CD[4]         ; 8.816  ; 8.816  ; 8.816  ; 8.816  ;
; FC[2]        ; CD[5]         ; 8.816  ; 8.816  ; 8.816  ; 8.816  ;
; FC[2]        ; CD[6]         ; 8.785  ; 8.785  ; 8.785  ; 8.785  ;
; FC[2]        ; CD[7]         ; 8.785  ; 8.785  ; 8.785  ; 8.785  ;
; FC[2]        ; DATA[0]       ; 10.544 ; 10.544 ; 10.544 ; 10.544 ;
; FC[2]        ; DATA[1]       ; 10.544 ; 10.449 ; 10.449 ; 10.544 ;
; FC[2]        ; DATA[2]       ; 10.403 ; 10.509 ; 10.509 ; 10.403 ;
; FC[2]        ; DATA[3]       ; 10.524 ; 10.524 ; 10.524 ; 10.524 ;
; FC[2]        ; DATA[4]       ; 10.349 ; 10.349 ; 10.349 ; 10.349 ;
; FC[2]        ; DATA[5]       ; 10.438 ; 10.438 ; 10.438 ; 10.438 ;
; FC[2]        ; DATA[6]       ; 10.025 ; 10.025 ; 10.025 ; 10.025 ;
; FC[2]        ; DATA[7]       ; 10.338 ; 10.338 ; 10.338 ; 10.338 ;
; FC[2]        ; DATA[8]       ; 10.272 ; 10.217 ; 10.217 ; 10.272 ;
; FC[2]        ; DATA[9]       ; 10.349 ; 10.357 ; 10.357 ; 10.349 ;
; FC[2]        ; DATA[10]      ; 10.382 ; 10.382 ; 10.382 ; 10.382 ;
; FC[2]        ; DATA[11]      ; 10.382 ; 10.382 ; 10.382 ; 10.382 ;
; FC[2]        ; DATA[12]      ; 10.387 ; 10.387 ; 10.387 ; 10.387 ;
; FC[2]        ; DATA[13]      ; 10.387 ; 10.387 ; 10.387 ; 10.387 ;
; FC[2]        ; DATA[14]      ; 10.154 ; 10.154 ; 10.154 ; 10.154 ;
; FC[2]        ; DATA[15]      ; 10.323 ; 10.323 ; 10.323 ; 10.323 ;
; FC[2]        ; DTACKn        ; 7.249  ; 7.249  ; 7.249  ; 7.249  ;
; FC[2]        ; FC[0]         ; 9.667  ; 9.667  ; 9.667  ; 9.667  ;
; FC[2]        ; FC[1]         ; 9.475  ; 9.475  ; 9.475  ; 9.475  ;
; FC[2]        ; FC[2]         ; 9.475  ; 9.475  ; 9.475  ; 9.475  ;
; FC[2]        ; FLASH_CEn     ; 9.906  ;        ;        ; 9.906  ;
; FC[2]        ; FLASH_OEn     ; 10.404 ;        ;        ; 10.404 ;
; FC[2]        ; IDE_CS0n      ; 7.909  ;        ;        ; 7.909  ;
; FC[2]        ; IDE_CS1n      ; 7.802  ;        ;        ; 7.802  ;
; FC[2]        ; IDE_D_EN_INn  ; 8.037  ;        ;        ; 8.037  ;
; FC[2]        ; IDE_D_EN_OUTn ; 7.817  ;        ;        ; 7.817  ;
; FC[2]        ; IDE_IORDn     ; 7.861  ;        ;        ; 7.861  ;
; FC[2]        ; IDE_IOWRn     ; 7.866  ;        ;        ; 7.866  ;
; FC[2]        ; JOY_RHn       ; 7.809  ; 8.190  ; 8.190  ; 7.809  ;
; FC[2]        ; JOY_RLn       ; 8.716  ; 9.107  ; 9.107  ; 8.716  ;
; FC[2]        ; JOY_WEn       ; 9.079  ; 8.688  ; 8.688  ; 9.079  ;
; FC[2]        ; JOY_WL        ; 7.856  ; 7.530  ; 7.530  ; 7.856  ;
; FC[2]        ; LDSn          ; 9.853  ; 9.853  ; 9.853  ; 9.853  ;
; FC[2]        ; RAM_DATA[0]   ; 9.144  ; 8.960  ; 8.960  ; 9.144  ;
; FC[2]        ; RAM_DATA[1]   ; 9.957  ; 9.534  ; 9.534  ; 9.957  ;
; FC[2]        ; RAM_DATA[2]   ; 9.560  ; 9.666  ; 9.666  ; 9.560  ;
; FC[2]        ; RAM_DATA[3]   ; 9.887  ; 9.887  ; 9.887  ; 9.887  ;
; FC[2]        ; RAM_DATA[4]   ; 10.478 ; 10.478 ; 10.478 ; 10.478 ;
; FC[2]        ; RAM_DATA[5]   ; 9.861  ; 9.861  ; 9.861  ; 9.861  ;
; FC[2]        ; RAM_DATA[6]   ; 9.856  ; 9.856  ; 9.856  ; 9.856  ;
; FC[2]        ; RAM_DATA[7]   ; 10.338 ; 10.338 ; 10.338 ; 10.338 ;
; FC[2]        ; RAM_DATA[8]   ; 9.883  ; 9.828  ; 9.828  ; 9.883  ;
; FC[2]        ; RAM_DATA[9]   ; 9.720  ; 9.748  ; 9.748  ; 9.720  ;
; FC[2]        ; RAM_DATA[10]  ; 10.753 ; 10.660 ; 10.660 ; 10.753 ;
; FC[2]        ; RAM_DATA[11]  ; 10.112 ; 9.790  ; 9.790  ; 10.112 ;
; FC[2]        ; RAM_DATA[12]  ; 10.646 ; 10.646 ; 10.646 ; 10.646 ;
; FC[2]        ; RAM_DATA[13]  ; 10.004 ; 9.638  ; 9.638  ; 10.004 ;
; FC[2]        ; RAM_DATA[14]  ; 9.270  ; 9.270  ; 9.270  ; 9.270  ;
; FC[2]        ; RAM_DATA[15]  ; 9.281  ; 9.281  ; 9.281  ; 9.281  ;
; FC[2]        ; ROM0n         ; 8.931  ;        ;        ; 8.931  ;
; FC[2]        ; ROM1n         ; 9.762  ;        ;        ; 9.762  ;
; FC[2]        ; ROM2n         ; 9.080  ;        ;        ; 9.080  ;
; FC[2]        ; ROM3n         ; 8.590  ;        ;        ; 8.590  ;
; FC[2]        ; ROM4n         ; 8.402  ;        ;        ; 8.402  ;
; FC[2]        ; ROM5n         ; 9.611  ;        ;        ; 9.611  ;
; FC[2]        ; ROM6n         ; 8.825  ;        ;        ; 8.825  ;
; FC[2]        ; RWn           ; 9.949  ; 9.949  ; 9.949  ; 9.949  ;
; FC[2]        ; UDSn          ; 9.853  ; 9.853  ; 9.853  ; 9.853  ;
; HDINTn       ; DATA[5]       ; 12.021 ; 12.021 ; 12.021 ; 12.021 ;
; HDINTn       ; DATA[13]      ; 11.915 ;        ;        ; 11.915 ;
; HDINTn       ; RAM_DATA[5]   ; 10.680 ; 10.680 ; 10.680 ; 10.680 ;
; HDINTn       ; RAM_DATA[13]  ; 10.766 ;        ;        ; 10.766 ;
; IDE_INTRQ    ; DATA[5]       ; 12.138 ; 12.138 ; 12.138 ; 12.138 ;
; IDE_INTRQ    ; DATA[13]      ;        ; 12.032 ; 12.032 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ; 10.797 ; 10.797 ; 10.797 ; 10.797 ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 10.883 ; 10.883 ;        ;
; LDSn         ; ACSI_RDn      ; 7.770  ; 7.770  ; 7.770  ; 7.770  ;
; LDSn         ; ACSI_WRn      ; 7.760  ; 7.760  ; 7.760  ; 7.760  ;
; LDSn         ; ASn           ; 9.507  ; 9.507  ; 9.507  ; 9.507  ;
; LDSn         ; BUTTONn       ; 8.267  ;        ;        ; 8.267  ;
; LDSn         ; CA1_OUT       ; 6.805  ;        ;        ; 6.805  ;
; LDSn         ; CD[0]         ; 7.851  ; 7.851  ; 7.851  ; 7.851  ;
; LDSn         ; CD[1]         ; 7.843  ; 7.843  ; 7.843  ; 7.843  ;
; LDSn         ; CD[2]         ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; LDSn         ; CD[3]         ; 7.843  ; 7.843  ; 7.843  ; 7.843  ;
; LDSn         ; CD[4]         ; 7.692  ; 7.692  ; 7.692  ; 7.692  ;
; LDSn         ; CD[5]         ; 7.692  ; 7.692  ; 7.692  ; 7.692  ;
; LDSn         ; CD[6]         ; 7.661  ; 7.661  ; 7.661  ; 7.661  ;
; LDSn         ; CD[7]         ; 7.661  ; 7.661  ; 7.661  ; 7.661  ;
; LDSn         ; DATA[0]       ; 10.470 ; 10.286 ; 10.286 ; 10.470 ;
; LDSn         ; DATA[1]       ; 10.451 ; 9.954  ; 9.954  ; 10.451 ;
; LDSn         ; DATA[2]       ; 10.014 ; 10.014 ; 10.014 ; 10.014 ;
; LDSn         ; DATA[3]       ; 10.295 ; 10.295 ; 10.295 ; 10.295 ;
; LDSn         ; DATA[4]       ; 10.168 ; 10.168 ; 10.168 ; 10.168 ;
; LDSn         ; DATA[5]       ; 10.440 ; 10.440 ; 10.440 ; 10.440 ;
; LDSn         ; DATA[6]       ; 10.027 ; 10.027 ; 10.027 ; 10.027 ;
; LDSn         ; DATA[7]       ; 10.287 ; 10.287 ; 10.287 ; 10.287 ;
; LDSn         ; DATA[8]       ; 10.008 ; 10.008 ; 10.008 ; 10.008 ;
; LDSn         ; DATA[9]       ; 10.286 ; 10.286 ; 10.286 ; 10.286 ;
; LDSn         ; DATA[10]      ; 10.138 ; 10.138 ; 10.138 ; 10.138 ;
; LDSn         ; DATA[11]      ; 10.384 ; 10.384 ; 10.384 ; 10.384 ;
; LDSn         ; DATA[12]      ; 10.030 ; 10.030 ; 10.030 ; 10.030 ;
; LDSn         ; DATA[13]      ; 10.389 ; 10.389 ; 10.389 ; 10.389 ;
; LDSn         ; DATA[14]      ; 9.506  ; 9.506  ; 9.506  ; 9.506  ;
; LDSn         ; DATA[15]      ; 9.675  ; 9.675  ; 9.675  ; 9.675  ;
; LDSn         ; DTACKn        ; 7.886  ; 7.886  ; 7.886  ; 7.886  ;
; LDSn         ; FC[0]         ; 9.788  ; 9.788  ; 9.788  ; 9.788  ;
; LDSn         ; FC[1]         ; 9.596  ; 9.596  ; 9.596  ; 9.596  ;
; LDSn         ; FC[2]         ; 9.596  ; 9.596  ; 9.596  ; 9.596  ;
; LDSn         ; IDE_IORDn     ; 7.299  ;        ;        ; 7.299  ;
; LDSn         ; IDE_IOWRn     ; 7.309  ;        ;        ; 7.309  ;
; LDSn         ; JOY_RLn       ; 8.031  ;        ;        ; 8.031  ;
; LDSn         ; JOY_WEn       ;        ; 8.003  ; 8.003  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.784  ; 6.784  ;        ;
; LDSn         ; LDSn          ; 9.974  ; 9.974  ; 9.974  ; 9.974  ;
; LDSn         ; RAM_CAS0n     ; 9.685  ;        ;        ; 9.685  ;
; LDSn         ; RAM_CAS1n     ; 9.271  ;        ;        ; 9.271  ;
; LDSn         ; RAM_DATA[0]   ; 8.649  ; 8.465  ; 8.465  ; 8.649  ;
; LDSn         ; RAM_DATA[1]   ; 9.536  ; 9.039  ; 9.039  ; 9.536  ;
; LDSn         ; RAM_DATA[2]   ; 9.171  ; 9.171  ; 9.171  ; 9.171  ;
; LDSn         ; RAM_DATA[3]   ; 9.392  ; 9.392  ; 9.392  ; 9.392  ;
; LDSn         ; RAM_DATA[4]   ; 10.297 ; 10.297 ; 10.297 ; 10.297 ;
; LDSn         ; RAM_DATA[5]   ; 9.907  ; 9.907  ; 9.907  ; 9.907  ;
; LDSn         ; RAM_DATA[6]   ; 9.858  ; 9.858  ; 9.858  ; 9.858  ;
; LDSn         ; RAM_DATA[7]   ; 9.969  ; 9.969  ; 9.969  ; 9.969  ;
; LDSn         ; RAM_DATA[8]   ; 9.619  ; 9.619  ; 9.619  ; 9.619  ;
; LDSn         ; RAM_DATA[9]   ; 9.657  ; 9.657  ; 9.657  ; 9.657  ;
; LDSn         ; RAM_DATA[10]  ; 10.275 ; 10.275 ; 10.275 ; 10.275 ;
; LDSn         ; RAM_DATA[11]  ; 9.724  ; 9.724  ; 9.724  ; 9.724  ;
; LDSn         ; RAM_DATA[12]  ; 10.094 ; 10.094 ; 10.094 ; 10.094 ;
; LDSn         ; RAM_DATA[13]  ; 9.678  ; 9.678  ; 9.678  ; 9.678  ;
; LDSn         ; RAM_DATA[14]  ; 8.622  ; 8.622  ; 8.622  ; 8.622  ;
; LDSn         ; RAM_DATA[15]  ; 8.633  ; 8.633  ; 8.633  ; 8.633  ;
; LDSn         ; RAM_DQM0H     ; 9.110  ; 9.027  ; 9.027  ; 9.110  ;
; LDSn         ; RAM_DQM0L     ; 8.600  ; 10.701 ; 10.701 ; 8.600  ;
; LDSn         ; RAM_DQM1H     ; 9.266  ; 9.183  ; 9.183  ; 9.266  ;
; LDSn         ; RAM_DQM1L     ; 8.590  ; 10.691 ; 10.691 ; 8.590  ;
; LDSn         ; RWn           ; 10.070 ; 10.070 ; 10.070 ; 10.070 ;
; LDSn         ; UDSn          ; 9.974  ; 9.974  ; 9.974  ; 9.974  ;
; LPT_BSY      ; DATA[0]       ; 10.508 ;        ;        ; 10.508 ;
; LPT_BSY      ; DATA[8]       ; 9.705  ;        ;        ; 9.705  ;
; LPT_BSY      ; RAM_DATA[0]   ; 8.687  ;        ;        ; 8.687  ;
; LPT_BSY      ; RAM_DATA[8]   ; 9.316  ;        ;        ; 9.316  ;
; LPT_D[0]     ; DATA[0]       ; 10.269 ;        ;        ; 10.269 ;
; LPT_D[0]     ; DATA[8]       ; 9.466  ;        ;        ; 9.466  ;
; LPT_D[0]     ; RAM_DATA[0]   ; 8.448  ;        ;        ; 8.448  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 9.077  ;        ;        ; 9.077  ;
; LPT_D[1]     ; DATA[1]       ; 10.091 ;        ;        ; 10.091 ;
; LPT_D[1]     ; DATA[9]       ; 9.693  ;        ;        ; 9.693  ;
; LPT_D[1]     ; RAM_DATA[1]   ; 9.176  ;        ;        ; 9.176  ;
; LPT_D[1]     ; RAM_DATA[9]   ; 9.064  ;        ;        ; 9.064  ;
; LPT_D[2]     ; DATA[2]       ; 9.895  ;        ;        ; 9.895  ;
; LPT_D[2]     ; DATA[10]      ; 9.394  ;        ;        ; 9.394  ;
; LPT_D[2]     ; RAM_DATA[2]   ; 9.052  ;        ;        ; 9.052  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.531  ;        ;        ; 9.531  ;
; LPT_D[3]     ; DATA[3]       ; 10.501 ;        ;        ; 10.501 ;
; LPT_D[3]     ; DATA[11]      ; 11.086 ;        ;        ; 11.086 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 9.598  ;        ;        ; 9.598  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.451  ;        ;        ; 9.451  ;
; LPT_D[4]     ; DATA[4]       ; 11.131 ; 11.131 ; 11.131 ; 11.131 ;
; LPT_D[4]     ; DATA[12]      ; 10.859 ;        ;        ; 10.859 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 11.260 ; 11.260 ; 11.260 ; 11.260 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 10.923 ;        ;        ; 10.923 ;
; LPT_D[5]     ; DATA[5]       ; 11.281 ; 11.281 ; 11.281 ; 11.281 ;
; LPT_D[5]     ; DATA[13]      ; 10.479 ;        ;        ; 10.479 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 9.940  ; 9.940  ; 9.940  ; 9.940  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 9.330  ;        ;        ; 9.330  ;
; LPT_D[6]     ; DATA[6]       ; 11.221 ; 11.221 ; 11.221 ; 11.221 ;
; LPT_D[6]     ; DATA[14]      ; 10.609 ; 10.609 ; 10.609 ; 10.609 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 11.052 ; 11.052 ; 11.052 ; 11.052 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 9.725  ; 9.725  ; 9.725  ; 9.725  ;
; LPT_D[7]     ; DATA[7]       ; 10.478 ; 10.478 ; 10.478 ; 10.478 ;
; LPT_D[7]     ; DATA[15]      ; 10.663 ; 10.663 ; 10.663 ; 10.663 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 10.160 ; 10.160 ; 10.160 ; 10.160 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 9.621  ; 9.621  ; 9.621  ; 9.621  ;
; MIDI_IN      ; MIDI_TLR      ; 4.723  ;        ;        ; 4.723  ;
; RAM_DATA[0]  ; DATA[0]       ; 11.727 ;        ;        ; 11.727 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 9.906  ;        ;        ; 9.906  ;
; RAM_DATA[1]  ; DATA[1]       ; 11.087 ;        ;        ; 11.087 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.172 ;        ;        ; 10.172 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.602 ;        ;        ; 10.602 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 9.759  ;        ;        ; 9.759  ;
; RAM_DATA[3]  ; DATA[3]       ; 11.042 ;        ;        ; 11.042 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.139 ;        ;        ; 10.139 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.830  ; 9.830  ; 9.830  ; 9.830  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 9.959  ; 9.959  ; 9.959  ; 9.959  ;
; RAM_DATA[5]  ; DATA[5]       ; 11.415 ; 11.415 ; 11.415 ; 11.415 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 10.074 ; 10.074 ; 10.074 ; 10.074 ;
; RAM_DATA[6]  ; DATA[6]       ; 11.568 ; 11.568 ; 11.568 ; 11.568 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.399 ; 11.399 ; 11.399 ; 11.399 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.234 ; 10.234 ; 10.234 ; 10.234 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 9.916  ; 9.916  ; 9.916  ; 9.916  ;
; RAM_DATA[8]  ; DATA[8]       ; 10.292 ;        ;        ; 10.292 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 9.903  ;        ;        ; 9.903  ;
; RAM_DATA[9]  ; DATA[9]       ; 10.476 ;        ;        ; 10.476 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 9.847  ;        ;        ; 9.847  ;
; RAM_DATA[10] ; DATA[10]      ; 10.205 ;        ;        ; 10.205 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 10.342 ;        ;        ; 10.342 ;
; RAM_DATA[11] ; DATA[11]      ; 11.770 ;        ;        ; 11.770 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.135 ;        ;        ; 10.135 ;
; RAM_DATA[12] ; DATA[12]      ; 11.247 ;        ;        ; 11.247 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 11.311 ;        ;        ; 11.311 ;
; RAM_DATA[13] ; DATA[13]      ; 11.221 ;        ;        ; 11.221 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.072 ;        ;        ; 10.072 ;
; RAM_DATA[14] ; DATA[14]      ; 11.089 ; 11.089 ; 11.089 ; 11.089 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.205 ; 10.205 ; 10.205 ; 10.205 ;
; RAM_DATA[15] ; DATA[15]      ; 11.462 ; 11.462 ; 11.462 ; 11.462 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 10.420 ; 10.420 ; 10.420 ; 10.420 ;
; RWn          ; ACSI_RDn      ; 8.200  ; 7.895  ; 7.895  ; 8.200  ;
; RWn          ; ACSI_WRn      ; 7.885  ; 8.190  ; 8.190  ; 7.885  ;
; RWn          ; ASn           ; 9.515  ; 9.515  ; 9.515  ; 9.515  ;
; RWn          ; BUTTONn       ;        ; 9.805  ; 9.805  ;        ;
; RWn          ; CA1_OUT       ;        ; 7.235  ; 7.235  ;        ;
; RWn          ; CD[0]         ; 7.746  ; 7.746  ; 7.746  ; 7.746  ;
; RWn          ; CD[1]         ; 7.629  ; 7.629  ; 7.629  ; 7.629  ;
; RWn          ; CD[2]         ; 7.580  ; 7.580  ; 7.580  ; 7.580  ;
; RWn          ; CD[3]         ; 7.738  ; 7.738  ; 7.738  ; 7.738  ;
; RWn          ; CD[4]         ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; RWn          ; CD[5]         ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; RWn          ; CD[6]         ; 7.556  ; 7.556  ; 7.556  ; 7.556  ;
; RWn          ; CD[7]         ; 7.556  ; 7.556  ; 7.556  ; 7.556  ;
; RWn          ; DATA[0]       ; 10.534 ; 10.712 ; 10.712 ; 10.534 ;
; RWn          ; DATA[1]       ; 10.217 ; 9.859  ; 9.859  ; 10.217 ;
; RWn          ; DATA[2]       ; 10.355 ; 10.244 ; 10.244 ; 10.355 ;
; RWn          ; DATA[3]       ; 10.683 ; 10.554 ; 10.554 ; 10.683 ;
; RWn          ; DATA[4]       ; 10.085 ; 10.085 ; 10.085 ; 10.085 ;
; RWn          ; DATA[5]       ; 11.031 ; 11.031 ; 11.031 ; 11.031 ;
; RWn          ; DATA[6]       ; 9.859  ; 9.859  ; 9.859  ; 9.859  ;
; RWn          ; DATA[7]       ; 10.571 ; 10.571 ; 10.571 ; 10.571 ;
; RWn          ; DATA[8]       ; 10.272 ; 10.171 ; 10.171 ; 10.272 ;
; RWn          ; DATA[9]       ; 10.470 ; 10.290 ; 10.290 ; 10.470 ;
; RWn          ; DATA[10]      ; 10.507 ; 10.239 ; 10.239 ; 10.507 ;
; RWn          ; DATA[11]      ; 11.403 ; 11.109 ; 11.109 ; 11.403 ;
; RWn          ; DATA[12]      ; 10.502 ; 10.502 ; 10.502 ; 10.502 ;
; RWn          ; DATA[13]      ; 11.058 ; 10.925 ; 10.925 ; 11.058 ;
; RWn          ; DATA[14]      ; 10.007 ; 10.007 ; 10.007 ; 10.007 ;
; RWn          ; DATA[15]      ; 10.079 ; 10.079 ; 10.079 ; 10.079 ;
; RWn          ; DTACKn        ; 7.769  ; 7.769  ; 7.769  ; 7.769  ;
; RWn          ; FC[0]         ; 9.796  ; 9.796  ; 9.796  ; 9.796  ;
; RWn          ; FC[1]         ; 9.604  ; 9.604  ; 9.604  ; 9.604  ;
; RWn          ; FC[2]         ; 9.604  ; 9.604  ; 9.604  ; 9.604  ;
; RWn          ; FLASH_CEn     ;        ; 11.017 ; 11.017 ;        ;
; RWn          ; FLASH_OEn     ;        ; 11.515 ; 11.515 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 9.038  ; 9.038  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 8.858  ;        ;        ; 8.858  ;
; RWn          ; IDE_IORDn     ;        ; 8.940  ; 8.940  ;        ;
; RWn          ; IDE_IOWRn     ; 8.967  ;        ;        ; 8.967  ;
; RWn          ; JOY_RHn       ; 9.495  ; 8.661  ; 8.661  ; 9.495  ;
; RWn          ; JOY_RLn       ; 10.412 ; 9.571  ; 9.571  ; 10.412 ;
; RWn          ; JOY_WEn       ; 9.543  ; 10.384 ; 10.384 ; 9.543  ;
; RWn          ; JOY_WL        ; 9.161  ; 8.268  ; 8.268  ; 9.161  ;
; RWn          ; LDSn          ; 9.982  ; 9.982  ; 9.982  ; 9.982  ;
; RWn          ; RAM_DATA[0]   ; 8.474  ; 8.474  ; 8.474  ; 8.474  ;
; RWn          ; RAM_DATA[1]   ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; RWn          ; RAM_DATA[2]   ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; RWn          ; RAM_DATA[3]   ; 9.053  ; 9.053  ; 9.053  ; 9.053  ;
; RWn          ; RAM_DATA[4]   ; 9.053  ; 9.053  ; 9.053  ; 9.053  ;
; RWn          ; RAM_DATA[5]   ; 9.467  ; 9.467  ; 9.467  ; 9.467  ;
; RWn          ; RAM_DATA[6]   ; 9.267  ; 9.267  ; 9.267  ; 9.267  ;
; RWn          ; RAM_DATA[7]   ; 9.467  ; 9.467  ; 9.467  ; 9.467  ;
; RWn          ; RAM_DATA[8]   ; 8.947  ; 8.947  ; 8.947  ; 8.947  ;
; RWn          ; RAM_DATA[9]   ; 8.947  ; 8.947  ; 8.947  ; 8.947  ;
; RWn          ; RAM_DATA[10]  ; 8.947  ; 8.947  ; 8.947  ; 8.947  ;
; RWn          ; RAM_DATA[11]  ; 8.937  ; 8.937  ; 8.937  ; 8.937  ;
; RWn          ; RAM_DATA[12]  ; 8.800  ; 8.800  ; 8.800  ; 8.800  ;
; RWn          ; RAM_DATA[13]  ; 8.800  ; 8.800  ; 8.800  ; 8.800  ;
; RWn          ; RAM_DATA[14]  ; 8.591  ; 8.591  ; 8.591  ; 8.591  ;
; RWn          ; RAM_DATA[15]  ; 8.591  ; 8.591  ; 8.591  ; 8.591  ;
; RWn          ; RAM_DQM0H     ;        ; 8.839  ; 8.839  ;        ;
; RWn          ; RAM_DQM0L     ;        ; 8.251  ; 8.251  ;        ;
; RWn          ; RAM_DQM1H     ;        ; 8.995  ; 8.995  ;        ;
; RWn          ; RAM_DQM1L     ;        ; 8.241  ; 8.241  ;        ;
; RWn          ; RAM_WEn       ; 9.417  ;        ;        ; 9.417  ;
; RWn          ; ROM0n         ;        ; 9.796  ; 9.796  ;        ;
; RWn          ; ROM1n         ;        ; 10.627 ; 10.627 ;        ;
; RWn          ; ROM2n         ;        ; 10.191 ; 10.191 ;        ;
; RWn          ; ROM3n         ;        ; 9.701  ; 9.701  ;        ;
; RWn          ; ROM4n         ;        ; 9.513  ; 9.513  ;        ;
; RWn          ; ROM5n         ;        ; 10.476 ; 10.476 ;        ;
; RWn          ; ROM6n         ;        ; 9.936  ; 9.936  ;        ;
; RWn          ; RWn           ; 10.078 ; 10.078 ; 10.078 ; 10.078 ;
; RWn          ; UDSn          ; 9.982  ; 9.982  ; 9.982  ; 9.982  ;
; SCSI_ACKn    ; CD[0]         ; 7.951  ; 7.951  ; 7.951  ; 7.951  ;
; SCSI_ATNn    ; CD[1]         ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; SCSI_BSYn    ; CD[6]         ;        ; 7.019  ; 7.019  ;        ;
; SCSI_D[0]    ; CD[0]         ; 8.485  ; 8.485  ; 8.485  ; 8.485  ;
; SCSI_D[1]    ; CD[1]         ; 8.138  ; 8.138  ; 8.138  ; 8.138  ;
; SCSI_D[2]    ; CD[2]         ;        ; 7.702  ; 7.702  ;        ;
; SCSI_D[3]    ; CD[3]         ; 8.804  ; 8.804  ; 8.804  ; 8.804  ;
; SCSI_D[4]    ; CD[4]         ; 6.442  ; 6.442  ; 6.442  ; 6.442  ;
; SCSI_D[5]    ; CD[5]         ; 6.256  ; 6.256  ; 6.256  ; 6.256  ;
; SCSI_D[6]    ; CD[6]         ; 7.643  ; 7.643  ; 7.643  ; 7.643  ;
; SCSI_D[7]    ; CD[7]         ;        ; 7.825  ; 7.825  ;        ;
; SCSI_DCn     ; CD[3]         ; 7.961  ; 7.961  ; 7.961  ; 7.961  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 7.254  ; 7.254  ; 7.254  ; 7.254  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.983  ; 7.983  ; 7.983  ; 7.983  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.983  ; 7.983  ; 7.983  ; 7.983  ;
; SCSI_DCn     ; SCSI_DP       ; 7.860  ; 7.860  ; 7.860  ; 7.860  ;
; SCSI_DP      ; CD[0]         ; 8.140  ; 8.140  ; 8.140  ; 8.140  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.638  ; 7.638  ;        ;
; SCSI_IOn     ; CD[3]         ; 9.153  ; 9.153  ; 9.153  ; 9.153  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.662  ; 7.442  ; 7.442  ; 6.662  ;
; SCSI_IOn     ; SCSI_D[0]     ; 7.258  ; 7.258  ; 7.258  ; 7.258  ;
; SCSI_IOn     ; SCSI_D[1]     ; 7.258  ; 7.258  ; 7.258  ; 7.258  ;
; SCSI_IOn     ; SCSI_D[2]     ; 7.363  ; 7.363  ; 7.363  ; 7.363  ;
; SCSI_IOn     ; SCSI_D[3]     ; 7.363  ; 7.363  ; 7.363  ; 7.363  ;
; SCSI_IOn     ; SCSI_D[4]     ; 7.382  ; 7.382  ; 7.382  ; 7.382  ;
; SCSI_IOn     ; SCSI_D[5]     ; 7.382  ; 7.382  ; 7.382  ; 7.382  ;
; SCSI_IOn     ; SCSI_D[6]     ; 7.391  ; 7.391  ; 7.391  ; 7.391  ;
; SCSI_IOn     ; SCSI_D[7]     ; 7.391  ; 7.391  ; 7.391  ; 7.391  ;
; SCSI_IOn     ; SCSI_DP       ; 7.268  ; 7.268  ; 7.268  ; 7.268  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.116  ;        ;        ; 6.116  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.098  ; 6.098  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.794  ; 8.794  ; 8.794  ; 8.794  ;
; SCSI_MSGn    ; CD[4]         ;        ; 6.001  ; 6.001  ;        ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.083  ; 7.083  ; 7.083  ; 7.083  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.679  ; 7.679  ; 7.679  ; 7.679  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.679  ; 7.679  ; 7.679  ; 7.679  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.784  ; 7.784  ; 7.784  ; 7.784  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.784  ; 7.784  ; 7.784  ; 7.784  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.803  ; 7.803  ; 7.803  ; 7.803  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.803  ; 7.803  ; 7.803  ; 7.803  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.812  ; 7.812  ; 7.812  ; 7.812  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.812  ; 7.812  ; 7.812  ; 7.812  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.689  ; 7.689  ; 7.689  ; 7.689  ;
; SCSI_REQn    ; CD[3]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; SCSI_REQn    ; CD[5]         ;        ; 5.946  ; 5.946  ;        ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 7.148  ;        ;        ; 7.148  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.849  ; 7.849  ; 7.849  ; 7.849  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.849  ; 7.849  ; 7.849  ; 7.849  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.868  ; 7.868  ; 7.868  ; 7.868  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.868  ; 7.868  ; 7.868  ; 7.868  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SCSI_REQn    ; SCSI_DP       ; 7.754  ; 7.754  ; 7.754  ; 7.754  ;
; SCSI_RSTn    ; CD[7]         ;        ; 7.478  ; 7.478  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.067  ; 7.067  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 7.169  ; 7.169  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 7.212  ; 7.212  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.074  ;        ;        ; 6.074  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.273  ;        ;        ; 6.273  ;
; SD_RESETn    ; COM_TxD       ; 8.327  ; 8.327  ; 8.327  ; 8.327  ;
; UDSn         ; ACSI_RDn      ; 9.213  ; 9.213  ; 9.213  ; 9.213  ;
; UDSn         ; ACSI_WRn      ; 9.203  ; 9.203  ; 9.203  ; 9.203  ;
; UDSn         ; ASn           ; 9.958  ; 9.958  ; 9.958  ; 9.958  ;
; UDSn         ; CA1_OUT       ; 8.248  ;        ;        ; 8.248  ;
; UDSn         ; CD[0]         ; 9.294  ; 9.294  ; 9.294  ; 9.294  ;
; UDSn         ; CD[1]         ; 9.286  ; 9.286  ; 9.286  ; 9.286  ;
; UDSn         ; CD[2]         ; 9.128  ; 9.128  ; 9.128  ; 9.128  ;
; UDSn         ; CD[3]         ; 9.286  ; 9.286  ; 9.286  ; 9.286  ;
; UDSn         ; CD[4]         ; 9.135  ; 9.135  ; 9.135  ; 9.135  ;
; UDSn         ; CD[5]         ; 9.135  ; 9.135  ; 9.135  ; 9.135  ;
; UDSn         ; CD[6]         ; 9.104  ; 9.104  ; 9.104  ; 9.104  ;
; UDSn         ; CD[7]         ; 9.104  ; 9.104  ; 9.104  ; 9.104  ;
; UDSn         ; DATA[0]       ; 11.203 ; 11.203 ; 11.203 ; 11.203 ;
; UDSn         ; DATA[1]       ; 11.203 ; 11.203 ; 11.203 ; 11.203 ;
; UDSn         ; DATA[2]       ; 11.183 ; 10.975 ; 10.975 ; 11.183 ;
; UDSn         ; DATA[3]       ; 11.183 ; 11.183 ; 11.183 ; 11.183 ;
; UDSn         ; DATA[4]       ; 10.721 ; 10.721 ; 10.721 ; 10.721 ;
; UDSn         ; DATA[5]       ; 11.097 ; 11.097 ; 11.097 ; 11.097 ;
; UDSn         ; DATA[6]       ; 10.566 ; 10.566 ; 10.566 ; 10.566 ;
; UDSn         ; DATA[7]       ; 10.826 ; 10.826 ; 10.826 ; 10.826 ;
; UDSn         ; DATA[8]       ; 10.170 ; 10.170 ; 10.170 ; 10.170 ;
; UDSn         ; DATA[9]       ; 10.374 ; 10.374 ; 10.374 ; 10.374 ;
; UDSn         ; DATA[10]      ; 10.390 ; 10.390 ; 10.390 ; 10.390 ;
; UDSn         ; DATA[11]      ; 11.041 ; 11.041 ; 11.041 ; 11.041 ;
; UDSn         ; DATA[12]      ; 10.395 ; 10.395 ; 10.395 ; 10.395 ;
; UDSn         ; DATA[13]      ; 10.892 ; 10.892 ; 10.892 ; 10.892 ;
; UDSn         ; DATA[14]      ; 10.048 ; 10.048 ; 10.048 ; 10.048 ;
; UDSn         ; DATA[15]      ; 10.217 ; 10.217 ; 10.217 ; 10.217 ;
; UDSn         ; DTACKn        ; 8.022  ; 8.022  ; 8.022  ; 8.022  ;
; UDSn         ; FC[0]         ; 10.239 ; 10.239 ; 10.239 ; 10.239 ;
; UDSn         ; FC[1]         ; 10.047 ; 10.047 ; 10.047 ; 10.047 ;
; UDSn         ; FC[2]         ; 10.047 ; 10.047 ; 10.047 ; 10.047 ;
; UDSn         ; JOY_RHn       ; 7.689  ;        ;        ; 7.689  ;
; UDSn         ; LDSn          ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; UDSn         ; RAM_CAS0n     ; 9.515  ;        ;        ; 9.515  ;
; UDSn         ; RAM_CAS1n     ; 9.101  ;        ;        ; 9.101  ;
; UDSn         ; RAM_DATA[0]   ; 9.849  ; 9.882  ; 9.882  ; 9.849  ;
; UDSn         ; RAM_DATA[1]   ; 10.427 ; 10.437 ; 10.437 ; 10.427 ;
; UDSn         ; RAM_DATA[2]   ; 10.580 ; 10.132 ; 10.132 ; 10.580 ;
; UDSn         ; RAM_DATA[3]   ; 10.314 ; 10.314 ; 10.314 ; 10.314 ;
; UDSn         ; RAM_DATA[4]   ; 10.850 ; 10.850 ; 10.850 ; 10.850 ;
; UDSn         ; RAM_DATA[5]   ; 10.539 ; 10.539 ; 10.539 ; 10.539 ;
; UDSn         ; RAM_DATA[6]   ; 10.397 ; 10.397 ; 10.397 ; 10.397 ;
; UDSn         ; RAM_DATA[7]   ; 10.508 ; 10.508 ; 10.508 ; 10.508 ;
; UDSn         ; RAM_DATA[8]   ; 9.781  ; 9.781  ; 9.781  ; 9.781  ;
; UDSn         ; RAM_DATA[9]   ; 9.745  ; 9.745  ; 9.745  ; 9.745  ;
; UDSn         ; RAM_DATA[10]  ; 10.527 ; 10.527 ; 10.527 ; 10.527 ;
; UDSn         ; RAM_DATA[11]  ; 10.106 ; 10.106 ; 10.106 ; 10.106 ;
; UDSn         ; RAM_DATA[12]  ; 10.459 ; 10.459 ; 10.459 ; 10.459 ;
; UDSn         ; RAM_DATA[13]  ; 9.743  ; 9.743  ; 9.743  ; 9.743  ;
; UDSn         ; RAM_DATA[14]  ; 9.164  ; 9.164  ; 9.164  ; 9.164  ;
; UDSn         ; RAM_DATA[15]  ; 9.175  ; 9.175  ; 9.175  ; 9.175  ;
; UDSn         ; RAM_DQM0H     ; 8.718  ; 11.116 ; 11.116 ; 8.718  ;
; UDSn         ; RAM_DQM0L     ; 8.181  ; 8.117  ; 8.117  ; 8.181  ;
; UDSn         ; RAM_DQM1H     ; 8.874  ; 11.272 ; 11.272 ; 8.874  ;
; UDSn         ; RAM_DQM1L     ; 8.171  ; 8.107  ; 8.107  ; 8.171  ;
; UDSn         ; RWn           ; 10.521 ; 10.521 ; 10.521 ; 10.521 ;
; UDSn         ; UDSn          ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                     ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise   ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 5.850  ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 5.057  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.417  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.417  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.403  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.403  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.412  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.402  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 5.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 5.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 5.267  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 5.267  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 5.077  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 5.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 5.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 5.490  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 5.494  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 5.392  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 5.057  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.352  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.352  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.376  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.387  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.397  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.376  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 14.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 13.307 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 13.497 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 13.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 13.331 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 13.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 13.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 13.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 13.307 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 13.307 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 5.578  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 15.493 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 15.699 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 15.699 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 15.679 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 15.679 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 15.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 15.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 15.503 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 15.493 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 15.512 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 15.512 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 15.537 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 15.537 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 15.542 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 15.542 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 15.670 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 15.660 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 2.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 15.750 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 14.442 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 14.634 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 14.442 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 14.442 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 14.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.855  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.393  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.293  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.293  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.288  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.288  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 2.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 2.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.855  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.390  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.390  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.158  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.158  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.628  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.491  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.491  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.282  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.282  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 14.916 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.668  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.805  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 2.176  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 4.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 4.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 4.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 4.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 4.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 4.831  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 4.831  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.840  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.840  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 2.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 4.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 2.176  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 2.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.272  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 14.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.071  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 2.938  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.298  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.298  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.284  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.284  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.293  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.283  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.410  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.410  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.148  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.148  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 2.958  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 2.948  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.381  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.375  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 2.938  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.233  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.233  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.257  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.268  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.278  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.257  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 9.928  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.559  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.749  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.583  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.590  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.590  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.559  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.559  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 10.745 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 10.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 10.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 10.931 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 10.931 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 10.755 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 10.745 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 10.764 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 10.764 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 10.789 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 10.789 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 10.794 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 10.794 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 10.922 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 10.912 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 11.062 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 10.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 10.209 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 10.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 10.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 10.395 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 10.491 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 10.395 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 5.057  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.417  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.417  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.403  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.403  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.412  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.402  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 5.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 5.529  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 5.267  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 5.267  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 5.077  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 5.067  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 5.500  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 5.490  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 5.494  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 5.392  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 5.057  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.352  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.352  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.376  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.387  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.397  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.376  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 14.353 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 13.307 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 13.497 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 13.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 13.331 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 13.489 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 13.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 13.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 13.307 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 13.307 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.578  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 15.493 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 15.699 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 15.699 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 15.679 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 15.679 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 15.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 15.593 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 15.503 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 15.493 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 15.512 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 15.512 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 15.537 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 15.537 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 15.542 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 15.542 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 15.670 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 15.660 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 2.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.750 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 14.442 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 14.634 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 14.442 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 14.442 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 14.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.855  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.393  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.293  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.293  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.288  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.288  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 2.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 2.975  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.855  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.165  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.390  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.390  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.744  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.158  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.958  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.158  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.638  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.628  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.491  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.491  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.282  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.282  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 14.916 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.668  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.805  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 2.176  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 4.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 4.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 4.707  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 4.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 4.812  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 4.831  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 4.831  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.840  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.840  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 2.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 4.717  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.765  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 2.176  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 2.186  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.272  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 14.820 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.071  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 2.938  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.298  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.298  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.284  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.284  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.293  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.283  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.410  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.410  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.148  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.148  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 2.958  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 2.948  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.381  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.371  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.375  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.273  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 2.938  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.233  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.233  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.257  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.268  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.278  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.257  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 9.928  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.559  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.749  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.583  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.741  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.590  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.590  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.559  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.559  ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 10.745 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 10.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 10.951 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 10.931 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 10.931 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 10.845 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 10.755 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 10.745 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 10.764 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 10.764 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 10.789 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 10.789 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 10.794 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 10.794 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 10.922 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 10.912 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.062 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 10.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 10.209 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 10.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 10.017 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 10.395 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 10.491 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 10.395 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 10.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 9.482  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 9.474  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 9.316  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 9.474  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 9.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 9.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 5.360  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 11.478 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 11.684 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 11.684 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 11.664 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 11.664 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 11.578 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 11.578 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 11.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 11.478 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 11.497 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 11.497 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 11.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 11.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 11.527 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 11.527 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 11.655 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 11.645 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 11.824 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 10.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 10.619 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 10.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 10.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 2.789  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 10.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.881  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 3.881  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.106  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.106  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.460  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.460  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.674  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.344  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 3.998  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 3.998  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 10.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 10.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 3.293  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 10.338 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.482  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.474  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.316  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.474  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.323  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.292  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.360  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 11.478 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 11.684 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 11.684 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 11.664 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 11.664 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 11.578 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 11.578 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 11.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 11.478 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 11.497 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 11.497 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 11.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 11.522 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 11.527 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 11.527 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 11.655 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 11.645 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.824 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 10.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 10.619 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 10.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 10.427 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 2.789  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 10.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.881  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 3.881  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.106  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.106  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.460  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.460  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.674  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.874  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.354  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.344  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.207  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 3.998  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 3.998  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 10.901 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 10.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.293  ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+--------+------+------------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; Rise  ; Fall ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 5.850 ;      ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 2.938 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.298 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.298 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.284 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.284 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.283 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.410 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.410 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.148 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.148 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 2.958 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 2.948 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.381 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.371 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.375 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.273 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 2.938 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.233 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.233 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.257 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.268 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.257 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.032 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 3.420 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.610 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.602 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 3.444 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.602 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.451 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.451 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.420 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.420 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 3.396 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 5.506 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 5.712 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 5.712 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 5.692 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 5.692 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 5.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 5.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 5.516 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 5.506 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 5.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 5.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 5.555 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 5.555 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 5.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 5.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 2.433 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.819 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.680 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.855 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.393 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.288 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.288 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 2.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 2.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.855 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 3.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.944 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.744 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.944 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.424 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.424 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.424 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.414 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.277 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.277 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.068 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.068 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.962 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 2.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.329 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.329 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.329 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.434 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.434 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.453 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.453 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 2.186 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 3.339 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.765 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 2.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 2.186 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.272 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 2.996 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 2.938 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.298 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.298 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.284 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.284 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.293 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.283 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.410 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.410 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.148 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.148 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 2.958 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 2.948 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.381 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.371 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.375 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 2.938 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.233 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.233 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.257 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.268 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.278 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.257 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 6.583 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 5.339 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 5.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 5.521 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 5.363 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 5.521 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 5.370 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 5.370 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 5.339 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 5.339 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 6.878 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 6.878 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 6.858 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 6.858 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 6.772 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 6.772 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 6.682 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 6.691 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 6.691 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 6.716 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 6.716 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 6.721 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 6.721 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 6.849 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 6.839 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.966 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 6.864 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 7.050 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 7.146 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 7.050 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 2.938 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.298 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.298 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.284 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.284 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.283 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.410 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.410 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.148 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.148 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 2.958 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 2.948 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.381 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.371 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.375 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.273 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 2.938 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.233 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.233 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.257 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.268 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.278 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.257 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.032 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.420 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.610 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.602 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.444 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.602 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.451 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.451 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.420 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.420 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 3.396 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 5.506 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 5.712 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 5.712 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 5.692 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 5.692 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 5.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 5.606 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 5.516 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 5.506 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 5.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 5.525 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 5.550 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 5.555 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 5.555 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 5.683 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 5.673 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 2.433 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.819 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.680 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.488 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.855 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.393 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.288 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.288 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 2.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 2.975 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.855 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 3.951 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.530 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.944 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.744 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.944 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.424 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.424 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.424 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.414 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.277 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.277 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.068 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.068 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.962 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.668 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.805 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 2.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.329 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.329 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.329 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.434 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.434 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.453 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.453 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.462 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 2.186 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.339 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.765 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 2.176 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 2.186 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.272 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.866 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 2.996 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 2.938 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.298 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.298 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.284 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.284 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.293 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.283 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.410 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.410 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.148 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.148 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 2.958 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 2.948 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.381 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.371 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.375 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.273 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 2.938 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.233 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.233 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.257 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.268 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.278 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.257 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 6.583 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 5.339 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 5.529 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 5.521 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 5.363 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 5.521 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 5.370 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 5.370 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 5.339 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 5.339 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 6.878 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 6.878 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 6.858 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 6.858 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 6.772 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 6.772 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 6.682 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 6.691 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 6.691 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 6.716 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 6.716 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 6.721 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 6.721 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 6.849 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 6.839 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.966 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 6.864 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 6.672 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 7.050 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 7.146 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 7.050 ;      ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 6.301 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 5.058 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 5.248 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 5.240 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 5.082 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 5.240 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 5.089 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 5.089 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 5.058 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 5.058 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.330 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 7.090 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 7.296 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 7.296 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 7.276 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 7.276 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 7.190 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 7.190 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 7.100 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 7.090 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 7.109 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 7.109 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 7.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 7.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 7.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 7.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 7.267 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 7.257 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 4.520 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 6.390 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 6.582 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 6.390 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 6.390 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 2.789 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 6.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.406 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 3.406 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 3.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 3.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.399 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.199 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.399 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 3.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 3.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 3.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 3.869 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 3.732 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 3.732 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 6.864 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 6.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 6.301 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 5.058 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 5.248 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 5.240 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 5.082 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 5.240 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 5.089 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 5.089 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 5.058 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 5.058 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.330 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 7.090 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 7.296 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 7.296 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 7.276 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 7.276 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 7.190 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 7.190 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 7.100 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 7.090 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 7.109 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 7.109 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 7.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 7.134 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 7.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 7.139 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 7.267 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 7.257 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.520 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 6.390 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 6.582 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 6.390 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 6.390 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 2.789 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 6.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.406 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 3.406 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 3.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 3.631 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 3.985 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.399 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.199 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.399 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 3.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 3.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 3.879 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 3.869 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 3.732 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 3.732 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 3.523 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 6.864 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 6.768 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.293 ;      ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+-------+------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 5.850     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 5.057     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 5.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 5.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 5.403     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 5.403     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 5.412     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 5.402     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 5.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 5.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 5.267     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 5.267     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 5.077     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 5.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 5.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 5.490     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 5.494     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 5.392     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 5.057     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 5.352     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 5.352     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 5.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 5.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 5.397     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 5.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 14.353    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 13.307    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 13.497    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 13.489    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 13.331    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 13.489    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 13.338    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 13.338    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 13.307    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 13.307    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 5.578     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 15.493    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 15.699    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 15.699    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 15.679    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 15.679    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 15.593    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 15.593    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 15.503    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 15.493    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 15.512    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 15.512    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 15.537    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 15.537    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 15.542    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 15.542    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 15.670    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 15.660    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 2.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 15.750    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 14.442    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 14.634    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 14.442    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 14.442    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 14.820    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.393     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 5.158     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 5.158     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.491     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.491     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.282     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.282     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 14.916    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.805     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 4.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 4.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 4.831     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 4.831     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 4.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 4.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 4.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.272     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 14.820    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 3.071     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.293     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.283     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 2.958     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 2.948     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.381     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.375     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.268     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.278     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 9.928     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 8.559     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 8.749     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 8.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 8.583     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 8.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 8.590     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 8.590     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 8.559     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 8.559     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 10.745    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 10.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 10.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 10.931    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 10.931    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 10.755    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 10.745    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 10.764    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 10.764    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 10.789    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 10.789    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 10.794    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 10.794    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 10.922    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 10.912    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 11.062    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 10.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 10.209    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 10.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 10.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 10.395    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 10.491    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 10.395    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 5.057     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 5.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 5.417     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 5.403     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 5.403     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 5.412     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 5.402     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 5.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 5.529     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 5.267     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 5.267     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 5.077     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 5.067     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 5.500     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 5.490     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 5.494     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 5.392     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 5.057     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 5.352     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 5.352     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 5.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 5.387     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 5.397     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 5.376     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 14.353    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 13.307    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 13.497    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 13.489    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 13.331    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 13.489    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 13.338    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 13.338    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 13.307    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 13.307    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.578     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 15.493    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 15.699    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 15.699    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 15.679    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 15.679    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 15.593    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 15.593    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 15.503    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 15.493    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 15.512    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 15.512    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 15.537    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 15.537    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 15.542    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 15.542    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 15.670    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 15.660    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 2.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 15.750    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 14.442    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 14.634    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 14.442    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 14.442    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 14.820    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.393     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 4.165     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 5.158     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 5.158     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.638     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.628     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.491     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.491     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.282     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.282     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 14.916    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.805     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 4.707     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 4.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 4.812     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 4.831     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 4.831     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 4.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 4.840     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 4.717     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.272     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 14.820    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 3.071     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.293     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.283     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 2.958     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 2.948     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.381     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.375     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.268     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.278     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 9.928     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 8.559     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 8.749     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 8.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 8.583     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 8.741     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 8.590     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 8.590     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 8.559     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 8.559     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 10.745    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 10.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 10.951    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 10.931    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 10.931    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 10.845    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 10.755    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 10.745    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 10.764    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 10.764    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 10.789    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 10.789    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 10.794    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 10.794    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 10.922    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 10.912    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.062    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 10.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 10.209    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 10.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 10.017    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 10.395    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 10.491    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 10.395    ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 10.338    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 9.482     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 9.474     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 9.316     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 9.474     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 9.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 9.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 5.360     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 11.478    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 11.684    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 11.684    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 11.664    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 11.664    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 11.578    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 11.578    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 11.488    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 11.478    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 11.497    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 11.497    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 11.522    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 11.522    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 11.527    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 11.527    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 11.655    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 11.645    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 11.824    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 10.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 10.619    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 10.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 10.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 2.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 10.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.881     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 3.881     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.106     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.106     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.460     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.460     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.674     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.344     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 3.998     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 3.998     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 10.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 10.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 10.338    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 9.482     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 9.474     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 9.316     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 9.474     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 9.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 9.323     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 9.292     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 5.360     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 11.478    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 11.684    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 11.684    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 11.664    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 11.664    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 11.578    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 11.578    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 11.488    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 11.478    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 11.497    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 11.497    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 11.522    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 11.522    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 11.527    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 11.527    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 11.655    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 11.645    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 11.824    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 10.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 10.619    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 10.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 10.427    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 2.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 10.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.881     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 3.881     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.106     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.106     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.460     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.460     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.674     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.874     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.354     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.344     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.207     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 3.998     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 3.998     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 10.901    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 10.805    ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                    ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; Data Port     ; Clock Port    ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                            ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+
; COM_TxD       ; CLK_PLL1      ; 5.850     ;           ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]        ; CLK_PLL1      ; 2.938     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.298     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.298     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.284     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.284     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.283     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.410     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.410     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.148     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.148     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 2.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 2.948     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.381     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.371     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.375     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.273     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 2.938     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.233     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.233     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.268     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 3.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 3.420     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 3.610     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 3.602     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 3.444     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 3.602     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 3.451     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 3.451     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 3.420     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 3.420     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD       ; CLK_PLL1      ; 3.396     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 5.506     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 5.712     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 5.712     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 5.692     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 5.692     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 5.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 5.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 5.516     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 5.506     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 5.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 5.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 5.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 5.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 5.683     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 5.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D      ; CLK_PLL1      ; 2.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.819     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 3.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 3.680     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 3.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 3.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]      ; CLK_PLL1      ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]     ; CLK_PLL1      ; 3.393     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]     ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]     ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]     ; CLK_PLL1      ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]     ; CLK_PLL1      ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]     ; CLK_PLL1      ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]     ; CLK_PLL1      ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]     ; CLK_PLL1      ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.951     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 3.951     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 4.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 4.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 4.530     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 4.530     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.944     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.944     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 4.424     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 4.424     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 4.424     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 4.414     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 4.277     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 4.277     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 4.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 4.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 3.962     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn     ; CLK_PLL1      ; 2.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn     ; CLK_PLL1      ; 3.805     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn     ; CLK_PLL1      ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]     ; CLK_PLL1      ; 3.329     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]    ; CLK_PLL1      ; 3.329     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]    ; CLK_PLL1      ; 3.329     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]    ; CLK_PLL1      ; 3.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]    ; CLK_PLL1      ; 3.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]    ; CLK_PLL1      ; 3.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]    ; CLK_PLL1      ; 3.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]    ; CLK_PLL1      ; 3.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]    ; CLK_PLL1      ; 3.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn      ; CLK_PLL1      ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP       ; CLK_PLL1      ; 3.339     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn      ; CLK_PLL1      ; 2.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn     ; CLK_PLL1      ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn     ; CLK_PLL1      ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn     ; CLK_PLL1      ; 2.272     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn          ; CLK_PLL1      ; 2.996     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CLK_PLL1      ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]       ; CLK_PLL1      ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]       ; CLK_PLL1      ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]       ; CLK_PLL1      ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]       ; CLK_PLL1      ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]       ; CLK_PLL1      ; 3.293     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]       ; CLK_PLL1      ; 3.283     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]       ; CLK_PLL1      ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]       ; CLK_PLL1      ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]       ; CLK_PLL1      ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]      ; CLK_PLL1      ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]      ; CLK_PLL1      ; 2.958     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]      ; CLK_PLL1      ; 2.948     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]      ; CLK_PLL1      ; 3.381     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]      ; CLK_PLL1      ; 3.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]      ; CLK_PLL1      ; 3.375     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]      ; CLK_PLL1      ; 3.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]      ; CLK_PLL1      ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]      ; CLK_PLL1      ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]      ; CLK_PLL1      ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]      ; CLK_PLL1      ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]      ; CLK_PLL1      ; 3.268     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]      ; CLK_PLL1      ; 3.278     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]      ; CLK_PLL1      ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn           ; CLK_PLL1      ; 6.583     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]         ; CLK_PLL1      ; 5.339     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]        ; CLK_PLL1      ; 5.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]        ; CLK_PLL1      ; 5.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]        ; CLK_PLL1      ; 5.363     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]        ; CLK_PLL1      ; 5.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]        ; CLK_PLL1      ; 5.370     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]        ; CLK_PLL1      ; 5.370     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]        ; CLK_PLL1      ; 5.339     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]        ; CLK_PLL1      ; 5.339     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]       ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]      ; CLK_PLL1      ; 6.878     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]      ; CLK_PLL1      ; 6.878     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]      ; CLK_PLL1      ; 6.858     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]      ; CLK_PLL1      ; 6.858     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]      ; CLK_PLL1      ; 6.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]      ; CLK_PLL1      ; 6.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]      ; CLK_PLL1      ; 6.682     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]      ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]      ; CLK_PLL1      ; 6.691     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]      ; CLK_PLL1      ; 6.691     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]     ; CLK_PLL1      ; 6.716     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]     ; CLK_PLL1      ; 6.716     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]     ; CLK_PLL1      ; 6.721     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]     ; CLK_PLL1      ; 6.721     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]     ; CLK_PLL1      ; 6.849     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]     ; CLK_PLL1      ; 6.839     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn        ; CLK_PLL1      ; 4.966     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]         ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]        ; CLK_PLL1      ; 6.864     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]        ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]        ; CLK_PLL1      ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn          ; CLK_PLL1      ; 7.050     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn           ; CLK_PLL1      ; 7.146     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn          ; CLK_PLL1      ; 7.050     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 2.938     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.298     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.298     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.284     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.284     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.283     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.410     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.410     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.148     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.148     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 2.958     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 2.948     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.381     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.371     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.375     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.273     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 2.938     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.233     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.233     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.268     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.278     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 3.032     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 3.420     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 3.610     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 3.602     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 3.444     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 3.602     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 3.451     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 3.451     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 3.420     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 3.420     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 3.396     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 5.506     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 5.712     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 5.712     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 5.692     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 5.692     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 5.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 5.606     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 5.516     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 5.506     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 5.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 5.525     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 5.550     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 5.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 5.555     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 5.683     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 5.673     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D      ; CRT_PIN4_CLK1 ; 2.433     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.819     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 3.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 3.680     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 3.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 3.488     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]      ; CRT_PIN4_CLK1 ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]     ; CRT_PIN4_CLK1 ; 3.393     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]     ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]     ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]     ; CRT_PIN4_CLK1 ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]     ; CRT_PIN4_CLK1 ; 3.288     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]     ; CRT_PIN4_CLK1 ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]     ; CRT_PIN4_CLK1 ; 2.975     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]     ; CRT_PIN4_CLK1 ; 2.855     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.951     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 3.951     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 4.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 4.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 4.530     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 4.530     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.944     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.744     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.944     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 4.424     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 4.424     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 4.424     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 4.414     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 4.277     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 4.277     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 4.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 4.068     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 3.962     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn     ; CRT_PIN4_CLK1 ; 2.668     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn     ; CRT_PIN4_CLK1 ; 3.805     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn     ; CRT_PIN4_CLK1 ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]     ; CRT_PIN4_CLK1 ; 3.329     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]    ; CRT_PIN4_CLK1 ; 3.329     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]    ; CRT_PIN4_CLK1 ; 3.329     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]    ; CRT_PIN4_CLK1 ; 3.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]    ; CRT_PIN4_CLK1 ; 3.434     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]    ; CRT_PIN4_CLK1 ; 3.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]    ; CRT_PIN4_CLK1 ; 3.453     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]    ; CRT_PIN4_CLK1 ; 3.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]    ; CRT_PIN4_CLK1 ; 3.462     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn      ; CRT_PIN4_CLK1 ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP       ; CRT_PIN4_CLK1 ; 3.339     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn      ; CRT_PIN4_CLK1 ; 2.765     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn     ; CRT_PIN4_CLK1 ; 2.176     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn     ; CRT_PIN4_CLK1 ; 2.186     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn     ; CRT_PIN4_CLK1 ; 2.272     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 3.866     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn          ; CRT_PIN4_CLK1 ; 2.996     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]        ; CRT_PIN4_CLK1 ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]       ; CRT_PIN4_CLK1 ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]       ; CRT_PIN4_CLK1 ; 3.298     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]       ; CRT_PIN4_CLK1 ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]       ; CRT_PIN4_CLK1 ; 3.284     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]       ; CRT_PIN4_CLK1 ; 3.293     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]       ; CRT_PIN4_CLK1 ; 3.283     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]       ; CRT_PIN4_CLK1 ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]       ; CRT_PIN4_CLK1 ; 3.410     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]       ; CRT_PIN4_CLK1 ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]      ; CRT_PIN4_CLK1 ; 3.148     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]      ; CRT_PIN4_CLK1 ; 2.958     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]      ; CRT_PIN4_CLK1 ; 2.948     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]      ; CRT_PIN4_CLK1 ; 3.381     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]      ; CRT_PIN4_CLK1 ; 3.371     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]      ; CRT_PIN4_CLK1 ; 3.375     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]      ; CRT_PIN4_CLK1 ; 3.273     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]      ; CRT_PIN4_CLK1 ; 2.938     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]      ; CRT_PIN4_CLK1 ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]      ; CRT_PIN4_CLK1 ; 3.233     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]      ; CRT_PIN4_CLK1 ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]      ; CRT_PIN4_CLK1 ; 3.268     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]      ; CRT_PIN4_CLK1 ; 3.278     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]      ; CRT_PIN4_CLK1 ; 3.257     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CRT_PIN4_CLK1 ; 6.583     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 5.339     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 5.529     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 5.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 5.363     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 5.521     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 5.370     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 5.370     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 5.339     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 5.339     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 6.878     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 6.878     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 6.858     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 6.858     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 6.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 6.772     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 6.682     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 6.691     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 6.691     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 6.716     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 6.716     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 6.721     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 6.721     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 6.849     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 6.839     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.966     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 6.864     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 6.672     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 7.050     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 7.146     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 7.050     ;           ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn           ; CLK_PLL1      ; 6.301     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]         ; CLK_PLL1      ; 5.058     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]        ; CLK_PLL1      ; 5.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]        ; CLK_PLL1      ; 5.240     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]        ; CLK_PLL1      ; 5.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]        ; CLK_PLL1      ; 5.240     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]        ; CLK_PLL1      ; 5.089     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]        ; CLK_PLL1      ; 5.089     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]        ; CLK_PLL1      ; 5.058     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]        ; CLK_PLL1      ; 5.058     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_TxD       ; CLK_PLL1      ; 4.330     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]       ; CLK_PLL1      ; 7.090     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]      ; CLK_PLL1      ; 7.296     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]      ; CLK_PLL1      ; 7.296     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]      ; CLK_PLL1      ; 7.276     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]      ; CLK_PLL1      ; 7.276     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]      ; CLK_PLL1      ; 7.190     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]      ; CLK_PLL1      ; 7.190     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]      ; CLK_PLL1      ; 7.100     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]      ; CLK_PLL1      ; 7.090     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]      ; CLK_PLL1      ; 7.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]      ; CLK_PLL1      ; 7.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]     ; CLK_PLL1      ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]     ; CLK_PLL1      ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]     ; CLK_PLL1      ; 7.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]     ; CLK_PLL1      ; 7.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]     ; CLK_PLL1      ; 7.267     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]     ; CLK_PLL1      ; 7.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DTACKn        ; CLK_PLL1      ; 4.520     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]         ; CLK_PLL1      ; 6.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]        ; CLK_PLL1      ; 6.582     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]        ; CLK_PLL1      ; 6.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]        ; CLK_PLL1      ; 6.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC         ; CLK_PLL1      ; 2.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn          ; CLK_PLL1      ; 6.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]   ; CLK_PLL1      ; 3.406     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]  ; CLK_PLL1      ; 3.406     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]  ; CLK_PLL1      ; 3.631     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]  ; CLK_PLL1      ; 3.631     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]  ; CLK_PLL1      ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]  ; CLK_PLL1      ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]  ; CLK_PLL1      ; 4.399     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]  ; CLK_PLL1      ; 4.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]  ; CLK_PLL1      ; 4.399     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]  ; CLK_PLL1      ; 3.879     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]  ; CLK_PLL1      ; 3.879     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10] ; CLK_PLL1      ; 3.879     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11] ; CLK_PLL1      ; 3.869     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12] ; CLK_PLL1      ; 3.732     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13] ; CLK_PLL1      ; 3.732     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14] ; CLK_PLL1      ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15] ; CLK_PLL1      ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn           ; CLK_PLL1      ; 6.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn          ; CLK_PLL1      ; 6.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC         ; CLK_PLL1      ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn           ; CRT_PIN4_CLK1 ; 6.301     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]         ; CRT_PIN4_CLK1 ; 5.058     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]        ; CRT_PIN4_CLK1 ; 5.248     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]        ; CRT_PIN4_CLK1 ; 5.240     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]        ; CRT_PIN4_CLK1 ; 5.082     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]        ; CRT_PIN4_CLK1 ; 5.240     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]        ; CRT_PIN4_CLK1 ; 5.089     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]        ; CRT_PIN4_CLK1 ; 5.089     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]        ; CRT_PIN4_CLK1 ; 5.058     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]        ; CRT_PIN4_CLK1 ; 5.058     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_TxD       ; CRT_PIN4_CLK1 ; 4.330     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]       ; CRT_PIN4_CLK1 ; 7.090     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]      ; CRT_PIN4_CLK1 ; 7.296     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]      ; CRT_PIN4_CLK1 ; 7.296     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]      ; CRT_PIN4_CLK1 ; 7.276     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]      ; CRT_PIN4_CLK1 ; 7.276     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]      ; CRT_PIN4_CLK1 ; 7.190     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]      ; CRT_PIN4_CLK1 ; 7.190     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]      ; CRT_PIN4_CLK1 ; 7.100     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]      ; CRT_PIN4_CLK1 ; 7.090     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]      ; CRT_PIN4_CLK1 ; 7.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]      ; CRT_PIN4_CLK1 ; 7.109     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]     ; CRT_PIN4_CLK1 ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]     ; CRT_PIN4_CLK1 ; 7.134     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]     ; CRT_PIN4_CLK1 ; 7.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]     ; CRT_PIN4_CLK1 ; 7.139     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]     ; CRT_PIN4_CLK1 ; 7.267     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]     ; CRT_PIN4_CLK1 ; 7.257     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DTACKn        ; CRT_PIN4_CLK1 ; 4.520     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]         ; CRT_PIN4_CLK1 ; 6.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]        ; CRT_PIN4_CLK1 ; 6.582     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]        ; CRT_PIN4_CLK1 ; 6.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]        ; CRT_PIN4_CLK1 ; 6.390     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC         ; CRT_PIN4_CLK1 ; 2.789     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn          ; CRT_PIN4_CLK1 ; 6.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]   ; CRT_PIN4_CLK1 ; 3.406     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]  ; CRT_PIN4_CLK1 ; 3.406     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]  ; CRT_PIN4_CLK1 ; 3.631     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]  ; CRT_PIN4_CLK1 ; 3.631     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]  ; CRT_PIN4_CLK1 ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]  ; CRT_PIN4_CLK1 ; 3.985     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]  ; CRT_PIN4_CLK1 ; 4.399     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]  ; CRT_PIN4_CLK1 ; 4.199     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]  ; CRT_PIN4_CLK1 ; 4.399     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]  ; CRT_PIN4_CLK1 ; 3.879     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]  ; CRT_PIN4_CLK1 ; 3.879     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10] ; CRT_PIN4_CLK1 ; 3.879     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11] ; CRT_PIN4_CLK1 ; 3.869     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12] ; CRT_PIN4_CLK1 ; 3.732     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13] ; CRT_PIN4_CLK1 ; 3.732     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14] ; CRT_PIN4_CLK1 ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15] ; CRT_PIN4_CLK1 ; 3.523     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn           ; CRT_PIN4_CLK1 ; 6.864     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn          ; CRT_PIN4_CLK1 ; 6.768     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC         ; CRT_PIN4_CLK1 ; 3.293     ;           ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+---------------+---------------+-----------+-----------+------------+------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                             ;
+-------------------------------------------------------------+------------+-----------+----------+---------+---------------------+
; Clock                                                       ; Setup      ; Hold      ; Recovery ; Removal ; Minimum Pulse Width ;
+-------------------------------------------------------------+------------+-----------+----------+---------+---------------------+
; Worst-case Slack                                            ; -12.133    ; -3.460    ; 21.924   ; 0.983   ; 10.131              ;
;  CLK_PLL1                                                   ; 59.898     ; 0.358     ; N/A      ; N/A     ; 30.139              ;
;  CLK_PLL2                                                   ; N/A        ; N/A       ; N/A      ; N/A     ; 31.250              ;
;  CRT_PIN4_CLK1                                              ; N/A        ; N/A       ; N/A      ; N/A     ; 31.250              ;
;  altera_reserved_tck                                        ; N/A        ; N/A       ; N/A      ; N/A     ; 97.531              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -11.466    ; -2.006    ; 21.924   ; 1.252   ; 28.943              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -11.466    ; -2.006    ; 21.924   ; 1.252   ; 28.943              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -12.133    ; -3.460    ; 28.501   ; 0.983   ; 13.061              ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -12.133    ; -3.460    ; 28.501   ; 0.983   ; 13.061              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; -1.381     ; -3.079    ; N/A      ; N/A     ; 18.420              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; -3.911     ; 0.215     ; N/A      ; N/A     ; 10.131              ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 61.245     ; 0.215     ; N/A      ; N/A     ; 30.139              ;
; Design-wide TNS                                             ; -42096.723 ; -2232.409 ; 0.0      ; 0.0     ; 0.0                 ;
;  CLK_PLL1                                                   ; 0.000      ; 0.000     ; N/A      ; N/A     ; 0.000               ;
;  CLK_PLL2                                                   ; N/A        ; N/A       ; N/A      ; N/A     ; 0.000               ;
;  CRT_PIN4_CLK1                                              ; N/A        ; N/A       ; N/A      ; N/A     ; 0.000               ;
;  altera_reserved_tck                                        ; N/A        ; N/A       ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; -12013.941 ; -141.124  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; -12013.941 ; -141.124  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; -8599.655  ; -746.183  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; -8599.655  ; -746.183  ; 0.000    ; 0.000   ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; -500.405   ; -514.643  ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; -369.126   ; 0.000     ; N/A      ; N/A     ; 0.000               ;
;  cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 0.000      ; 0.000     ; N/A      ; N/A     ; 0.000               ;
+-------------------------------------------------------------+------------+-----------+----------+---------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; -0.590 ; -0.590 ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]         ; CLK_PLL1      ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 26.366 ; 26.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 25.876 ; 25.876 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 26.482 ; 26.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 26.949 ; 26.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 34.201 ; 34.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.309  ; 7.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 10.936 ; 10.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 17.375 ; 17.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 17.045 ; 17.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 17.228 ; 17.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 17.926 ; 17.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 16.819 ; 16.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 15.419 ; 15.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 18.105 ; 18.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.883 ; 19.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 22.861 ; 22.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; 15.990 ; 15.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.932 ; 19.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 19.478 ; 19.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 16.041 ; 16.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 16.251 ; 16.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.542 ; 15.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 13.063 ; 13.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 12.805 ; 12.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 13.670 ; 13.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 12.348 ; 12.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.837 ; 15.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 15.891 ; 15.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.805 ; 14.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 15.141 ; 15.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.877 ; 11.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 12.055 ; 12.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 6.886  ; 6.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 18.779 ; 18.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 35.084 ; 35.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 35.026 ; 35.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; 11.760 ; 11.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; 13.358 ; 13.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; 10.435 ; 10.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 9.737  ; 9.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 19.843 ; 19.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; 7.689  ; 7.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.049 ; 20.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 33.005 ; 33.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 17.665 ; 17.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.703 ; 16.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 16.591 ; 16.591 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 16.399 ; 16.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.209 ; 17.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.257 ; 18.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.177 ; 19.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; 5.964  ; 5.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 20.638 ; 20.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.268 ; 19.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 18.199 ; 18.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.445 ; 18.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.888 ; 17.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.288 ; 18.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.836 ; 18.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 17.956 ; 17.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.205 ; 17.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.962 ; 18.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.867 ; 20.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.250 ; 18.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.689 ; 20.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.054 ; 21.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; 3.336  ; 3.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 6.818  ; 6.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 35.013 ; 35.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 10.398 ; 10.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 8.825  ; 8.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 10.824 ; 10.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 9.784  ; 9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 10.267 ; 10.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 10.246 ; 10.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 10.148 ; 10.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 10.072 ; 10.072 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 10.901 ; 10.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 11.298 ; 11.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 10.547 ; 10.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 9.261  ; 9.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; 14.901 ; 14.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; 8.317  ; 8.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; 14.117 ; 14.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 22.095 ; 22.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; 8.694  ; 8.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; 9.579  ; 9.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; 9.424  ; 9.424  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; 8.732  ; 8.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; 6.890  ; 6.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; 7.403  ; 7.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 34.823 ; 34.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; 11.984 ; 11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 26.088 ; 26.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 25.598 ; 25.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 26.204 ; 26.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 26.671 ; 26.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 33.438 ; 33.438 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; 7.308  ; 7.308  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; 7.791  ; 7.791  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; 7.328  ; 7.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 16.612 ; 16.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 16.596 ; 16.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 16.601 ; 16.601 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 17.648 ; 17.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 15.986 ; 15.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 14.625 ; 14.625 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 17.602 ; 17.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; 19.434 ; 19.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; 22.177 ; 22.177 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; 19.116 ; 19.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.794 ; 18.794 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 15.278 ; 15.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 15.396 ; 15.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 15.264 ; 15.264 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 12.230 ; 12.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 12.011 ; 12.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 12.737 ; 12.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 11.962 ; 11.962 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 15.225 ; 15.225 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 16.167 ; 16.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 14.117 ; 14.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 14.657 ; 14.657 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 15.934 ; 15.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 11.193 ; 11.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 11.239 ; 11.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 17.725 ; 17.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 34.600 ; 34.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 34.542 ; 34.542 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; 6.253  ; 6.253  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 7.394  ; 7.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; 19.698 ; 19.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; 19.904 ; 19.904 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 32.242 ; 32.242 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; 17.053 ; 17.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 16.091 ; 16.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 16.227 ; 16.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 15.772 ; 15.772 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.095 ; 17.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 17.463 ; 17.463 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 19.880 ; 19.880 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 18.361 ; 18.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 19.875 ; 19.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 18.819 ; 18.819 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 17.572 ; 17.572 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 18.167 ; 18.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 17.055 ; 17.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 17.494 ; 17.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 20.843 ; 20.843 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 15.845 ; 15.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 18.224 ; 18.224 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.232 ; 18.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 16.517 ; 16.517 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 18.478 ; 18.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.219 ; 18.219 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 20.005 ; 20.005 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 20.238 ; 20.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 34.735 ; 34.735 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; 15.683 ; 15.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 34.339 ; 34.339 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 26.366 ; 26.366 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 27.596 ; 27.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 25.876 ; 25.876 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 26.482 ; 26.482 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 26.949 ; 26.949 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 34.201 ; 34.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.309  ; 7.309  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 10.936 ; 10.936 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 17.375 ; 17.375 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 17.045 ; 17.045 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 17.228 ; 17.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 17.926 ; 17.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 16.819 ; 16.819 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.419 ; 15.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 18.535 ; 18.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.105 ; 18.105 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.883 ; 19.883 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 22.861 ; 22.861 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; 15.990 ; 15.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.932 ; 19.932 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 19.478 ; 19.478 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 37.406 ; 37.406 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.041 ; 16.041 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.251 ; 16.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.542 ; 15.542 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.063 ; 13.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.805 ; 12.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 13.670 ; 13.670 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 12.348 ; 12.348 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.837 ; 15.837 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 15.891 ; 15.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.805 ; 14.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.141 ; 15.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 18.009 ; 18.009 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.965 ; 15.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.877 ; 11.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 12.055 ; 12.055 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 6.886  ; 6.886  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 18.779 ; 18.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 35.572 ; 35.572 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 35.084 ; 35.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 35.026 ; 35.026 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; 11.760 ; 11.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; 6.158  ; 6.158  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; 13.358 ; 13.358 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; 10.435 ; 10.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 9.737  ; 9.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.843 ; 19.843 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; 7.689  ; 7.689  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.049 ; 20.049 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; 7.606  ; 7.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 33.005 ; 33.005 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.665 ; 17.665 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.703 ; 16.703 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 16.591 ; 16.591 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 16.399 ; 16.399 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.209 ; 17.209 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 21.666 ; 21.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.257 ; 18.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.177 ; 19.177 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; 5.964  ; 5.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 20.638 ; 20.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.268 ; 19.268 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 18.199 ; 18.199 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.445 ; 18.445 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.888 ; 17.888 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.288 ; 18.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 21.776 ; 21.776 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.231 ; 16.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.836 ; 18.836 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 17.956 ; 17.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.205 ; 17.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.962 ; 18.962 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.867 ; 20.867 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.250 ; 18.250 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.689 ; 20.689 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.054 ; 21.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; 3.336  ; 3.336  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 6.818  ; 6.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 35.013 ; 35.013 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 10.398 ; 10.398 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 8.825  ; 8.825  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 10.900 ; 10.900 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 10.824 ; 10.824 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 10.428 ; 10.428 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 9.784  ; 9.784  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 10.267 ; 10.267 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 10.246 ; 10.246 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 10.148 ; 10.148 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 10.072 ; 10.072 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 10.901 ; 10.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 11.298 ; 11.298 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 10.493 ; 10.493 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 10.547 ; 10.547 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 9.261  ; 9.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; 14.901 ; 14.901 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; 8.317  ; 8.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; 14.117 ; 14.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 22.095 ; 22.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; 8.694  ; 8.694  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; 9.579  ; 9.579  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; 9.817  ; 9.817  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; 9.424  ; 9.424  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; 8.732  ; 8.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; 6.890  ; 6.890  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; 7.403  ; 7.403  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.823 ; 34.823 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; 11.984 ; 11.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 26.088 ; 26.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 27.318 ; 27.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 25.598 ; 25.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 26.204 ; 26.204 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 26.671 ; 26.671 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 33.438 ; 33.438 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; 7.308  ; 7.308  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 7.791  ; 7.791  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 6.906  ; 6.906  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; 7.328  ; 7.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 16.612 ; 16.612 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 16.596 ; 16.596 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 16.601 ; 16.601 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 17.648 ; 17.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 15.986 ; 15.986 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 14.625 ; 14.625 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 17.602 ; 17.602 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 17.719 ; 17.719 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 19.434 ; 19.434 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 22.177 ; 22.177 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 19.116 ; 19.116 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.794 ; 18.794 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 36.922 ; 36.922 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 15.278 ; 15.278 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 15.802 ; 15.802 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 15.396 ; 15.396 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 15.264 ; 15.264 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 12.230 ; 12.230 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.011 ; 12.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 12.737 ; 12.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 11.962 ; 11.962 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 15.225 ; 15.225 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.167 ; 16.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 14.117 ; 14.117 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 14.657 ; 14.657 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 17.998 ; 17.998 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 15.934 ; 15.934 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.193 ; 11.193 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 11.239 ; 11.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 17.725 ; 17.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 35.088 ; 35.088 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 34.600 ; 34.600 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 34.542 ; 34.542 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; 6.253  ; 6.253  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 7.394  ; 7.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.698 ; 19.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 19.904 ; 19.904 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 32.242 ; 32.242 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 17.053 ; 17.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 16.091 ; 16.091 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 16.227 ; 16.227 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 15.772 ; 15.772 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.095 ; 17.095 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 20.833 ; 20.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 17.463 ; 17.463 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 19.880 ; 19.880 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 18.361 ; 18.361 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 19.875 ; 19.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 18.819 ; 18.819 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 17.572 ; 17.572 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 18.167 ; 18.167 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 17.055 ; 17.055 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 17.494 ; 17.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 20.843 ; 20.843 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 15.845 ; 15.845 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 18.224 ; 18.224 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.232 ; 18.232 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 16.517 ; 16.517 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 18.478 ; 18.478 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.856 ; 20.856 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.219 ; 18.219 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 20.005 ; 20.005 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 20.238 ; 20.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 34.735 ; 34.735 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 15.683 ; 15.683 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.339 ; 34.339 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CLK_PLL1      ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[1]        ; CLK_PLL1      ; 27.103 ; 27.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[2]        ; CLK_PLL1      ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[3]        ; CLK_PLL1      ; 26.613 ; 26.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[4]        ; CLK_PLL1      ; 27.219 ; 27.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[5]        ; CLK_PLL1      ; 27.686 ; 27.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 34.278 ; 34.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 17.452 ; 17.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 17.712 ; 17.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 18.059 ; 18.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 18.663 ; 18.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 17.442 ; 17.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 18.747 ; 18.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; 20.550 ; 20.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; 22.138 ; 22.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; 20.044 ; 20.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; 18.755 ; 18.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 16.118 ; 16.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 16.918 ; 16.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 16.854 ; 16.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 16.279 ; 16.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 13.686 ; 13.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 12.990 ; 12.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 16.363 ; 16.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 16.718 ; 16.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 15.535 ; 15.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 15.283 ; 15.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 11.154 ; 11.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 12.167 ; 12.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; 35.226 ; 35.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; 35.168 ; 35.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; 19.977 ; 19.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; 20.183 ; 20.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 33.082 ; 33.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; 18.191 ; 18.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; 17.229 ; 17.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; 17.258 ; 17.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; 17.230 ; 17.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; 18.391 ; 18.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; 21.279 ; 21.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; 19.289 ; 19.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Xn         ; CLK_PLL1      ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Yn         ; CLK_PLL1      ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Xn         ; CLK_PLL1      ; 4.471  ; 4.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Yn         ; CLK_PLL1      ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PENn           ; CLK_PLL1      ; 8.010  ; 8.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 20.715 ; 20.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 19.935 ; 19.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 19.030 ; 19.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 19.182 ; 19.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 18.511 ; 18.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 18.422 ; 18.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 19.362 ; 19.362 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 18.783 ; 18.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 17.935 ; 17.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 19.104 ; 19.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 20.942 ; 20.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 18.308 ; 18.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 19.966 ; 19.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 21.166 ; 21.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; 35.750 ; 35.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; 20.035 ; 20.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 34.965 ; 34.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 27.103 ; 27.103 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 28.333 ; 28.333 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 26.613 ; 26.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 27.219 ; 27.219 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 27.686 ; 27.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 34.278 ; 34.278 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 17.452 ; 17.452 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 17.712 ; 17.712 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 18.059 ; 18.059 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 18.663 ; 18.663 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 17.442 ; 17.442 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 15.553 ; 15.553 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 19.001 ; 19.001 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 18.747 ; 18.747 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; 20.550 ; 20.550 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; 22.138 ; 22.138 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; 20.044 ; 20.044 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; 18.755 ; 18.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; 37.548 ; 37.548 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 16.118 ; 16.118 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 16.918 ; 16.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 16.854 ; 16.854 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 16.279 ; 16.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 13.686 ; 13.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 12.939 ; 12.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 14.136 ; 14.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 12.990 ; 12.990 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 16.363 ; 16.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 16.718 ; 16.718 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 15.535 ; 15.535 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 15.283 ; 15.283 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 18.084 ; 18.084 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 16.023 ; 16.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 11.154 ; 11.154 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 12.167 ; 12.167 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 35.714 ; 35.714 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 35.226 ; 35.226 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 35.168 ; 35.168 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; 19.977 ; 19.977 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; 20.183 ; 20.183 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 33.082 ; 33.082 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; 18.191 ; 18.191 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 17.229 ; 17.229 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 17.258 ; 17.258 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 17.230 ; 17.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 17.946 ; 17.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 22.289 ; 22.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 18.391 ; 18.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 21.279 ; 21.279 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 19.289 ; 19.289 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; 4.671  ; 4.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; 4.932  ; 4.932  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; 4.471  ; 4.471  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; 6.710  ; 6.710  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PENn           ; CRT_PIN4_CLK1 ; 8.010  ; 8.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 20.715 ; 20.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 19.935 ; 19.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 19.030 ; 19.030 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 19.182 ; 19.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 18.511 ; 18.511 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 18.422 ; 18.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 22.242 ; 22.242 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 16.873 ; 16.873 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 19.362 ; 19.362 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 18.783 ; 18.783 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 17.935 ; 17.935 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 19.104 ; 19.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 20.942 ; 20.942 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 18.308 ; 18.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 19.966 ; 19.966 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 21.166 ; 21.166 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 35.750 ; 35.750 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; 20.035 ; 20.035 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 34.965 ; 34.965 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; RESET_COREn    ; CLK_PLL1      ; 0.841  ; 0.841  ; Rise       ; CLK_PLL1                                                   ;
; ADR[*]         ; CLK_PLL1      ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; -4.719 ; -4.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; -5.054 ; -5.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; -4.801 ; -4.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; -4.755 ; -4.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.864 ; -3.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -3.764 ; -3.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -3.540 ; -3.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -3.377 ; -3.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -3.567 ; -3.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -3.394 ; -3.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -3.391 ; -3.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -3.285 ; -3.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -4.560 ; -4.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -4.614 ; -4.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RxD        ; CLK_PLL1      ; -5.308 ; -5.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -6.978 ; -6.978 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -6.877 ; -6.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.570 ; -4.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.565 ; -4.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.621 ; -4.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.529 ; -4.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -4.365 ; -4.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -4.791 ; -4.791 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -4.379 ; -4.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.069 ; -4.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; -3.623 ; -3.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.931 ; -4.931 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -4.439 ; -4.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_IPn        ; CLK_PLL1      ; -3.309 ; -3.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_TR00n      ; CLK_PLL1      ; -1.338 ; -1.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WPn        ; CLK_PLL1      ; -3.849 ; -3.849 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_RDY      ; CLK_PLL1      ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -4.047 ; -4.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -5.086 ; -5.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDRQn          ; CLK_PLL1      ; -3.910 ; -3.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -5.203 ; -5.203 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_RxD       ; CLK_PLL1      ; -3.979 ; -3.979 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -4.345 ; -4.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -3.460 ; -3.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -5.631 ; -5.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -5.720 ; -5.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.004 ; -6.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.181 ; -7.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -5.786 ; -5.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -6.735 ; -6.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.100 ; -6.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_IN        ; CLK_PLL1      ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.989 ; -3.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.260 ; -4.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -4.151 ; -4.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.064 ; -4.064 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.180 ; -4.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -4.054 ; -4.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.119 ; -4.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.162 ; -4.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.956 ; -3.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESET_COREn    ; CLK_PLL1      ; -1.549 ; -1.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; -3.598 ; -3.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.693 ; -4.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; -3.517 ; -3.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; -3.907 ; -3.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; -3.715 ; -3.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; -3.879 ; -3.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; -3.941 ; -3.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; -4.288 ; -4.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; -4.476 ; -4.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; -4.117 ; -4.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; -3.929 ; -3.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; -3.706 ; -3.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_ENn     ; CLK_PLL1      ; -4.465 ; -4.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_ACK    ; CLK_PLL1      ; -4.121 ; -4.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESET_COREn ; CLK_PLL1      ; -4.136 ; -4.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -4.451 ; -4.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_CLK     ; CLK_PLL1      ; -4.280 ; -4.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MOSI    ; CLK_PLL1      ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_SSn[*]  ; CLK_PLL1      ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[0] ; CLK_PLL1      ; -4.141 ; -4.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[1] ; CLK_PLL1      ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SD_SPI_SSn[2] ; CLK_PLL1      ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_ACK   ; CLK_PLL1      ; -3.448 ; -3.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_CLK    ; CLK_PLL1      ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MOSI   ; CLK_PLL1      ; -3.626 ; -3.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -5.853 ; -5.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VPAn           ; CLK_PLL1      ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; -5.554 ; -5.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; -5.937 ; -5.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; -5.355 ; -5.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; -5.574 ; -5.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; -4.513 ; -4.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; AVECn          ; CLK_PLL1      ; -3.844 ; -3.844 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BERRn          ; CLK_PLL1      ; -4.112 ; -4.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; -3.660 ; -3.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BRn            ; CLK_PLL1      ; -3.821 ; -3.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; -6.366 ; -6.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; -6.370 ; -6.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; -6.381 ; -6.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; -6.936 ; -6.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; -7.138 ; -7.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; -7.151 ; -7.151 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DCD        ; CLK_PLL1      ; -7.637 ; -7.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RI         ; CLK_PLL1      ; -8.182 ; -8.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CONFIG[*]      ; CLK_PLL1      ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.537 ; -7.537 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.494 ; -7.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CONFIG[5]     ; CLK_PLL1      ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; -4.737 ; -4.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; -4.947 ; -4.947 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; -4.895 ; -4.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; -4.956 ; -4.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; -5.506 ; -5.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; -5.178 ; -5.178 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; -5.820 ; -5.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; -5.428 ; -5.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; -4.987 ; -4.987 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; -4.715 ; -4.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; -5.053 ; -5.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; -4.686 ; -4.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; -4.609 ; -4.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; -4.223 ; -4.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; -5.336 ; -5.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; -5.141 ; -5.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_RDn        ; CLK_PLL1      ; -3.301 ; -3.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; -3.876 ; -3.876 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDINTn         ; CLK_PLL1      ; -7.481 ; -7.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.598 ; -7.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; -5.641 ; -5.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_BSY        ; CLK_PLL1      ; -6.349 ; -6.349 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.110 ; -6.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.632 ; -6.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.850 ; -7.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; -6.460 ; -6.460 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.352 ; -7.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.804 ; -6.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -7.568 ; -7.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -7.452 ; -7.452 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -6.821 ; -6.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -7.173 ; -7.173 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -6.766 ; -6.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -6.875 ; -6.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -8.481 ; -8.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -7.318 ; -7.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -7.154 ; -7.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -6.833 ; -6.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -7.370 ; -7.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -8.238 ; -8.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -7.202 ; -7.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -7.832 ; -7.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -7.906 ; -7.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_RESETn      ; CLK_PLL1      ; -5.678 ; -5.678 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; -6.661 ; -6.661 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -4.719 ; -4.719 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -5.054 ; -5.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -4.801 ; -4.801 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -4.755 ; -4.755 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.386 ; -4.386 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.864 ; -3.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -3.944 ; -3.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -3.764 ; -3.764 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -3.540 ; -3.540 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -3.377 ; -3.377 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -3.567 ; -3.567 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -3.394 ; -3.394 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -3.391 ; -3.391 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -3.285 ; -3.285 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -4.560 ; -4.560 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -4.614 ; -4.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RxD        ; CRT_PIN4_CLK1 ; -5.308 ; -5.308 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -6.978 ; -6.978 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -6.877 ; -6.877 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.164 ; -6.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.570 ; -4.570 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.846 ; -4.846 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.565 ; -4.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.621 ; -4.621 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.529 ; -4.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.782 ; -4.782 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -5.046 ; -5.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.365 ; -4.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -4.791 ; -4.791 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.038 ; -4.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.379 ; -4.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.069 ; -4.069 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.050 ; -4.050 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; -3.623 ; -3.623 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.931 ; -4.931 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.317 ; -4.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.439 ; -4.439 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.392 ; -4.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_IPn        ; CRT_PIN4_CLK1 ; -3.309 ; -3.309 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_TR00n      ; CRT_PIN4_CLK1 ; -1.338 ; -1.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WPn        ; CRT_PIN4_CLK1 ; -3.849 ; -3.849 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_RDY      ; CRT_PIN4_CLK1 ; -4.551 ; -4.551 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -4.047 ; -4.047 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -5.086 ; -5.086 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDRQn          ; CRT_PIN4_CLK1 ; -3.910 ; -3.910 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -5.203 ; -5.203 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_RxD       ; CRT_PIN4_CLK1 ; -3.979 ; -3.979 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.345 ; -4.345 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -3.460 ; -3.460 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -5.631 ; -5.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -5.720 ; -5.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.385 ; -5.385 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.004 ; -6.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.181 ; -7.181 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -5.786 ; -5.786 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -6.735 ; -6.735 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.100 ; -6.100 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_IN        ; CRT_PIN4_CLK1 ; -3.227 ; -3.227 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -3.757 ; -3.757 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.989 ; -3.989 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.797 ; -3.797 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.260 ; -4.260 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -4.151 ; -4.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.116 ; -4.116 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.064 ; -4.064 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.180 ; -4.180 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -4.054 ; -4.054 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.311 ; -4.311 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.119 ; -4.119 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -4.272 ; -4.272 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.019 ; -4.019 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.162 ; -4.162 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.908 ; -3.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.956 ; -3.956 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESET_COREn    ; CRT_PIN4_CLK1 ; -1.549 ; -1.549 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; -3.598 ; -3.598 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.693 ; -4.693 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; -3.517 ; -3.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; -3.907 ; -3.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; -3.715 ; -3.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; -3.651 ; -3.651 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; -3.720 ; -3.720 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; -3.954 ; -3.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; -3.879 ; -3.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; -3.915 ; -3.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; -3.941 ; -3.941 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; -4.288 ; -4.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; -4.476 ; -4.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; -4.117 ; -4.117 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; -3.929 ; -3.929 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; -3.706 ; -3.706 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_AVR_ENn     ; CRT_PIN4_CLK1 ; -4.465 ; -4.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_ACK    ; CRT_PIN4_CLK1 ; -4.121 ; -4.121 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESET_COREn ; CRT_PIN4_CLK1 ; -4.136 ; -4.136 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.451 ; -4.451 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_CLK     ; CRT_PIN4_CLK1 ; -4.280 ; -4.280 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MOSI    ; CRT_PIN4_CLK1 ; -4.587 ; -4.587 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_SSn[*]  ; CRT_PIN4_CLK1 ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[0] ; CRT_PIN4_CLK1 ; -4.141 ; -4.141 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[1] ; CRT_PIN4_CLK1 ; -4.046 ; -4.046 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SD_SPI_SSn[2] ; CRT_PIN4_CLK1 ; -4.043 ; -4.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_ACK   ; CRT_PIN4_CLK1 ; -3.448 ; -3.448 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_CLK    ; CRT_PIN4_CLK1 ; -3.606 ; -3.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MOSI   ; CRT_PIN4_CLK1 ; -3.626 ; -3.626 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.853 ; -5.853 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VPAn           ; CRT_PIN4_CLK1 ; -5.666 ; -5.666 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -5.554 ; -5.554 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -5.937 ; -5.937 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -5.355 ; -5.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -5.574 ; -5.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.513 ; -4.513 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; AVECn          ; CRT_PIN4_CLK1 ; -3.844 ; -3.844 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; -4.112 ; -4.112 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; -3.660 ; -3.660 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BRn            ; CRT_PIN4_CLK1 ; -3.821 ; -3.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.366 ; -6.366 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.370 ; -6.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -6.381 ; -6.381 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.936 ; -6.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.320 ; -6.320 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -5.687 ; -5.687 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -7.138 ; -7.138 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -7.151 ; -7.151 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.637 ; -7.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -8.182 ; -8.182 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.537 ; -7.537 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.494 ; -7.494 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -5.801 ; -5.801 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.737 ; -4.737 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -4.579 ; -4.579 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -4.947 ; -4.947 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.895 ; -4.895 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -4.956 ; -4.956 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -4.936 ; -4.936 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -5.506 ; -5.506 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -5.178 ; -5.178 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -5.820 ; -5.820 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -5.428 ; -5.428 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.987 ; -4.987 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.715 ; -4.715 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -5.053 ; -5.053 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.686 ; -4.686 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.609 ; -4.609 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; -4.223 ; -4.223 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -5.336 ; -5.336 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -5.141 ; -5.141 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -5.114 ; -5.114 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_RDn        ; CRT_PIN4_CLK1 ; -3.301 ; -3.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; -3.876 ; -3.876 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.481 ; -7.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.598 ; -7.598 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -5.641 ; -5.641 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.349 ; -6.349 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.110 ; -6.110 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.371 ; -6.371 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -6.022 ; -6.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.632 ; -6.632 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.850 ; -7.850 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -6.460 ; -6.460 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.352 ; -7.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.804 ; -6.804 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -7.568 ; -7.568 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -7.452 ; -7.452 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -6.821 ; -6.821 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -7.173 ; -7.173 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -6.766 ; -6.766 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -6.875 ; -6.875 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -8.481 ; -8.481 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -6.560 ; -6.560 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -7.318 ; -7.318 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -7.154 ; -7.154 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -6.833 ; -6.833 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -7.370 ; -7.370 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -8.238 ; -8.238 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -7.202 ; -7.202 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -7.832 ; -7.832 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -7.906 ; -7.906 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.893 ; -4.893 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -5.678 ; -5.678 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -6.661 ; -6.661 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CLK_PLL1      ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[1]        ; CLK_PLL1      ; -6.743 ; -6.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[2]        ; CLK_PLL1      ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[3]        ; CLK_PLL1      ; -6.608 ; -6.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[4]        ; CLK_PLL1      ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  ADR[5]        ; CLK_PLL1      ; -6.628 ; -6.628 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; -6.288 ; -6.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; -6.266 ; -6.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; -6.465 ; -6.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; -6.907 ; -6.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; -6.388 ; -6.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; -6.575 ; -6.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; -6.781 ; -6.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_DCD        ; CLK_PLL1      ; -7.425 ; -7.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; COM_RI         ; CLK_PLL1      ; -7.619 ; -7.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CONFIG[*]      ; CLK_PLL1      ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[1]     ; CLK_PLL1      ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[2]     ; CLK_PLL1      ; -7.205 ; -7.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CONFIG[5]     ; CLK_PLL1      ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; -4.971 ; -4.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; -5.275 ; -5.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; -5.032 ; -5.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; -4.866 ; -4.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; -5.024 ; -5.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; -5.020 ; -5.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; -4.943 ; -4.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; -5.562 ; -5.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; -5.128 ; -5.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; -4.805 ; -4.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; -4.579 ; -4.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FC[*]          ; CLK_PLL1      ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[0]         ; CLK_PLL1      ; -4.585 ; -4.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[1]         ; CLK_PLL1      ; -4.638 ; -4.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  FC[2]         ; CLK_PLL1      ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HDINTn         ; CLK_PLL1      ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_INTRQ      ; CLK_PLL1      ; -7.539 ; -7.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; -4.698 ; -4.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_BSY        ; CLK_PLL1      ; -6.271 ; -6.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LPT_D[*]       ; CLK_PLL1      ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[0]      ; CLK_PLL1      ; -6.032 ; -6.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[1]      ; CLK_PLL1      ; -6.159 ; -6.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[2]      ; CLK_PLL1      ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[3]      ; CLK_PLL1      ; -6.453 ; -6.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[4]      ; CLK_PLL1      ; -7.609 ; -7.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[5]      ; CLK_PLL1      ; -5.986 ; -5.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[6]      ; CLK_PLL1      ; -7.063 ; -7.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  LPT_D[7]      ; CLK_PLL1      ; -6.434 ; -6.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Xn         ; CLK_PLL1      ; -1.607 ; -1.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD0Yn         ; CLK_PLL1      ; -1.690 ; -1.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Xn         ; CLK_PLL1      ; -1.473 ; -1.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PAD1Yn         ; CLK_PLL1      ; -2.531 ; -2.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PENn           ; CLK_PLL1      ; -2.352 ; -2.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; -3.884 ; -3.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; -3.976 ; -3.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; -4.104 ; -4.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; -4.004 ; -4.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; -4.307 ; -4.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; -4.081 ; -4.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; -4.048 ; -4.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; -3.878 ; -3.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; -4.161 ; -4.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; -4.076 ; -4.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; -3.939 ; -3.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RWn            ; CLK_PLL1      ; -4.748 ; -4.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; SD_RESETn      ; CLK_PLL1      ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; -5.231 ; -5.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ADR[*]         ; CRT_PIN4_CLK1 ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; -6.743 ; -6.743 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; -6.496 ; -6.496 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; -6.608 ; -6.608 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; -6.585 ; -6.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; -6.628 ; -6.628 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; -4.687 ; -4.687 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; -6.288 ; -6.288 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; -6.266 ; -6.266 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; -6.465 ; -6.465 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; -6.907 ; -6.907 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; -6.388 ; -6.388 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; -5.771 ; -5.771 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; -6.575 ; -6.575 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; -6.781 ; -6.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_DCD        ; CRT_PIN4_CLK1 ; -7.425 ; -7.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; COM_RI         ; CRT_PIN4_CLK1 ; -7.619 ; -7.619 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CONFIG[*]      ; CRT_PIN4_CLK1 ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[1]     ; CRT_PIN4_CLK1 ; -7.179 ; -7.179 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[2]     ; CRT_PIN4_CLK1 ; -7.205 ; -7.205 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CONFIG[5]     ; CRT_PIN4_CLK1 ; -6.317 ; -6.317 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; -4.971 ; -4.971 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; -5.275 ; -5.275 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; -5.032 ; -5.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; -4.866 ; -4.866 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; -5.024 ; -5.024 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; -5.020 ; -5.020 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; -4.943 ; -4.943 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; -5.562 ; -5.562 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; -4.808 ; -4.808 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; -5.128 ; -5.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; -4.805 ; -4.805 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; -4.474 ; -4.474 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; -4.579 ; -4.579 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; -4.397 ; -4.397 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; -4.251 ; -4.251 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; -4.585 ; -4.585 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; -4.638 ; -4.638 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; -4.473 ; -4.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HDINTn         ; CRT_PIN4_CLK1 ; -7.422 ; -7.422 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_INTRQ      ; CRT_PIN4_CLK1 ; -7.539 ; -7.539 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; -4.698 ; -4.698 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_BSY        ; CRT_PIN4_CLK1 ; -6.271 ; -6.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; -6.032 ; -6.032 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; -6.159 ; -6.159 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; -5.722 ; -5.722 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; -6.453 ; -6.453 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; -7.609 ; -7.609 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; -5.986 ; -5.986 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; -7.063 ; -7.063 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; -6.434 ; -6.434 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Xn         ; CRT_PIN4_CLK1 ; -1.607 ; -1.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD0Yn         ; CRT_PIN4_CLK1 ; -1.690 ; -1.690 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Xn         ; CRT_PIN4_CLK1 ; -1.473 ; -1.473 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PAD1Yn         ; CRT_PIN4_CLK1 ; -2.531 ; -2.531 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PENn           ; CRT_PIN4_CLK1 ; -2.352 ; -2.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; -4.098 ; -4.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; -3.884 ; -3.884 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; -3.976 ; -3.976 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; -4.104 ; -4.104 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; -3.946 ; -3.946 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; -4.004 ; -4.004 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; -4.307 ; -4.307 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; -4.201 ; -4.201 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; -3.872 ; -3.872 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; -4.081 ; -4.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; -4.048 ; -4.048 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; -3.878 ; -3.878 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; -4.161 ; -4.161 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; -4.076 ; -4.076 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; -3.891 ; -3.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; -3.939 ; -3.939 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RWn            ; CRT_PIN4_CLK1 ; -4.748 ; -4.748 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; SD_RESETn      ; CRT_PIN4_CLK1 ; -4.906 ; -4.906 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; -5.231 ; -5.231 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; PLL_FAULT      ; CLK_PLL1      ; 7.683  ; 7.683  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 8.490  ; 8.490  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_RDn       ; CLK_PLL1      ; 29.742 ; 29.742 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 29.732 ; 29.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 21.137 ; 21.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 19.051 ; 19.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 20.040 ; 20.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 19.492 ; 19.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 19.830 ; 19.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 20.099 ; 20.099 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 20.660 ; 20.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 20.319 ; 20.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 21.379 ; 21.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 20.459 ; 20.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 21.707 ; 21.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 21.306 ; 21.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 20.066 ; 20.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 21.746 ; 21.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 22.336 ; 22.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 22.097 ; 22.097 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 22.021 ; 22.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 23.085 ; 23.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 22.447 ; 22.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 23.607 ; 23.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 22.322 ; 22.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 14.257 ; 14.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 10.752 ; 10.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 10.491 ; 10.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 5.081  ; 5.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 28.301 ; 28.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 27.606 ; 27.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 35.573 ; 35.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 35.058 ; 35.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 34.499 ; 34.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 36.038 ; 36.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 34.980 ; 34.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 34.144 ; 34.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 8.031  ; 8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 8.097  ; 8.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL1      ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL1      ; 22.569 ; 22.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL1      ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL1      ; 20.363 ; 20.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL1      ; 22.247 ; 22.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL1      ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL1      ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL1      ; 24.273 ; 24.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL1      ; 23.461 ; 23.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL1      ; 23.780 ; 23.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL1      ; 18.589 ; 18.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL1      ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL1      ; 21.425 ; 21.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL1      ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL1      ; 21.038 ; 21.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL1      ; 21.754 ; 21.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 47.313 ; 47.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 46.506 ; 46.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 45.421 ; 45.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 45.631 ; 45.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 43.988 ; 43.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 47.908 ; 47.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 44.841 ; 44.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 45.197 ; 45.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 44.778 ; 44.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 46.618 ; 46.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 46.953 ; 46.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 45.238 ; 45.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 47.648 ; 47.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 45.313 ; 45.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 6.409  ; 6.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 5.042  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 6.173  ; 6.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 6.195  ; 6.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 20.241 ; 20.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 20.350 ; 20.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 6.086  ; 6.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 5.808  ; 5.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 5.539  ; 5.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 4.925  ; 4.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 4.626  ; 4.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 22.444 ; 22.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 22.363 ; 22.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 30.190 ; 30.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 31.409 ; 31.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 6.916  ; 6.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 8.827  ; 8.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 8.971  ; 8.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 20.164 ; 20.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 28.926 ; 28.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 27.999 ; 27.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 28.293 ; 28.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 28.124 ; 28.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 27.173 ; 27.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 30.310 ; 30.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 28.108 ; 28.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 30.128 ; 30.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 30.098 ; 30.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 27.352 ; 27.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 9.342  ; 9.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 8.640  ; 8.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 8.905  ; 8.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 8.089  ; 8.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 20.476 ; 20.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 6.933  ; 6.933  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 7.371  ; 7.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 6.732  ; 6.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 7.475  ; 7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 7.955  ; 7.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 27.061 ; 27.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 27.129 ; 27.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 28.450 ; 28.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 27.185 ; 27.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 26.596 ; 26.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 25.993 ; 25.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 28.222 ; 28.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 25.880 ; 25.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 22.002 ; 22.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 21.182 ; 21.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 21.291 ; 21.291 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 22.590 ; 22.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 24.707 ; 24.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 23.891 ; 23.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 42.702 ; 42.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 44.563 ; 44.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 43.133 ; 43.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 43.155 ; 43.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 44.544 ; 44.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 44.546 ; 44.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 44.365 ; 44.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 44.132 ; 44.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 43.417 ; 43.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 44.752 ; 44.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 45.057 ; 45.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 44.338 ; 44.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 42.737 ; 42.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 42.443 ; 42.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 26.233 ; 26.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 24.982 ; 24.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 26.426 ; 26.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 24.972 ; 24.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 26.642 ; 26.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 26.365 ; 26.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_WEn        ; CLK_PLL1      ; 12.429 ; 12.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 8.358  ; 8.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 27.779 ; 27.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 29.416 ; 29.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 28.228 ; 28.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 31.282 ; 31.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 30.650 ; 30.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 29.102 ; 29.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 31.614 ; 31.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 11.488 ; 11.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 8.076  ; 8.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 7.144  ; 7.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 5.904  ; 5.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 6.239  ; 6.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 6.178  ; 6.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 6.180  ; 6.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 6.067  ; 6.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 7.472  ; 7.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 5.238  ; 5.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 9.561  ; 9.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 8.626  ; 8.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 7.002  ; 7.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 7.531  ; 7.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 7.538  ; 7.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 20.101 ; 20.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 5.992  ; 5.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 13.744 ; 13.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 17.947 ; 17.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 16.995 ; 16.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 18.781 ; 18.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 18.480 ; 18.480 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 18.470 ; 18.470 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 12.315 ; 12.315 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 17.039 ; 17.039 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 24.311 ; 24.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 23.796 ; 23.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 23.237 ; 23.237 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 24.776 ; 24.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 23.718 ; 23.718 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 22.882 ; 22.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 23.235 ; 23.235 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 36.051 ; 36.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 35.131 ; 35.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 34.153 ; 34.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 34.244 ; 34.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 33.169 ; 33.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 36.521 ; 36.521 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 34.022 ; 34.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 34.304 ; 34.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 33.910 ; 33.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 35.231 ; 35.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 35.566 ; 35.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 33.851 ; 33.851 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 36.386 ; 36.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 33.885 ; 33.885 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 34.509 ; 34.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 10.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 9.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 20.355 ; 20.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 21.574 ; 21.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 18.118 ; 18.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 17.191 ; 17.191 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 17.485 ; 17.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 17.316 ; 17.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 16.365 ; 16.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 19.502 ; 19.502 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 16.846 ; 16.846 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 18.866 ; 18.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 18.836 ; 18.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 16.090 ; 16.090 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 17.019 ; 17.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 18.231 ; 18.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 18.692 ; 18.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 18.479 ; 18.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 17.882 ; 17.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 19.929 ; 19.929 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 17.352 ; 17.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 19.329 ; 19.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 16.301 ; 16.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 12.704 ; 12.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 11.510 ; 11.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 10.327 ; 10.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 10.199 ; 10.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.375 ; 11.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 17.543 ; 17.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 16.725 ; 16.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 31.440 ; 31.440 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 33.188 ; 33.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 31.865 ; 31.865 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 31.768 ; 31.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 33.725 ; 33.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 33.159 ; 33.159 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 33.546 ; 33.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 33.239 ; 33.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 32.549 ; 32.549 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 33.365 ; 33.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 34.080 ; 34.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 33.670 ; 33.670 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 33.076 ; 33.076 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 31.309 ; 31.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 31.485 ; 31.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 22.455 ; 22.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 20.774 ; 20.774 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 22.648 ; 22.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 20.764 ; 20.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 15.535 ; 15.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 15.399 ; 15.258 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 16.516 ; 16.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 18.153 ; 18.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 18.393 ; 18.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 20.176 ; 20.035 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 19.544 ; 19.403 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 17.839 ; 17.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 20.508 ; 20.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 16.637 ; 16.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 29.742 ; 29.742 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 29.732 ; 29.732 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 21.137 ; 21.137 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 19.051 ; 19.051 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 20.040 ; 20.040 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 19.492 ; 19.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 19.830 ; 19.830 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 20.099 ; 20.099 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 20.660 ; 20.660 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 20.319 ; 20.319 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 21.379 ; 21.379 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 20.459 ; 20.459 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 21.707 ; 21.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 21.306 ; 21.306 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 20.813 ; 20.813 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 20.066 ; 20.066 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 23.927 ; 23.927 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 21.746 ; 21.746 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 22.336 ; 22.336 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 22.097 ; 22.097 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 22.021 ; 22.021 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 23.085 ; 23.085 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 22.447 ; 22.447 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 23.607 ; 23.607 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 22.322 ; 22.322 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 14.257 ; 14.257 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 10.752 ; 10.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 10.491 ; 10.491 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 5.081  ; 5.081  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 28.301 ; 28.301 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 27.606 ; 27.606 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 35.573 ; 35.573 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 35.058 ; 35.058 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 34.499 ; 34.499 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 36.038 ; 36.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 34.980 ; 34.980 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 34.144 ; 34.144 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 36.818 ; 36.818 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 8.031  ; 8.031  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 8.097  ; 8.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 11.640 ; 11.640 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 22.569 ; 22.569 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 23.530 ; 23.530 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 20.363 ; 20.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 22.247 ; 22.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 27.611 ; 27.611 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 24.273 ; 24.273 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 23.461 ; 23.461 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 23.780 ; 23.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 18.589 ; 18.589 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 21.425 ; 21.425 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 25.981 ; 25.981 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 21.038 ; 21.038 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 21.754 ; 21.754 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 47.313 ; 47.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 46.506 ; 46.506 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 45.421 ; 45.421 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 45.631 ; 45.631 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 43.988 ; 43.988 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 47.908 ; 47.908 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 44.841 ; 44.841 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 45.197 ; 45.197 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 44.778 ; 44.778 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 46.618 ; 46.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 46.953 ; 46.953 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 49.679 ; 49.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 45.238 ; 45.238 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 47.648 ; 47.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 45.313 ; 45.313 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 6.409  ; 6.409  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 5.042  ; 5.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 6.173  ; 6.173  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 6.964  ; 6.964  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 6.195  ; 6.195  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 20.241 ; 20.241 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 20.350 ; 20.350 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 21.429 ; 21.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 6.086  ; 6.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 5.658  ; 5.658  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 4.736  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 5.808  ; 5.808  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 5.539  ; 5.539  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 4.925  ; 4.925  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 4.626  ; 4.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 22.444 ; 22.444 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 22.363 ; 22.363 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 30.190 ; 30.190 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 31.409 ; 31.409 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 8.062  ; 8.062  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 7.194  ; 7.194  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 6.916  ; 6.916  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 8.827  ; 8.827  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 8.971  ; 8.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 20.164 ; 20.164 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 28.926 ; 28.926 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 27.999 ; 27.999 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 28.293 ; 28.293 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 28.124 ; 28.124 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 27.173 ; 27.173 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 30.310 ; 30.310 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 28.108 ; 28.108 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 30.128 ; 30.128 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 30.098 ; 30.098 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 27.352 ; 27.352 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 9.342  ; 9.342  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 9.543  ; 9.543  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 8.640  ; 8.640  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 8.905  ; 8.905  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 8.089  ; 8.089  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 20.476 ; 20.476 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 7.353  ; 7.353  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 6.933  ; 6.933  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 7.619  ; 7.619  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 7.371  ; 7.371  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 6.744  ; 6.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 7.136  ; 7.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 6.416  ; 6.416  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 6.732  ; 6.732  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 7.475  ; 7.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 7.955  ; 7.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 7.385  ; 7.385  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 27.061 ; 27.061 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 27.129 ; 27.129 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 28.450 ; 28.450 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 27.185 ; 27.185 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 26.596 ; 26.596 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 28.564 ; 28.564 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 25.993 ; 25.993 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 28.222 ; 28.222 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 25.880 ; 25.880 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 22.002 ; 22.002 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 21.637 ; 21.637 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 21.182 ; 21.182 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 21.291 ; 21.291 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 22.590 ; 22.590 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 25.780 ; 25.780 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 24.707 ; 24.707 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 23.891 ; 23.891 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 42.702 ; 42.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 44.563 ; 44.563 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 43.133 ; 43.133 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 43.155 ; 43.155 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 44.544 ; 44.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 44.546 ; 44.546 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 44.365 ; 44.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 44.132 ; 44.132 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 43.417 ; 43.417 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 44.752 ; 44.752 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 46.682 ; 46.682 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 45.467 ; 45.467 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 45.057 ; 45.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 44.338 ; 44.338 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 42.737 ; 42.737 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 42.443 ; 42.443 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 26.233 ; 26.233 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 24.982 ; 24.982 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 26.426 ; 26.426 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 24.972 ; 24.972 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 26.642 ; 26.642 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 26.365 ; 26.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 12.429 ; 12.429 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 8.358  ; 8.358  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 27.779 ; 27.779 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 29.416 ; 29.416 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 28.228 ; 28.228 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 31.282 ; 31.282 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 30.650 ; 30.650 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 29.102 ; 29.102 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 31.614 ; 31.614 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 11.488 ; 11.488 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 8.076  ; 8.076  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 8.496  ; 8.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 7.144  ; 7.144  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 9.997  ; 9.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 5.864  ; 5.864  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 5.904  ; 5.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 6.239  ; 6.239  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 6.178  ; 6.178  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 6.685  ; 6.685  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 6.180  ; 6.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 6.446  ; 6.446  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 6.067  ; 6.067  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 6.512  ; 6.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 7.472  ; 7.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 7.177  ; 7.177  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 5.238  ; 5.238  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 5.386  ; 5.386  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 7.436  ; 7.436  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 9.561  ; 9.561  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 8.626  ; 8.626  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 7.002  ; 7.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 6.553  ; 6.553  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 6.417  ; 6.417  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 7.531  ; 7.531  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 8.636  ; 8.636  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 7.538  ; 7.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 8.791  ; 8.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 20.101 ; 20.101 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 5.992  ; 5.992  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 7.261  ; 7.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 13.744 ; 13.744 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 17.947 ; 17.947 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 16.995 ; 16.995 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 18.781 ; 18.781 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 7.227  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 18.480 ; 18.480 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 18.470 ; 18.470 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 12.315 ; 12.315 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 17.039 ; 17.039 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 16.344 ; 16.344 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 24.311 ; 24.311 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 23.796 ; 23.796 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 23.237 ; 23.237 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 24.776 ; 24.776 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 23.718 ; 23.718 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 22.882 ; 22.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 25.556 ; 25.556 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 23.235 ; 23.235 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 36.051 ; 36.051 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 35.131 ; 35.131 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 34.153 ; 34.153 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 34.244 ; 34.244 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 33.169 ; 33.169 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 36.521 ; 36.521 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 34.022 ; 34.022 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 34.304 ; 34.304 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 33.910 ; 33.910 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 35.231 ; 35.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 35.566 ; 35.566 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 38.292 ; 38.292 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 33.851 ; 33.851 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 36.386 ; 36.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 33.885 ; 33.885 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 34.509 ; 34.509 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 10.386 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 9.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 20.355 ; 20.355 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 21.574 ; 21.574 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 18.118 ; 18.118 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 17.191 ; 17.191 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 17.485 ; 17.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 17.316 ; 17.316 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 16.365 ; 16.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 19.502 ; 19.502 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 16.846 ; 16.846 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 18.866 ; 18.866 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 18.836 ; 18.836 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 16.090 ; 16.090 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 17.019 ; 17.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 18.231 ; 18.231 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 18.692 ; 18.692 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 20.019 ; 20.019 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 18.479 ; 18.479 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 17.882 ; 17.882 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 19.929 ; 19.929 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 17.352 ; 17.352 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 19.329 ; 19.329 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 16.301 ; 16.301 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 12.704 ; 12.704 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 11.510 ; 11.510 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 10.327 ; 10.327 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 10.199 ; 10.199 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.375 ; 11.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 13.870 ; 14.011 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 17.543 ; 17.543 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 16.725 ; 16.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 31.440 ; 31.440 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 33.188 ; 33.188 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 31.865 ; 31.865 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 31.768 ; 31.768 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 33.725 ; 33.725 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 33.159 ; 33.159 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 33.546 ; 33.546 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 33.239 ; 33.239 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 32.549 ; 32.549 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 33.365 ; 33.365 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 35.295 ; 35.295 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 34.080 ; 34.080 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 33.670 ; 33.670 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 33.076 ; 33.076 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 31.309 ; 31.309 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 31.485 ; 31.485 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 22.455 ; 22.455 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 20.774 ; 20.774 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 22.648 ; 22.648 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 20.764 ; 20.764 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 15.535 ; 15.676 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 15.399 ; 15.258 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 16.516 ; 16.375 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 18.153 ; 18.012 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 18.393 ; 18.393 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 20.176 ; 20.035 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 19.544 ; 19.403 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 17.839 ; 17.698 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 20.508 ; 20.367 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 16.637 ; 16.637 ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 7.227  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 19.958 ; 19.958 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 12.495 ; 12.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BERRn          ; CLK_PLL1      ; 6.590  ; 6.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BUTTONn        ; CLK_PLL1      ; 18.517 ; 18.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 17.822 ; 17.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 25.789 ; 25.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 25.274 ; 25.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 24.715 ; 24.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 26.254 ; 26.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 25.196 ; 25.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 24.360 ; 24.360 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 24.713 ; 24.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 24.023 ; 24.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 21.817 ; 21.817 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 23.701 ; 23.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 25.727 ; 25.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 24.915 ; 24.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 25.234 ; 25.234 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 20.043 ; 20.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 22.879 ; 22.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 22.492 ; 22.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 23.208 ; 23.208 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_LDACn      ; CLK_PLL1      ; 8.106  ; 8.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SCLK       ; CLK_PLL1      ; 9.220  ; 9.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SYNCn      ; CLK_PLL1      ; 5.743  ; 5.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 37.529 ; 37.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 36.440 ; 36.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 35.355 ; 35.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 35.565 ; 35.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 34.204 ; 34.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 37.842 ; 37.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 35.057 ; 35.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 35.339 ; 35.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 34.945 ; 34.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 36.552 ; 36.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 36.887 ; 36.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 35.172 ; 35.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 37.864 ; 37.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 35.247 ; 35.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 35.544 ; 35.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 5.776  ; 5.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_CEn      ; CLK_PLL1      ; 20.610 ; 20.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_OEn      ; CLK_PLL1      ; 21.829 ; 21.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC          ; CLK_PLL1      ; 21.618 ; 21.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS0n       ; CLK_PLL1      ; 19.346 ; 19.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS1n       ; CLK_PLL1      ; 18.419 ; 18.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 18.713 ; 18.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 18.544 ; 18.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IORDn      ; CLK_PLL1      ; 17.593 ; 17.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IOWRn      ; CLK_PLL1      ; 20.730 ; 20.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RHn        ; CLK_PLL1      ; 18.324 ; 18.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RLn        ; CLK_PLL1      ; 20.344 ; 20.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WEn        ; CLK_PLL1      ; 20.314 ; 20.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WL         ; CLK_PLL1      ; 17.568 ; 17.568 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 13.230 ; 13.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 4.955  ; 4.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 6.837  ; 6.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PADRSTn        ; CLK_PLL1      ; 6.651  ; 6.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 16.838 ; 16.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 16.787 ; 16.787 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 17.785 ; 17.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 16.151 ; 16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 17.798 ; 17.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 15.800 ; 15.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 17.081 ; 17.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 15.027 ; 15.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 15.392 ; 15.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 15.271 ; 15.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 14.804 ; 14.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 11.952 ; 11.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 17.723 ; 17.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 16.905 ; 16.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 32.918 ; 32.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 33.067 ; 33.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 33.089 ; 33.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 34.760 ; 34.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 34.480 ; 34.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 34.581 ; 34.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 34.274 ; 34.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 33.584 ; 33.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 34.686 ; 34.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 35.401 ; 35.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 34.991 ; 34.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 34.554 ; 34.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 32.671 ; 32.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 32.520 ; 32.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 22.635 ; 22.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 20.954 ; 20.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 22.828 ; 22.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 20.944 ; 20.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 17.202 ; 17.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 16.925 ; 16.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 13.555 ; 13.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 9.316  ; 9.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM0n          ; CLK_PLL1      ; 18.042 ; 18.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM1n          ; CLK_PLL1      ; 19.679 ; 19.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM2n          ; CLK_PLL1      ; 18.648 ; 18.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM3n          ; CLK_PLL1      ; 21.702 ; 21.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM4n          ; CLK_PLL1      ; 21.070 ; 21.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM5n          ; CLK_PLL1      ; 19.365 ; 19.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM6n          ; CLK_PLL1      ; 22.034 ; 22.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 13.095 ; 13.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC          ; CLK_PLL1      ; 15.198 ; 15.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 19.958 ; 19.958 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 19.948 ; 19.948 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 12.495 ; 12.495 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 6.590  ; 6.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 18.517 ; 18.517 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 17.822 ; 17.822 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 25.789 ; 25.789 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 25.274 ; 25.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 24.715 ; 24.715 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 26.254 ; 26.254 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 25.196 ; 25.196 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 24.360 ; 24.360 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 27.034 ; 27.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 24.713 ; 24.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 24.023 ; 24.023 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 24.984 ; 24.984 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 21.817 ; 21.817 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 23.701 ; 23.701 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 29.065 ; 29.065 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 25.727 ; 25.727 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 24.915 ; 24.915 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 25.234 ; 25.234 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 20.043 ; 20.043 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 22.879 ; 22.879 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 27.435 ; 27.435 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 22.492 ; 22.492 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 23.208 ; 23.208 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 8.106  ; 8.106  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 9.220  ; 9.220  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 5.743  ; 5.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 37.529 ; 37.529 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 36.440 ; 36.440 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 35.355 ; 35.355 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 35.565 ; 35.565 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 34.204 ; 34.204 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 37.842 ; 37.842 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 35.057 ; 35.057 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 35.339 ; 35.339 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 34.945 ; 34.945 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 36.552 ; 36.552 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 36.887 ; 36.887 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 39.613 ; 39.613 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 35.172 ; 35.172 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 37.864 ; 37.864 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 35.247 ; 35.247 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 35.544 ; 35.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 5.776  ; 5.776  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 20.610 ; 20.610 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 21.829 ; 21.829 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 21.618 ; 21.618 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 19.346 ; 19.346 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 18.419 ; 18.419 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 18.713 ; 18.713 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 18.544 ; 18.544 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 17.593 ; 17.593 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 20.730 ; 20.730 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 18.324 ; 18.324 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 20.344 ; 20.344 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 20.314 ; 20.314 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 17.568 ; 17.568 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 13.230 ; 13.230 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 5.545  ; 5.545  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 4.955  ; 4.955  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 6.837  ; 6.837  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 6.651  ; 6.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 16.838 ; 16.838 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 16.787 ; 16.787 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 17.785 ; 17.785 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 18.671 ; 18.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 16.151 ; 16.151 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 17.798 ; 17.798 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 15.800 ; 15.800 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 17.081 ; 17.081 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 15.027 ; 15.027 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 15.392 ; 15.392 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 14.578 ; 14.578 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 15.271 ; 15.271 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 14.804 ; 14.804 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 11.952 ; 11.952 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 15.537 ; 15.537 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 17.723 ; 17.723 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 16.905 ; 16.905 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.807  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 32.918 ; 32.918 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 34.497 ; 34.497 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 33.067 ; 33.067 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 33.089 ; 33.089 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 34.760 ; 34.760 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 34.480 ; 34.480 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 34.581 ; 34.581 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 34.274 ; 34.274 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 33.584 ; 33.584 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 34.686 ; 34.686 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 36.616 ; 36.616 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 35.401 ; 35.401 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 34.991 ; 34.991 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 34.554 ; 34.554 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 32.671 ; 32.671 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 32.520 ; 32.520 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 22.635 ; 22.635 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 20.954 ; 20.954 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 22.828 ; 22.828 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 20.944 ; 20.944 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 17.202 ; 17.202 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 16.925 ; 16.925 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 13.555 ; 13.555 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 9.316  ; 9.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 18.042 ; 18.042 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 19.679 ; 19.679 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 18.648 ; 18.648 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 21.702 ; 21.702 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 21.070 ; 21.070 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 19.365 ; 19.365 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 22.034 ; 22.034 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 13.095 ; 13.095 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 15.198 ; 15.198 ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 9.025  ; 9.025  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.807  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 8.681  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CLK_AUX        ; CLK_PLL2      ; 2.896  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL2      ; 24.605 ; 24.605 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL2      ; 23.644 ; 23.644 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL2      ; 24.605 ; 24.605 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL2      ; 21.438 ; 21.438 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL2      ; 23.322 ; 23.322 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL2      ; 28.686 ; 28.686 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL2      ; 28.686 ; 28.686 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL2      ; 25.348 ; 25.348 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL2      ; 24.536 ; 24.536 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL2      ; 24.855 ; 24.855 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL2      ; 19.664 ; 19.664 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL2      ; 27.056 ; 27.056 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL2      ; 22.500 ; 22.500 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL2      ; 27.056 ; 27.056 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL2      ; 22.113 ; 22.113 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL2      ; 22.829 ; 22.829 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL2      ; 6.475  ; 6.475  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ; 6.553  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL2      ; 25.204 ; 25.204 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL2      ; 25.204 ; 25.204 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL2      ; 24.818 ; 24.818 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL2      ; 23.247 ; 23.247 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL2      ; 23.280 ; 23.280 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL2      ; 21.739 ; 21.739 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL2      ; 24.593 ; 24.593 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL2      ; 21.736 ; 21.736 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL2      ; 23.742 ; 23.742 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL2      ; 22.758 ; 22.758 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL2      ; 24.691 ; 24.691 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL2      ; 23.832 ; 23.832 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL2      ; 21.239 ; 21.239 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL2      ; 23.561 ; 23.561 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL2      ; 20.593 ; 20.593 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL2      ; 22.875 ; 22.875 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL2      ; 20.959 ; 20.959 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL2      ; 20.804 ; 20.804 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL2      ; 22.295 ; 22.295 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL2      ; 21.231 ; 21.231 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL2      ; 21.260 ; 21.260 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL2      ; 22.677 ; 22.677 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL2      ; 21.397 ; 21.397 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL2      ; 22.825 ; 22.825 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL2      ; 23.561 ; 23.561 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL2      ; 14.819 ; 14.819 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ; 8.302  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ; 8.302  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL2      ;        ; 2.896  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ;        ; 6.553  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ;        ; 8.302  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ;        ; 8.302  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.821  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.821  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; Data Port      ; Clock Port    ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                            ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+
; PLL_FAULT      ; CLK_PLL1      ; 3.910  ; 3.910  ; Rise       ; CLK_PLL1                                                   ;
; RESETn         ; CLK_PLL1      ; 4.222  ; 4.222  ; Rise       ; CLK_PLL1                                                   ;
; ACSI_RDn       ; CLK_PLL1      ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 3.651  ; 3.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ADR[*]         ; CLK_PLL1      ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[1]        ; CLK_PLL1      ; 4.815  ; 4.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[2]        ; CLK_PLL1      ; 4.191  ; 4.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[3]        ; CLK_PLL1      ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[4]        ; CLK_PLL1      ; 4.169  ; 4.169  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[5]        ; CLK_PLL1      ; 4.310  ; 4.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[6]        ; CLK_PLL1      ; 4.398  ; 4.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[7]        ; CLK_PLL1      ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[8]        ; CLK_PLL1      ; 4.709  ; 4.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[9]        ; CLK_PLL1      ; 4.323  ; 4.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[10]       ; CLK_PLL1      ; 4.421  ; 4.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[11]       ; CLK_PLL1      ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[12]       ; CLK_PLL1      ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[13]       ; CLK_PLL1      ; 4.142  ; 4.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[14]       ; CLK_PLL1      ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[15]       ; CLK_PLL1      ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[16]       ; CLK_PLL1      ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[17]       ; CLK_PLL1      ; 4.046  ; 4.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[18]       ; CLK_PLL1      ; 4.683  ; 4.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[19]       ; CLK_PLL1      ; 4.439  ; 4.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[20]       ; CLK_PLL1      ; 4.316  ; 4.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[21]       ; CLK_PLL1      ; 4.597  ; 4.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[22]       ; CLK_PLL1      ; 5.187  ; 5.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  ADR[23]       ; CLK_PLL1      ; 4.319  ; 4.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.457  ; 3.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGACKn         ; CLK_PLL1      ; 3.520  ; 3.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BGOn           ; CLK_PLL1      ; 3.431  ; 3.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BOOT_LED       ; CLK_PLL1      ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.087  ; 4.087  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 2.742  ; 2.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_DTR        ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_RTS        ; CLK_PLL1      ; 3.653  ; 3.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; COM_TxD        ; CLK_PLL1      ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL1      ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL1      ; 5.129  ; 5.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL1      ; 5.902  ; 5.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL1      ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL1      ; 6.024  ; 6.024  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL1      ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL1      ; 5.283  ; 5.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL1      ; 5.516  ; 5.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL1      ; 4.887  ; 4.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL1      ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL1      ; 5.818  ; 5.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL1      ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL1      ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL1      ; 5.505  ; 5.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL1      ; 5.677  ; 5.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL1      ; 5.768  ; 5.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 4.373  ; 4.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 4.692  ; 4.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 3.966  ; 3.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 4.504  ; 4.504  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 4.123  ; 4.123  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 3.884  ; 3.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 4.744  ; 4.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 3.971  ; 3.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 3.981  ; 3.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 2.747  ; 2.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 3.020  ; 3.020  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 2.796  ; 2.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_CE      ; CLK_PLL1      ; 2.608  ; 2.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_D       ; CLK_PLL1      ; 2.289  ; 2.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DS1392_SCL     ; CLK_PLL1      ; 2.506  ; 2.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DTACKn         ; CLK_PLL1      ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; E              ; CLK_PLL1      ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FC[*]          ; CLK_PLL1      ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[0]         ; CLK_PLL1      ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[1]         ; CLK_PLL1      ; 3.596  ; 3.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  FC[2]         ; CLK_PLL1      ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D0SELn     ; CLK_PLL1      ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_D1SELn     ; CLK_PLL1      ; 2.599  ; 2.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_DIRCn      ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_MOn        ; CLK_PLL1      ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_SDSEL      ; CLK_PLL1      ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_STEPn      ; CLK_PLL1      ; 2.512  ; 2.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WDn        ; CLK_PLL1      ; 2.229  ; 2.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FDD_WGn        ; CLK_PLL1      ; 2.097  ; 2.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ; 4.306  ; 4.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ; 4.013  ; 4.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 3.958  ; 3.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 4.387  ; 4.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_WEn      ; CLK_PLL1      ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; GPO            ; CLK_PLL1      ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HALTn          ; CLK_PLL1      ; 2.918  ; 2.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDACKn         ; CLK_PLL1      ; 3.364  ; 3.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HDCSn          ; CLK_PLL1      ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL1      ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 3.702  ; 3.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 3.595  ; 3.656  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 3.830  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 3.610  ; 3.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 3.631  ; 3.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 3.641  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 3.476  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.363  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.542  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.384  ; 3.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; KEYB_TxD       ; CLK_PLL1      ; 3.189  ; 3.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDATA[*]       ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[0]      ; CLK_PLL1      ; 3.609  ; 3.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[1]      ; CLK_PLL1      ; 3.097  ; 3.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[2]      ; CLK_PLL1      ; 3.270  ; 3.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LDATA[3]      ; CLK_PLL1      ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LFS            ; CLK_PLL1      ; 3.221  ; 3.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LLCLK          ; CLK_PLL1      ; 3.136  ; 3.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_D[*]       ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[0]      ; CLK_PLL1      ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[1]      ; CLK_PLL1      ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[2]      ; CLK_PLL1      ; 2.990  ; 2.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[3]      ; CLK_PLL1      ; 3.153  ; 3.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[4]      ; CLK_PLL1      ; 2.896  ; 2.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[5]      ; CLK_PLL1      ; 2.977  ; 2.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[6]      ; CLK_PLL1      ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  LPT_D[7]      ; CLK_PLL1      ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LPT_STRB       ; CLK_PLL1      ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; MIDI_OLR       ; CLK_PLL1      ; 2.606  ; 2.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 6.360  ; 6.360  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 6.333  ; 6.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.181  ; 6.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.028  ; 6.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 6.858  ; 6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.337  ; 6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.281  ; 4.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.935  ; 3.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.777  ; 3.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.183  ; 4.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.643  ; 4.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.866  ; 4.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.159  ; 5.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 4.859  ; 4.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.349  ; 5.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 4.219  ; 4.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 4.570  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.380  ; 5.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 4.374  ; 4.374  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.590  ; 4.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.505  ; 4.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.968  ; 3.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.661  ; 4.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.958  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.436  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 4.913  ; 5.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_WEn        ; CLK_PLL1      ; 4.894  ; 4.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RESETn         ; CLK_PLL1      ; 3.204  ; 3.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 3.960  ; 3.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.792  ; 4.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.502  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.053  ; 4.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.723  ; 4.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.431  ; 4.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RWn            ; CLK_PLL1      ; 3.571  ; 3.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ACKn      ; CLK_PLL1      ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_ATNn      ; CLK_PLL1      ; 3.738  ; 3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_BSYn      ; CLK_PLL1      ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_CTRL_ENn  ; CLK_PLL1      ; 2.820  ; 2.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_D[*]      ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[0]     ; CLK_PLL1      ; 2.625  ; 2.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[1]     ; CLK_PLL1      ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[2]     ; CLK_PLL1      ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[3]     ; CLK_PLL1      ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[4]     ; CLK_PLL1      ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[5]     ; CLK_PLL1      ; 2.653  ; 2.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[6]     ; CLK_PLL1      ; 2.765  ; 2.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  SCSI_D[7]     ; CLK_PLL1      ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DCn       ; CLK_PLL1      ; 2.197  ; 2.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_DP        ; CLK_PLL1      ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_IOn       ; CLK_PLL1      ; 2.882  ; 2.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_MSGn      ; CLK_PLL1      ; 2.181  ; 2.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RDn       ; CLK_PLL1      ; 2.779  ; 2.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_REQn      ; CLK_PLL1      ; 2.441  ; 2.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_RSTn      ; CLK_PLL1      ; 2.347  ; 2.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_SELn      ; CLK_PLL1      ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SCSI_WRn       ; CLK_PLL1      ; 2.760  ; 2.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_BOOT_REQ    ; CLK_PLL1      ; 3.591  ; 3.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SD_SPI_MISO    ; CLK_PLL1      ; 3.790  ; 3.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_BOOT_REQ   ; CLK_PLL1      ; 2.496  ; 2.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; SYS_SPI_MISO   ; CLK_PLL1      ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UART_MIDI_RTSn ; CLK_PLL1      ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDATA[*]       ; CLK_PLL1      ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[0]      ; CLK_PLL1      ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[1]      ; CLK_PLL1      ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[2]      ; CLK_PLL1      ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  UDATA[3]      ; CLK_PLL1      ; 3.034  ; 3.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.279  ; 3.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VDCLK          ; CLK_PLL1      ; 2.671  ; 2.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VMAn           ; CLK_PLL1      ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL1      ; 5.046  ; 5.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_A       ; CLK_PLL1      ; 3.859  ; 3.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_B       ; CLK_PLL1      ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; YM_OUT_C       ; CLK_PLL1      ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CLK_PLL1      ; 5.448  ; 5.448  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.438  ; 5.438  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ASn            ; CLK_PLL1      ; 3.457  ; 3.457  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; BUTTONn        ; CLK_PLL1      ; 4.211  ; 4.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CA1_OUT        ; CLK_PLL1      ; 4.483  ; 4.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; CD[*]          ; CLK_PLL1      ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[0]         ; CLK_PLL1      ; 6.289  ; 6.289  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[1]         ; CLK_PLL1      ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[2]         ; CLK_PLL1      ; 5.985  ; 5.985  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[3]         ; CLK_PLL1      ; 6.298  ; 6.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[4]         ; CLK_PLL1      ; 6.158  ; 6.158  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[5]         ; CLK_PLL1      ; 6.070  ; 6.070  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[6]         ; CLK_PLL1      ; 6.085  ; 6.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  CD[7]         ; CLK_PLL1      ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL1      ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL1      ; 7.411  ; 7.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL1      ; 7.142  ; 7.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL1      ; 6.846  ; 6.846  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL1      ; 6.961  ; 6.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL1      ; 6.344  ; 6.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL1      ; 7.503  ; 7.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL1      ; 6.189  ; 6.189  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL1      ; 6.449  ; 6.449  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL1      ; 6.472  ; 6.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL1      ; 6.863  ; 6.745  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL1      ; 6.646  ; 6.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[11]      ; CLK_PLL1      ; 7.902  ; 7.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[12]      ; CLK_PLL1      ; 6.362  ; 6.362  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[13]      ; CLK_PLL1      ; 7.614  ; 7.533  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[14]      ; CLK_PLL1      ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[15]      ; CLK_PLL1      ; 6.004  ; 6.004  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_18   ; CLK_PLL1      ;        ; 4.306  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_ADR_19   ; CLK_PLL1      ;        ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.562  ; 5.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; FLASH_OEn      ; CLK_PLL1      ; 6.060  ; 5.826  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS0n       ; CLK_PLL1      ; 3.763  ; 3.702  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_CS1n       ; CLK_PLL1      ; 3.656  ; 3.595  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 3.891  ; 3.830  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 3.671  ; 3.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IORDn      ; CLK_PLL1      ; 3.715  ; 3.631  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; IDE_IOWRn      ; CLK_PLL1      ; 3.720  ; 3.641  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RHn        ; CLK_PLL1      ; 3.663  ; 3.476  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_RLn        ; CLK_PLL1      ; 4.570  ; 4.363  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WEn        ; CLK_PLL1      ; 4.335  ; 4.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; JOY_WL         ; CLK_PLL1      ; 3.116  ; 3.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; LDSn           ; CLK_PLL1      ; 3.267  ; 3.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 6.613  ; 6.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 6.584  ; 6.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 6.305  ; 6.305  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 6.394  ; 6.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 7.067  ; 7.067  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 6.065  ; 6.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 5.899  ; 5.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.281  ; 4.281  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.935  ; 3.935  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 3.777  ; 3.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_BA[*]      ; CLK_PLL1      ; 4.179  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 4.183  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.179  ; 4.768  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS0n      ; CLK_PLL1      ; 4.278  ; 4.643  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_CAS1n      ; CLK_PLL1      ; 4.231  ; 3.866  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 5.590  ; 5.590  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 6.227  ; 6.166  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 6.003  ; 6.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 6.058  ; 6.058  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 6.473  ; 6.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 6.162  ; 6.162  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 6.020  ; 6.020  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 6.131  ; 6.131  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 6.083  ; 5.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 6.234  ; 6.116  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 6.783  ; 6.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 6.267  ; 6.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 6.426  ; 6.426  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 6.465  ; 6.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.962  ; 4.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0H      ; CLK_PLL1      ; 4.774  ; 4.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM0L      ; CLK_PLL1      ; 3.904  ; 3.968  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1H      ; CLK_PLL1      ; 4.930  ; 4.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DQM1L      ; CLK_PLL1      ; 3.894  ; 3.958  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS0n      ; CLK_PLL1      ; 5.071  ; 5.436  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_RAS1n      ; CLK_PLL1      ; 5.278  ; 4.913  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM0n          ; CLK_PLL1      ; 4.005  ; 4.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM1n          ; CLK_PLL1      ; 4.832  ; 4.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM2n          ; CLK_PLL1      ; 4.736  ; 4.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM3n          ; CLK_PLL1      ; 4.351  ; 4.351  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM4n          ; CLK_PLL1      ; 4.086  ; 4.086  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM5n          ; CLK_PLL1      ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ROM6n          ; CLK_PLL1      ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; UDSn           ; CLK_PLL1      ; 3.279  ; 3.279  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 3.651  ; 3.651  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ADR[*]         ; CRT_PIN4_CLK1 ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[1]        ; CRT_PIN4_CLK1 ; 4.815  ; 4.815  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[2]        ; CRT_PIN4_CLK1 ; 4.191  ; 4.191  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[3]        ; CRT_PIN4_CLK1 ; 4.329  ; 4.329  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[4]        ; CRT_PIN4_CLK1 ; 4.169  ; 4.169  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[5]        ; CRT_PIN4_CLK1 ; 4.310  ; 4.310  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[6]        ; CRT_PIN4_CLK1 ; 4.398  ; 4.398  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[7]        ; CRT_PIN4_CLK1 ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[8]        ; CRT_PIN4_CLK1 ; 4.709  ; 4.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[9]        ; CRT_PIN4_CLK1 ; 4.323  ; 4.323  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[10]       ; CRT_PIN4_CLK1 ; 4.421  ; 4.421  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[11]       ; CRT_PIN4_CLK1 ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[12]       ; CRT_PIN4_CLK1 ; 3.997  ; 3.997  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[13]       ; CRT_PIN4_CLK1 ; 4.142  ; 4.142  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[14]       ; CRT_PIN4_CLK1 ; 3.969  ; 3.969  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[15]       ; CRT_PIN4_CLK1 ; 4.780  ; 4.780  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[16]       ; CRT_PIN4_CLK1 ; 4.180  ; 4.180  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[17]       ; CRT_PIN4_CLK1 ; 4.046  ; 4.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[18]       ; CRT_PIN4_CLK1 ; 4.683  ; 4.683  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[19]       ; CRT_PIN4_CLK1 ; 4.439  ; 4.439  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[20]       ; CRT_PIN4_CLK1 ; 4.316  ; 4.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[21]       ; CRT_PIN4_CLK1 ; 4.597  ; 4.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[22]       ; CRT_PIN4_CLK1 ; 5.187  ; 5.187  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  ADR[23]       ; CRT_PIN4_CLK1 ; 4.319  ; 4.319  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.457  ; 3.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGACKn         ; CRT_PIN4_CLK1 ; 3.520  ; 3.520  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BGOn           ; CRT_PIN4_CLK1 ; 3.431  ; 3.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BOOT_LED       ; CRT_PIN4_CLK1 ; 2.294  ; 2.294  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.087  ; 4.087  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 2.758  ; 2.758  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 3.488  ; 3.488  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 3.357  ; 3.357  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 3.248  ; 3.248  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 3.798  ; 3.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 2.742  ; 2.742  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 2.641  ; 2.641  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 3.201  ; 3.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 3.281  ; 3.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_DTR        ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_RTS        ; CRT_PIN4_CLK1 ; 3.653  ; 3.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; COM_TxD        ; CRT_PIN4_CLK1 ; 3.708  ; 3.708  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 5.129  ; 5.129  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 5.902  ; 5.902  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 4.956  ; 4.956  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 6.024  ; 6.024  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 5.283  ; 5.283  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 5.516  ; 5.516  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 4.887  ; 4.887  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 4.773  ; 4.773  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 5.818  ; 5.818  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 5.397  ; 5.397  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 5.505  ; 5.505  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 5.677  ; 5.677  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 5.768  ; 5.768  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 4.373  ; 4.373  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 4.692  ; 4.692  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 3.966  ; 3.966  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 4.504  ; 4.504  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 4.123  ; 4.123  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 3.884  ; 3.884  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 4.744  ; 4.744  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 3.971  ; 3.971  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 2.982  ; 2.982  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 3.981  ; 3.981  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 2.747  ; 2.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 2.457  ; 2.457  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 3.020  ; 3.020  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 2.796  ; 2.796  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_CE      ; CRT_PIN4_CLK1 ; 2.608  ; 2.608  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_D       ; CRT_PIN4_CLK1 ; 2.289  ; 2.289  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DS1392_SCL     ; CRT_PIN4_CLK1 ; 2.506  ; 2.506  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DTACKn         ; CRT_PIN4_CLK1 ; 2.961  ; 2.961  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; E              ; CRT_PIN4_CLK1 ; 2.791  ; 2.791  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FC[*]          ; CRT_PIN4_CLK1 ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[0]         ; CRT_PIN4_CLK1 ; 3.401  ; 3.401  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[1]         ; CRT_PIN4_CLK1 ; 3.596  ; 3.596  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  FC[2]         ; CRT_PIN4_CLK1 ; 3.367  ; 3.367  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D0SELn     ; CRT_PIN4_CLK1 ; 2.709  ; 2.709  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_D1SELn     ; CRT_PIN4_CLK1 ; 2.599  ; 2.599  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_DIRCn      ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_MOn        ; CRT_PIN4_CLK1 ; 2.168  ; 2.168  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_SDSEL      ; CRT_PIN4_CLK1 ; 2.603  ; 2.603  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_STEPn      ; CRT_PIN4_CLK1 ; 2.512  ; 2.512  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WDn        ; CRT_PIN4_CLK1 ; 2.229  ; 2.229  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FDD_WGn        ; CRT_PIN4_CLK1 ; 2.097  ; 2.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ; 4.306  ; 4.722  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ; 4.013  ; 4.406  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 3.958  ; 3.958  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 4.387  ; 4.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_WEn      ; CRT_PIN4_CLK1 ; 3.490  ; 3.490  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; GPO            ; CRT_PIN4_CLK1 ; 3.225  ; 3.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HALTn          ; CRT_PIN4_CLK1 ; 2.918  ; 2.918  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDACKn         ; CRT_PIN4_CLK1 ; 3.364  ; 3.364  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HDCSn          ; CRT_PIN4_CLK1 ; 3.190  ; 3.190  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 5.878  ; 5.878  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 3.702  ; 3.763  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 3.595  ; 3.656  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 3.830  ; 3.891  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 3.610  ; 3.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 3.631  ; 3.715  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 3.641  ; 3.720  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 3.476  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.363  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.542  ; 4.335  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.384  ; 3.116  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; KEYB_TxD       ; CRT_PIN4_CLK1 ; 3.189  ; 3.189  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDATA[*]       ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[0]      ; CRT_PIN4_CLK1 ; 3.609  ; 3.609  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[1]      ; CRT_PIN4_CLK1 ; 3.097  ; 3.097  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[2]      ; CRT_PIN4_CLK1 ; 3.270  ; 3.270  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LDATA[3]      ; CRT_PIN4_CLK1 ; 2.960  ; 2.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.267  ; 3.267  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LFS            ; CRT_PIN4_CLK1 ; 3.221  ; 3.221  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LLCLK          ; CRT_PIN4_CLK1 ; 3.136  ; 3.136  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_D[*]       ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[0]      ; CRT_PIN4_CLK1 ; 3.482  ; 3.482  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[1]      ; CRT_PIN4_CLK1 ; 3.316  ; 3.316  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[2]      ; CRT_PIN4_CLK1 ; 2.990  ; 2.990  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[3]      ; CRT_PIN4_CLK1 ; 3.153  ; 3.153  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[4]      ; CRT_PIN4_CLK1 ; 2.896  ; 2.896  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[5]      ; CRT_PIN4_CLK1 ; 2.977  ; 2.977  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[6]      ; CRT_PIN4_CLK1 ; 2.888  ; 2.888  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  LPT_D[7]      ; CRT_PIN4_CLK1 ; 3.285  ; 3.285  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LPT_STRB       ; CRT_PIN4_CLK1 ; 3.441  ; 3.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; MIDI_OLR       ; CRT_PIN4_CLK1 ; 2.606  ; 2.606  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 6.360  ; 6.360  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 6.333  ; 6.333  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.181  ; 6.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.028  ; 6.028  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 6.858  ; 6.858  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 5.903  ; 5.903  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.337  ; 6.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 5.601  ; 5.601  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.281  ; 4.281  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.935  ; 3.935  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.777  ; 3.777  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.183  ; 4.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.643  ; 4.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.866  ; 4.231  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.292  ; 4.292  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.769  ; 4.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 4.799  ; 4.799  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 4.881  ; 4.881  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.159  ; 5.159  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 4.859  ; 4.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.349  ; 5.349  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 4.219  ; 4.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 4.570  ; 4.570  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.380  ; 5.380  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 4.374  ; 4.374  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 4.860  ; 4.860  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 4.383  ; 4.383  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.590  ; 4.590  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.505  ; 4.774  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.968  ; 3.904  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.661  ; 4.930  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.958  ; 3.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.436  ; 5.071  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 4.913  ; 5.278  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 4.894  ; 4.894  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 3.204  ; 3.204  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.960  ; 3.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.792  ; 4.792  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.502  ; 4.736  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.053  ; 4.053  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.898  ; 3.898  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.723  ; 4.723  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.431  ; 4.431  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RWn            ; CRT_PIN4_CLK1 ; 3.571  ; 3.571  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ACKn      ; CRT_PIN4_CLK1 ; 3.061  ; 3.061  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_ATNn      ; CRT_PIN4_CLK1 ; 3.738  ; 3.738  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_BSYn      ; CRT_PIN4_CLK1 ; 2.584  ; 2.584  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_CTRL_ENn  ; CRT_PIN4_CLK1 ; 2.820  ; 2.820  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_D[*]      ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[0]     ; CRT_PIN4_CLK1 ; 2.625  ; 2.625  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[1]     ; CRT_PIN4_CLK1 ; 2.602  ; 2.602  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[2]     ; CRT_PIN4_CLK1 ; 2.729  ; 2.729  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[3]     ; CRT_PIN4_CLK1 ; 2.705  ; 2.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[4]     ; CRT_PIN4_CLK1 ; 2.915  ; 2.915  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[5]     ; CRT_PIN4_CLK1 ; 2.653  ; 2.653  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[6]     ; CRT_PIN4_CLK1 ; 2.765  ; 2.765  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  SCSI_D[7]     ; CRT_PIN4_CLK1 ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DCn       ; CRT_PIN4_CLK1 ; 2.197  ; 2.197  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_DP        ; CRT_PIN4_CLK1 ; 2.743  ; 2.743  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_IOn       ; CRT_PIN4_CLK1 ; 2.882  ; 2.882  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_MSGn      ; CRT_PIN4_CLK1 ; 2.181  ; 2.181  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RDn       ; CRT_PIN4_CLK1 ; 2.779  ; 2.779  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_REQn      ; CRT_PIN4_CLK1 ; 2.441  ; 2.441  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_RSTn      ; CRT_PIN4_CLK1 ; 2.347  ; 2.347  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_SELn      ; CRT_PIN4_CLK1 ; 2.414  ; 2.414  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SCSI_WRn       ; CRT_PIN4_CLK1 ; 2.760  ; 2.760  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_BOOT_REQ    ; CRT_PIN4_CLK1 ; 3.591  ; 3.591  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SD_SPI_MISO    ; CRT_PIN4_CLK1 ; 3.790  ; 3.790  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_BOOT_REQ   ; CRT_PIN4_CLK1 ; 2.496  ; 2.496  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; SYS_SPI_MISO   ; CRT_PIN4_CLK1 ; 2.856  ; 2.856  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UART_MIDI_RTSn ; CRT_PIN4_CLK1 ; 2.660  ; 2.660  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDATA[*]       ; CRT_PIN4_CLK1 ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[0]      ; CRT_PIN4_CLK1 ; 2.587  ; 2.587  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[1]      ; CRT_PIN4_CLK1 ; 3.042  ; 3.042  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[2]      ; CRT_PIN4_CLK1 ; 2.695  ; 2.695  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  UDATA[3]      ; CRT_PIN4_CLK1 ; 3.034  ; 3.034  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.279  ; 3.279  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VDCLK          ; CRT_PIN4_CLK1 ; 2.671  ; 2.671  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VMAn           ; CRT_PIN4_CLK1 ; 3.133  ; 3.133  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 5.046  ; 5.046  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_A       ; CRT_PIN4_CLK1 ; 3.859  ; 3.859  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_B       ; CRT_PIN4_CLK1 ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; YM_OUT_C       ; CRT_PIN4_CLK1 ; 4.829  ; 4.829  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 3.063  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.448  ; 5.448  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.438  ; 5.438  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 3.457  ; 3.457  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.211  ; 4.211  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.483  ; 4.483  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.289  ; 6.289  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 5.929  ; 5.929  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.985  ; 5.985  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.298  ; 6.298  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 6.158  ; 6.158  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 6.070  ; 6.070  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 6.085  ; 6.085  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.962  ; 5.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 7.411  ; 7.411  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 7.142  ; 7.081  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 6.846  ; 6.846  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 6.961  ; 6.961  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 6.344  ; 6.344  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 7.503  ; 7.503  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 6.189  ; 6.189  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 6.449  ; 6.449  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 6.472  ; 6.370  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 6.863  ; 6.745  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 6.646  ; 6.611  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 7.902  ; 7.902  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 6.362  ; 6.362  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 7.614  ; 7.533  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.835  ; 5.835  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 6.004  ; 6.004  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_18   ; CRT_PIN4_CLK1 ;        ; 4.306  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_ADR_19   ; CRT_PIN4_CLK1 ;        ; 4.013  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.562  ; 5.328  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 6.060  ; 5.826  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 3.763  ; 3.702  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 3.656  ; 3.595  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 3.891  ; 3.830  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 3.671  ; 3.610  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 3.715  ; 3.631  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 3.720  ; 3.641  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 3.663  ; 3.476  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.570  ; 4.363  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.335  ; 4.542  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.116  ; 3.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 3.267  ; 3.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 6.613  ; 6.613  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 6.584  ; 6.584  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 6.305  ; 6.305  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 6.394  ; 6.394  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 7.067  ; 7.067  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 6.065  ; 6.065  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 6.499  ; 6.499  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 5.899  ; 5.899  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.281  ; 4.281  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.935  ; 3.935  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 3.534  ; 3.534  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 3.777  ; 3.777  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 4.179  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 4.183  ; 4.183  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.179  ; 4.768  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 4.278  ; 4.643  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 4.231  ; 3.866  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 5.590  ; 5.590  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 6.227  ; 6.166  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 6.003  ; 6.003  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 6.058  ; 6.058  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 6.473  ; 6.473  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 6.162  ; 6.162  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 6.020  ; 6.020  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 6.131  ; 6.131  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 6.083  ; 5.981  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 6.234  ; 6.116  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 6.783  ; 6.748  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 6.267  ; 6.267  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 6.426  ; 6.426  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 6.465  ; 6.384  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.951  ; 4.951  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.962  ; 4.962  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 4.774  ; 4.505  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 3.904  ; 3.968  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 4.930  ; 4.661  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 3.894  ; 3.958  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 5.071  ; 5.436  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 5.278  ; 4.913  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 4.005  ; 4.005  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.832  ; 4.832  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 4.736  ; 4.502  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.351  ; 4.351  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 4.086  ; 4.086  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.885  ; 4.885  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.431  ; 4.431  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 3.279  ; 3.279  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 3.063  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ;
; ACSI_RDn       ; CLK_PLL1      ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_WRn       ; CLK_PLL1      ; 5.157  ; 5.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ASn            ; CLK_PLL1      ; 4.620  ; 4.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BERRn          ; CLK_PLL1      ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; BUTTONn        ; CLK_PLL1      ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CA1_OUT        ; CLK_PLL1      ; 4.202  ; 4.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CD[*]          ; CLK_PLL1      ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[0]         ; CLK_PLL1      ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[1]         ; CLK_PLL1      ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[2]         ; CLK_PLL1      ; 5.704  ; 5.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[3]         ; CLK_PLL1      ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[4]         ; CLK_PLL1      ; 5.877  ; 5.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[5]         ; CLK_PLL1      ; 5.789  ; 5.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[6]         ; CLK_PLL1      ; 5.804  ; 5.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CD[7]         ; CLK_PLL1      ; 5.681  ; 5.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_B[*]       ; CLK_PLL1      ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[0]      ; CLK_PLL1      ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[1]      ; CLK_PLL1      ; 3.769  ; 3.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[2]      ; CLK_PLL1      ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_B[3]      ; CLK_PLL1      ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_G[*]       ; CLK_PLL1      ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[0]      ; CLK_PLL1      ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[1]      ; CLK_PLL1      ; 3.823  ; 3.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[2]      ; CLK_PLL1      ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_G[3]      ; CLK_PLL1      ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_MONO       ; CLK_PLL1      ; 4.261  ; 4.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; CRT_R[*]       ; CLK_PLL1      ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[0]      ; CLK_PLL1      ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[1]      ; CLK_PLL1      ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[2]      ; CLK_PLL1      ; 3.433  ; 3.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  CRT_R[3]      ; CLK_PLL1      ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_LDACn      ; CLK_PLL1      ; 3.405  ; 3.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SCLK       ; CLK_PLL1      ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DAC_SYNCn      ; CLK_PLL1      ; 2.492  ; 2.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; DATA[*]        ; CLK_PLL1      ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[0]       ; CLK_PLL1      ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[1]       ; CLK_PLL1      ; 5.387  ; 5.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[2]       ; CLK_PLL1      ; 5.803  ; 5.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[3]       ; CLK_PLL1      ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[4]       ; CLK_PLL1      ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[5]       ; CLK_PLL1      ; 6.588  ; 6.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[6]       ; CLK_PLL1      ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[7]       ; CLK_PLL1      ; 5.787  ; 5.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[8]       ; CLK_PLL1      ; 5.337  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[9]       ; CLK_PLL1      ; 5.924  ; 5.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[10]      ; CLK_PLL1      ; 5.670  ; 5.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[11]      ; CLK_PLL1      ; 6.704  ; 6.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[12]      ; CLK_PLL1      ; 5.288  ; 5.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[13]      ; CLK_PLL1      ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[14]      ; CLK_PLL1      ; 5.211  ; 5.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  DATA[15]      ; CLK_PLL1      ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FCLK           ; CLK_PLL1      ; 2.535  ; 2.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_CEn      ; CLK_PLL1      ; 5.828  ; 5.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; FLASH_OEn      ; CLK_PLL1      ; 6.326  ; 6.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; HSYNC          ; CLK_PLL1      ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS0n       ; CLK_PLL1      ; 3.870  ; 3.870  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_CS1n       ; CLK_PLL1      ; 3.907  ; 3.907  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_INn   ; CLK_PLL1      ; 4.225  ; 4.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_D_EN_OUTn  ; CLK_PLL1      ; 4.005  ; 4.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IORDn      ; CLK_PLL1      ; 4.049  ; 4.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; IDE_IOWRn      ; CLK_PLL1      ; 4.054  ; 4.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RHn        ; CLK_PLL1      ; 3.802  ; 3.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_RLn        ; CLK_PLL1      ; 4.719  ; 4.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WEn        ; CLK_PLL1      ; 4.691  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; JOY_WL         ; CLK_PLL1      ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; LDSn           ; CLK_PLL1      ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWD            ; CLK_PLL1      ; 2.405  ; 2.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWEn           ; CLK_PLL1      ; 2.182  ; 2.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; MWK            ; CLK_PLL1      ; 2.219  ; 2.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; PADRSTn        ; CLK_PLL1      ; 2.538  ; 2.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_ADR[*]     ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[0]    ; CLK_PLL1      ; 4.029  ; 4.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[1]    ; CLK_PLL1      ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[2]    ; CLK_PLL1      ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[3]    ; CLK_PLL1      ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[4]    ; CLK_PLL1      ; 4.600  ; 4.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[5]    ; CLK_PLL1      ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[6]    ; CLK_PLL1      ; 4.253  ; 4.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[7]    ; CLK_PLL1      ; 4.419  ; 4.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[8]    ; CLK_PLL1      ; 4.201  ; 4.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[9]    ; CLK_PLL1      ; 4.104  ; 4.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[10]   ; CLK_PLL1      ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[11]   ; CLK_PLL1      ; 4.137  ; 4.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_ADR[12]   ; CLK_PLL1      ; 4.075  ; 4.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_BA[*]      ; CLK_PLL1      ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[0]     ; CLK_PLL1      ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_BA[1]     ; CLK_PLL1      ; 4.479  ; 4.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS0n      ; CLK_PLL1      ; 3.597  ; 3.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CAS1n      ; CLK_PLL1      ; 3.183  ; 3.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DATA[*]    ; CLK_PLL1      ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[0]   ; CLK_PLL1      ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[1]   ; CLK_PLL1      ; 4.472  ; 4.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[2]   ; CLK_PLL1      ; 4.960  ; 4.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[3]   ; CLK_PLL1      ; 5.057  ; 5.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[4]   ; CLK_PLL1      ; 5.481  ; 5.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[5]   ; CLK_PLL1      ; 5.247  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[6]   ; CLK_PLL1      ; 4.866  ; 4.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[7]   ; CLK_PLL1      ; 5.469  ; 5.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[8]   ; CLK_PLL1      ; 4.948  ; 4.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[9]   ; CLK_PLL1      ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[10]  ; CLK_PLL1      ; 5.807  ; 5.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[11]  ; CLK_PLL1      ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[12]  ; CLK_PLL1      ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[13]  ; CLK_PLL1      ; 5.086  ; 5.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[14]  ; CLK_PLL1      ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  RAM_DATA[15]  ; CLK_PLL1      ; 4.572  ; 4.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0H      ; CLK_PLL1      ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM0L      ; CLK_PLL1      ; 4.523  ; 4.523  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1H      ; CLK_PLL1      ; 5.280  ; 5.280  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_DQM1L      ; CLK_PLL1      ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS0n      ; CLK_PLL1      ; 3.454  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_RAS1n      ; CLK_PLL1      ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_WEn        ; CLK_PLL1      ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RESETn         ; CLK_PLL1      ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM0n          ; CLK_PLL1      ; 3.737  ; 3.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM1n          ; CLK_PLL1      ; 4.569  ; 4.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM2n          ; CLK_PLL1      ; 5.002  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM3n          ; CLK_PLL1      ; 4.165  ; 4.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM4n          ; CLK_PLL1      ; 3.901  ; 3.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM5n          ; CLK_PLL1      ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ROM6n          ; CLK_PLL1      ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; UDSn           ; CLK_PLL1      ; 4.798  ; 4.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; VSYNC          ; CLK_PLL1      ; 3.188  ; 3.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; RAM_CLK        ; CLK_PLL1      ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; xFF827E_D[*]   ; CLK_PLL1      ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
;  xFF827E_D[2]  ; CLK_PLL1      ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ;
; ACSI_RDn       ; CRT_PIN4_CLK1 ; 5.167  ; 5.167  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ACSI_WRn       ; CRT_PIN4_CLK1 ; 5.157  ; 5.157  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ASn            ; CRT_PIN4_CLK1 ; 4.620  ; 4.620  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BERRn          ; CRT_PIN4_CLK1 ; 2.942  ; 2.942  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; BUTTONn        ; CRT_PIN4_CLK1 ; 4.010  ; 4.010  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CA1_OUT        ; CRT_PIN4_CLK1 ; 4.202  ; 4.202  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CD[*]          ; CRT_PIN4_CLK1 ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[0]         ; CRT_PIN4_CLK1 ; 6.008  ; 6.008  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[1]         ; CRT_PIN4_CLK1 ; 5.648  ; 5.648  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[2]         ; CRT_PIN4_CLK1 ; 5.704  ; 5.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[3]         ; CRT_PIN4_CLK1 ; 6.017  ; 6.017  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[4]         ; CRT_PIN4_CLK1 ; 5.877  ; 5.877  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[5]         ; CRT_PIN4_CLK1 ; 5.789  ; 5.789  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[6]         ; CRT_PIN4_CLK1 ; 5.804  ; 5.804  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CD[7]         ; CRT_PIN4_CLK1 ; 5.681  ; 5.681  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_B[*]       ; CRT_PIN4_CLK1 ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[0]      ; CRT_PIN4_CLK1 ; 3.706  ; 3.706  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[1]      ; CRT_PIN4_CLK1 ; 3.769  ; 3.769  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[2]      ; CRT_PIN4_CLK1 ; 3.563  ; 3.563  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_B[3]      ; CRT_PIN4_CLK1 ; 3.661  ; 3.661  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_G[*]       ; CRT_PIN4_CLK1 ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[0]      ; CRT_PIN4_CLK1 ; 3.705  ; 3.705  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[1]      ; CRT_PIN4_CLK1 ; 3.823  ; 3.823  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[2]      ; CRT_PIN4_CLK1 ; 3.475  ; 3.475  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_G[3]      ; CRT_PIN4_CLK1 ; 3.612  ; 3.612  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_MONO       ; CRT_PIN4_CLK1 ; 4.261  ; 4.261  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CRT_R[*]       ; CRT_PIN4_CLK1 ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[0]      ; CRT_PIN4_CLK1 ; 3.317  ; 3.317  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[1]      ; CRT_PIN4_CLK1 ; 3.914  ; 3.914  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[2]      ; CRT_PIN4_CLK1 ; 3.433  ; 3.433  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  CRT_R[3]      ; CRT_PIN4_CLK1 ; 3.622  ; 3.622  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_LDACn      ; CRT_PIN4_CLK1 ; 3.405  ; 3.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SCLK       ; CRT_PIN4_CLK1 ; 3.865  ; 3.865  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DAC_SYNCn      ; CRT_PIN4_CLK1 ; 2.492  ; 2.492  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; DATA[*]        ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[0]       ; CRT_PIN4_CLK1 ; 6.568  ; 6.568  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[1]       ; CRT_PIN4_CLK1 ; 5.387  ; 5.387  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[2]       ; CRT_PIN4_CLK1 ; 5.803  ; 5.803  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[3]       ; CRT_PIN4_CLK1 ; 5.960  ; 5.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[4]       ; CRT_PIN4_CLK1 ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[5]       ; CRT_PIN4_CLK1 ; 6.588  ; 6.588  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[6]       ; CRT_PIN4_CLK1 ; 5.035  ; 5.035  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[7]       ; CRT_PIN4_CLK1 ; 5.787  ; 5.787  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[8]       ; CRT_PIN4_CLK1 ; 5.337  ; 5.337  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[9]       ; CRT_PIN4_CLK1 ; 5.924  ; 5.924  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[10]      ; CRT_PIN4_CLK1 ; 5.670  ; 5.670  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[11]      ; CRT_PIN4_CLK1 ; 6.704  ; 6.704  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[12]      ; CRT_PIN4_CLK1 ; 5.288  ; 5.288  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[13]      ; CRT_PIN4_CLK1 ; 6.235  ; 6.235  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[14]      ; CRT_PIN4_CLK1 ; 5.211  ; 5.211  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  DATA[15]      ; CRT_PIN4_CLK1 ; 5.614  ; 5.614  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FCLK           ; CRT_PIN4_CLK1 ; 2.535  ; 2.535  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_CEn      ; CRT_PIN4_CLK1 ; 5.828  ; 5.828  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; FLASH_OEn      ; CRT_PIN4_CLK1 ; 6.326  ; 6.326  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; HSYNC          ; CRT_PIN4_CLK1 ; 3.103  ; 3.103  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS0n       ; CRT_PIN4_CLK1 ; 3.870  ; 3.870  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_CS1n       ; CRT_PIN4_CLK1 ; 3.907  ; 3.907  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_INn   ; CRT_PIN4_CLK1 ; 4.225  ; 4.225  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_D_EN_OUTn  ; CRT_PIN4_CLK1 ; 4.005  ; 4.005  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IORDn      ; CRT_PIN4_CLK1 ; 4.049  ; 4.049  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; IDE_IOWRn      ; CRT_PIN4_CLK1 ; 4.054  ; 4.054  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RHn        ; CRT_PIN4_CLK1 ; 3.802  ; 3.802  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_RLn        ; CRT_PIN4_CLK1 ; 4.719  ; 4.719  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WEn        ; CRT_PIN4_CLK1 ; 4.691  ; 4.691  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; JOY_WL         ; CRT_PIN4_CLK1 ; 3.468  ; 3.468  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; LDSn           ; CRT_PIN4_CLK1 ; 4.786  ; 4.786  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWD            ; CRT_PIN4_CLK1 ; 2.405  ; 2.405  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWEn           ; CRT_PIN4_CLK1 ; 2.182  ; 2.182  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; MWK            ; CRT_PIN4_CLK1 ; 2.219  ; 2.219  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; PADRSTn        ; CRT_PIN4_CLK1 ; 2.538  ; 2.538  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_ADR[*]     ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[0]    ; CRT_PIN4_CLK1 ; 4.029  ; 4.029  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[1]    ; CRT_PIN4_CLK1 ; 3.562  ; 3.562  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[2]    ; CRT_PIN4_CLK1 ; 4.019  ; 4.019  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[3]    ; CRT_PIN4_CLK1 ; 3.663  ; 3.663  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[4]    ; CRT_PIN4_CLK1 ; 4.600  ; 4.600  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[5]    ; CRT_PIN4_CLK1 ; 4.147  ; 4.147  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[6]    ; CRT_PIN4_CLK1 ; 4.253  ; 4.253  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[7]    ; CRT_PIN4_CLK1 ; 4.419  ; 4.419  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[8]    ; CRT_PIN4_CLK1 ; 4.201  ; 4.201  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[9]    ; CRT_PIN4_CLK1 ; 4.104  ; 4.104  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[10]   ; CRT_PIN4_CLK1 ; 3.812  ; 3.812  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[11]   ; CRT_PIN4_CLK1 ; 4.137  ; 4.137  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_ADR[12]   ; CRT_PIN4_CLK1 ; 4.075  ; 4.075  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_BA[*]      ; CRT_PIN4_CLK1 ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[0]     ; CRT_PIN4_CLK1 ; 3.662  ; 3.662  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_BA[1]     ; CRT_PIN4_CLK1 ; 4.479  ; 4.479  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS0n      ; CRT_PIN4_CLK1 ; 3.597  ; 3.597  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CAS1n      ; CRT_PIN4_CLK1 ; 3.183  ; 3.183  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ; 0.124  ;        ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DATA[*]    ; CRT_PIN4_CLK1 ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[0]   ; CRT_PIN4_CLK1 ; 4.747  ; 4.747  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[1]   ; CRT_PIN4_CLK1 ; 4.472  ; 4.472  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[2]   ; CRT_PIN4_CLK1 ; 4.960  ; 4.960  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[3]   ; CRT_PIN4_CLK1 ; 5.057  ; 5.057  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[4]   ; CRT_PIN4_CLK1 ; 5.481  ; 5.481  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[5]   ; CRT_PIN4_CLK1 ; 5.247  ; 5.247  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[6]   ; CRT_PIN4_CLK1 ; 4.866  ; 4.866  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[7]   ; CRT_PIN4_CLK1 ; 5.469  ; 5.469  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[8]   ; CRT_PIN4_CLK1 ; 4.948  ; 4.948  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[9]   ; CRT_PIN4_CLK1 ; 5.295  ; 5.295  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[10]  ; CRT_PIN4_CLK1 ; 5.807  ; 5.807  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[11]  ; CRT_PIN4_CLK1 ; 5.069  ; 5.069  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[12]  ; CRT_PIN4_CLK1 ; 5.352  ; 5.352  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[13]  ; CRT_PIN4_CLK1 ; 5.086  ; 5.086  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[14]  ; CRT_PIN4_CLK1 ; 4.327  ; 4.327  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  RAM_DATA[15]  ; CRT_PIN4_CLK1 ; 4.572  ; 4.572  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0H      ; CRT_PIN4_CLK1 ; 5.124  ; 5.124  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM0L      ; CRT_PIN4_CLK1 ; 4.523  ; 4.523  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1H      ; CRT_PIN4_CLK1 ; 5.280  ; 5.280  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_DQM1L      ; CRT_PIN4_CLK1 ; 4.513  ; 4.513  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS0n      ; CRT_PIN4_CLK1 ; 3.454  ; 3.454  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_RAS1n      ; CRT_PIN4_CLK1 ; 3.296  ; 3.296  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_WEn        ; CRT_PIN4_CLK1 ; 3.645  ; 3.645  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RESETn         ; CRT_PIN4_CLK1 ; 2.943  ; 2.943  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM0n          ; CRT_PIN4_CLK1 ; 3.737  ; 3.737  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM1n          ; CRT_PIN4_CLK1 ; 4.569  ; 4.569  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM2n          ; CRT_PIN4_CLK1 ; 5.002  ; 5.002  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM3n          ; CRT_PIN4_CLK1 ; 4.165  ; 4.165  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM4n          ; CRT_PIN4_CLK1 ; 3.901  ; 3.901  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM5n          ; CRT_PIN4_CLK1 ; 4.500  ; 4.500  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; ROM6n          ; CRT_PIN4_CLK1 ; 4.246  ; 4.246  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; UDSn           ; CRT_PIN4_CLK1 ; 4.798  ; 4.798  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; VSYNC          ; CRT_PIN4_CLK1 ; 3.188  ; 3.188  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ; 3.579  ; 3.594  ; Rise       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; RAM_CLK        ; CRT_PIN4_CLK1 ;        ; 0.124  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; xFF827E_D[*]   ; CRT_PIN4_CLK1 ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
;  xFF827E_D[2]  ; CRT_PIN4_CLK1 ;        ; 3.579  ; Fall       ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ;
; CLK_AUX        ; CLK_PLL2      ; 1.223  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_B[*]       ; CLK_PLL2      ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[0]      ; CLK_PLL2      ; 5.507  ; 5.507  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[1]      ; CLK_PLL2      ; 6.280  ; 6.280  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[2]      ; CLK_PLL2      ; 5.334  ; 5.334  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_B[3]      ; CLK_PLL2      ; 6.402  ; 6.402  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_G[*]       ; CLK_PLL2      ; 5.151  ; 5.151  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[0]      ; CLK_PLL2      ; 5.661  ; 5.661  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[1]      ; CLK_PLL2      ; 5.894  ; 5.894  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[2]      ; CLK_PLL2      ; 5.265  ; 5.265  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_G[3]      ; CLK_PLL2      ; 5.151  ; 5.151  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_MONO       ; CLK_PLL2      ; 6.196  ; 6.196  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CRT_R[*]       ; CLK_PLL2      ; 5.775  ; 5.775  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[0]      ; CLK_PLL2      ; 5.775  ; 5.775  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[1]      ; CLK_PLL2      ; 5.883  ; 5.883  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[2]      ; CLK_PLL2      ; 6.055  ; 6.055  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  CRT_R[3]      ; CLK_PLL2      ; 6.146  ; 6.146  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_LDACn      ; CLK_PLL2      ; 2.759  ; 2.759  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ; 2.686  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DATA[*]        ; CLK_PLL2      ; 8.756  ; 8.756  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[0]       ; CLK_PLL2      ; 10.107 ; 10.107 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[1]       ; CLK_PLL2      ; 9.663  ; 9.663  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[2]       ; CLK_PLL2      ; 8.913  ; 8.913  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[3]       ; CLK_PLL2      ; 9.284  ; 9.284  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[4]       ; CLK_PLL2      ; 8.756  ; 8.756  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[5]       ; CLK_PLL2      ; 10.114 ; 10.114 ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[6]       ; CLK_PLL2      ; 8.954  ; 8.954  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[7]       ; CLK_PLL2      ; 9.458  ; 9.458  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[8]       ; CLK_PLL2      ; 9.150  ; 9.150  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[9]       ; CLK_PLL2      ; 9.866  ; 9.866  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  DATA[10]      ; CLK_PLL2      ; 9.451  ; 9.451  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; HSYNC          ; CLK_PLL2      ; 6.256  ; 6.256  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; RAM_DATA[*]    ; CLK_PLL2      ; 8.070  ; 8.070  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[0]   ; CLK_PLL2      ; 8.286  ; 8.286  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[1]   ; CLK_PLL2      ; 8.748  ; 8.748  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[2]   ; CLK_PLL2      ; 8.070  ; 8.070  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[3]   ; CLK_PLL2      ; 8.381  ; 8.381  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[4]   ; CLK_PLL2      ; 8.885  ; 8.885  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[5]   ; CLK_PLL2      ; 8.773  ; 8.773  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[6]   ; CLK_PLL2      ; 8.785  ; 8.785  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[7]   ; CLK_PLL2      ; 9.140  ; 9.140  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[8]   ; CLK_PLL2      ; 8.761  ; 8.761  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[9]   ; CLK_PLL2      ; 9.237  ; 9.237  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  RAM_DATA[10]  ; CLK_PLL2      ; 9.588  ; 9.588  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; VSYNC          ; CLK_PLL2      ; 5.424  ; 5.424  ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ; 3.441  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ; 3.441  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; CLK_AUX        ; CLK_PLL2      ;        ; 1.223  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; DAC_SCLK       ; CLK_PLL2      ;        ; 2.686  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; xFF827E_D[*]   ; CLK_PLL2      ;        ; 3.441  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
;  xFF827E_D[2]  ; CLK_PLL2      ;        ; 3.441  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ;
; SD_AVR_CLK     ; CLK_PLL2      ; 0.141  ;        ; Rise       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
; SD_AVR_CLK     ; CLK_PLL2      ;        ; 0.141  ; Fall       ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ;
+----------------+---------------+--------+--------+------------+------------------------------------------------------------+


+------------------------------------------------------------------+
; Progagation Delay                                                ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ADR[1]       ; DATA[0]       ; 31.407 ; 31.407 ; 31.407 ; 31.407 ;
; ADR[1]       ; DATA[1]       ; 30.877 ; 30.877 ; 30.877 ; 30.877 ;
; ADR[1]       ; DATA[2]       ; 29.779 ; 29.779 ; 29.779 ; 29.779 ;
; ADR[1]       ; DATA[3]       ; 32.365 ; 32.365 ; 32.365 ; 32.365 ;
; ADR[1]       ; DATA[4]       ; 28.591 ; 28.591 ; 28.591 ; 28.591 ;
; ADR[1]       ; DATA[5]       ; 30.699 ; 30.699 ; 30.699 ; 30.699 ;
; ADR[1]       ; DATA[6]       ; 28.327 ; 28.327 ; 28.327 ; 28.327 ;
; ADR[1]       ; DATA[7]       ; 30.772 ; 30.772 ; 30.772 ; 30.772 ;
; ADR[1]       ; DATA[8]       ; 29.631 ; 29.631 ; 29.631 ; 29.631 ;
; ADR[1]       ; DATA[9]       ; 30.410 ; 30.410 ; 30.410 ; 30.410 ;
; ADR[1]       ; DATA[10]      ; 30.492 ; 30.492 ; 30.492 ; 30.492 ;
; ADR[1]       ; DATA[11]      ; 32.288 ; 32.288 ; 32.288 ; 32.288 ;
; ADR[1]       ; DATA[12]      ; 30.877 ; 30.877 ; 30.877 ; 30.877 ;
; ADR[1]       ; DATA[13]      ; 31.352 ; 31.352 ; 31.352 ; 31.352 ;
; ADR[1]       ; DATA[14]      ; 30.772 ; 30.772 ; 30.772 ; 30.772 ;
; ADR[1]       ; DATA[15]      ; 31.497 ; 31.497 ; 31.497 ; 31.497 ;
; ADR[1]       ; RAM_DATA[0]   ; 26.796 ; 26.796 ; 26.796 ; 26.796 ;
; ADR[1]       ; RAM_DATA[1]   ; 28.934 ; 28.934 ; 28.934 ; 28.934 ;
; ADR[1]       ; RAM_DATA[2]   ; 27.491 ; 27.491 ; 27.491 ; 27.491 ;
; ADR[1]       ; RAM_DATA[3]   ; 29.889 ; 29.889 ; 29.889 ; 29.889 ;
; ADR[1]       ; RAM_DATA[4]   ; 29.147 ; 29.147 ; 29.147 ; 29.147 ;
; ADR[1]       ; RAM_DATA[5]   ; 27.337 ; 27.337 ; 27.337 ; 27.337 ;
; ADR[1]       ; RAM_DATA[6]   ; 27.851 ; 27.851 ; 27.851 ; 27.851 ;
; ADR[1]       ; RAM_DATA[7]   ; 29.707 ; 29.707 ; 29.707 ; 29.707 ;
; ADR[1]       ; RAM_DATA[8]   ; 28.270 ; 28.270 ; 28.270 ; 28.270 ;
; ADR[1]       ; RAM_DATA[9]   ; 28.544 ; 28.544 ; 28.544 ; 28.544 ;
; ADR[1]       ; RAM_DATA[10]  ; 30.221 ; 30.221 ; 30.221 ; 30.221 ;
; ADR[1]       ; RAM_DATA[11]  ; 28.076 ; 28.076 ; 28.076 ; 28.076 ;
; ADR[1]       ; RAM_DATA[12]  ; 30.696 ; 30.696 ; 30.696 ; 30.696 ;
; ADR[1]       ; RAM_DATA[13]  ; 28.042 ; 28.042 ; 28.042 ; 28.042 ;
; ADR[1]       ; RAM_DATA[14]  ; 28.196 ; 28.196 ; 28.196 ; 28.196 ;
; ADR[1]       ; RAM_DATA[15]  ; 28.473 ; 28.473 ; 28.473 ; 28.473 ;
; ADR[2]       ; DATA[0]       ; 32.342 ; 32.366 ; 32.366 ; 32.342 ;
; ADR[2]       ; DATA[1]       ; 31.812 ; 31.835 ; 31.835 ; 31.812 ;
; ADR[2]       ; DATA[2]       ; 30.714 ; 30.753 ; 30.753 ; 30.714 ;
; ADR[2]       ; DATA[3]       ; 33.595 ; 33.595 ; 33.595 ; 33.595 ;
; ADR[2]       ; DATA[4]       ; 29.821 ; 29.821 ; 29.821 ; 29.821 ;
; ADR[2]       ; DATA[5]       ; 31.929 ; 31.929 ; 31.929 ; 31.929 ;
; ADR[2]       ; DATA[6]       ; 29.462 ; 29.462 ; 29.462 ; 29.462 ;
; ADR[2]       ; DATA[7]       ; 32.002 ; 32.002 ; 32.002 ; 32.002 ;
; ADR[2]       ; DATA[8]       ; 30.566 ; 30.590 ; 30.590 ; 30.566 ;
; ADR[2]       ; DATA[9]       ; 31.345 ; 31.368 ; 31.368 ; 31.345 ;
; ADR[2]       ; DATA[10]      ; 31.427 ; 31.466 ; 31.466 ; 31.427 ;
; ADR[2]       ; DATA[11]      ; 33.518 ; 33.518 ; 33.518 ; 33.518 ;
; ADR[2]       ; DATA[12]      ; 32.107 ; 32.107 ; 32.107 ; 32.107 ;
; ADR[2]       ; DATA[13]      ; 32.582 ; 32.582 ; 32.582 ; 32.582 ;
; ADR[2]       ; DATA[14]      ; 32.002 ; 32.002 ; 32.002 ; 32.002 ;
; ADR[2]       ; DATA[15]      ; 32.727 ; 32.727 ; 32.727 ; 32.727 ;
; ADR[2]       ; RAM_DATA[0]   ; 27.731 ; 27.755 ; 27.755 ; 27.731 ;
; ADR[2]       ; RAM_DATA[1]   ; 29.869 ; 29.892 ; 29.892 ; 29.869 ;
; ADR[2]       ; RAM_DATA[2]   ; 28.426 ; 28.465 ; 28.465 ; 28.426 ;
; ADR[2]       ; RAM_DATA[3]   ; 31.119 ; 31.119 ; 31.119 ; 31.119 ;
; ADR[2]       ; RAM_DATA[4]   ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; ADR[2]       ; RAM_DATA[5]   ; 28.567 ; 28.567 ; 28.567 ; 28.567 ;
; ADR[2]       ; RAM_DATA[6]   ; 28.986 ; 28.986 ; 28.986 ; 28.986 ;
; ADR[2]       ; RAM_DATA[7]   ; 30.937 ; 30.937 ; 30.937 ; 30.937 ;
; ADR[2]       ; RAM_DATA[8]   ; 29.205 ; 29.229 ; 29.229 ; 29.205 ;
; ADR[2]       ; RAM_DATA[9]   ; 29.479 ; 29.502 ; 29.502 ; 29.479 ;
; ADR[2]       ; RAM_DATA[10]  ; 31.156 ; 31.195 ; 31.195 ; 31.156 ;
; ADR[2]       ; RAM_DATA[11]  ; 29.306 ; 29.306 ; 29.306 ; 29.306 ;
; ADR[2]       ; RAM_DATA[12]  ; 31.926 ; 31.926 ; 31.926 ; 31.926 ;
; ADR[2]       ; RAM_DATA[13]  ; 29.272 ; 29.272 ; 29.272 ; 29.272 ;
; ADR[2]       ; RAM_DATA[14]  ; 29.426 ; 29.426 ; 29.426 ; 29.426 ;
; ADR[2]       ; RAM_DATA[15]  ; 29.703 ; 29.703 ; 29.703 ; 29.703 ;
; ADR[3]       ; DATA[0]       ; 31.248 ; 30.977 ; 30.977 ; 31.248 ;
; ADR[3]       ; DATA[1]       ; 30.717 ; 30.447 ; 30.447 ; 30.717 ;
; ADR[3]       ; DATA[2]       ; 29.620 ; 29.349 ; 29.349 ; 29.620 ;
; ADR[3]       ; DATA[3]       ; 31.875 ; 31.875 ; 31.875 ; 31.875 ;
; ADR[3]       ; DATA[4]       ; 28.101 ; 28.101 ; 28.101 ; 28.101 ;
; ADR[3]       ; DATA[5]       ; 30.321 ; 30.321 ; 30.321 ; 30.321 ;
; ADR[3]       ; DATA[6]       ; 28.284 ; 28.284 ; 28.284 ; 28.284 ;
; ADR[3]       ; DATA[7]       ; 30.282 ; 30.282 ; 30.282 ; 30.282 ;
; ADR[3]       ; DATA[8]       ; 29.472 ; 29.201 ; 29.201 ; 29.472 ;
; ADR[3]       ; DATA[9]       ; 30.250 ; 29.980 ; 29.980 ; 30.250 ;
; ADR[3]       ; DATA[10]      ; 30.333 ; 30.062 ; 30.062 ; 30.333 ;
; ADR[3]       ; DATA[11]      ; 31.798 ; 31.798 ; 31.798 ; 31.798 ;
; ADR[3]       ; DATA[12]      ; 30.387 ; 30.387 ; 30.387 ; 30.387 ;
; ADR[3]       ; DATA[13]      ; 30.862 ; 30.862 ; 30.862 ; 30.862 ;
; ADR[3]       ; DATA[14]      ; 30.282 ; 30.282 ; 30.282 ; 30.282 ;
; ADR[3]       ; DATA[15]      ; 31.007 ; 31.007 ; 31.007 ; 31.007 ;
; ADR[3]       ; RAM_DATA[0]   ; 26.637 ; 26.366 ; 26.366 ; 26.637 ;
; ADR[3]       ; RAM_DATA[1]   ; 28.774 ; 28.504 ; 28.504 ; 28.774 ;
; ADR[3]       ; RAM_DATA[2]   ; 27.332 ; 27.061 ; 27.061 ; 27.332 ;
; ADR[3]       ; RAM_DATA[3]   ; 29.399 ; 29.399 ; 29.399 ; 29.399 ;
; ADR[3]       ; RAM_DATA[4]   ; 28.657 ; 28.657 ; 28.657 ; 28.657 ;
; ADR[3]       ; RAM_DATA[5]   ; 26.959 ; 26.959 ; 26.959 ; 26.959 ;
; ADR[3]       ; RAM_DATA[6]   ; 27.808 ; 27.808 ; 27.808 ; 27.808 ;
; ADR[3]       ; RAM_DATA[7]   ; 29.217 ; 29.217 ; 29.217 ; 29.217 ;
; ADR[3]       ; RAM_DATA[8]   ; 28.111 ; 27.840 ; 27.840 ; 28.111 ;
; ADR[3]       ; RAM_DATA[9]   ; 28.384 ; 28.114 ; 28.114 ; 28.384 ;
; ADR[3]       ; RAM_DATA[10]  ; 30.062 ; 29.791 ; 29.791 ; 30.062 ;
; ADR[3]       ; RAM_DATA[11]  ; 27.586 ; 27.586 ; 27.586 ; 27.586 ;
; ADR[3]       ; RAM_DATA[12]  ; 30.206 ; 30.206 ; 30.206 ; 30.206 ;
; ADR[3]       ; RAM_DATA[13]  ; 27.552 ; 27.552 ; 27.552 ; 27.552 ;
; ADR[3]       ; RAM_DATA[14]  ; 27.706 ; 27.706 ; 27.706 ; 27.706 ;
; ADR[3]       ; RAM_DATA[15]  ; 27.983 ; 27.983 ; 27.983 ; 27.983 ;
; ADR[4]       ; DATA[0]       ; 31.400 ; 31.400 ; 31.400 ; 31.400 ;
; ADR[4]       ; DATA[1]       ; 30.870 ; 30.870 ; 30.870 ; 30.870 ;
; ADR[4]       ; DATA[2]       ; 29.772 ; 29.772 ; 29.772 ; 29.772 ;
; ADR[4]       ; DATA[3]       ; 32.481 ; 32.481 ; 32.481 ; 32.481 ;
; ADR[4]       ; DATA[4]       ; 28.707 ; 28.707 ; 28.707 ; 28.707 ;
; ADR[4]       ; DATA[5]       ; 30.815 ; 30.815 ; 30.815 ; 30.815 ;
; ADR[4]       ; DATA[6]       ; 28.348 ; 28.348 ; 28.348 ; 28.348 ;
; ADR[4]       ; DATA[7]       ; 30.888 ; 30.888 ; 30.888 ; 30.888 ;
; ADR[4]       ; DATA[8]       ; 29.624 ; 29.624 ; 29.624 ; 29.624 ;
; ADR[4]       ; DATA[9]       ; 30.403 ; 30.403 ; 30.403 ; 30.403 ;
; ADR[4]       ; DATA[10]      ; 30.485 ; 30.485 ; 30.485 ; 30.485 ;
; ADR[4]       ; DATA[11]      ; 32.404 ; 32.404 ; 32.404 ; 32.404 ;
; ADR[4]       ; DATA[12]      ; 30.993 ; 30.993 ; 30.993 ; 30.993 ;
; ADR[4]       ; DATA[13]      ; 31.468 ; 31.468 ; 31.468 ; 31.468 ;
; ADR[4]       ; DATA[14]      ; 30.888 ; 30.888 ; 30.888 ; 30.888 ;
; ADR[4]       ; DATA[15]      ; 31.613 ; 31.613 ; 31.613 ; 31.613 ;
; ADR[4]       ; RAM_DATA[0]   ; 26.789 ; 26.789 ; 26.789 ; 26.789 ;
; ADR[4]       ; RAM_DATA[1]   ; 28.927 ; 28.927 ; 28.927 ; 28.927 ;
; ADR[4]       ; RAM_DATA[2]   ; 27.484 ; 27.484 ; 27.484 ; 27.484 ;
; ADR[4]       ; RAM_DATA[3]   ; 30.005 ; 30.005 ; 30.005 ; 30.005 ;
; ADR[4]       ; RAM_DATA[4]   ; 29.263 ; 29.263 ; 29.263 ; 29.263 ;
; ADR[4]       ; RAM_DATA[5]   ; 27.453 ; 27.453 ; 27.453 ; 27.453 ;
; ADR[4]       ; RAM_DATA[6]   ; 27.872 ; 27.872 ; 27.872 ; 27.872 ;
; ADR[4]       ; RAM_DATA[7]   ; 29.823 ; 29.823 ; 29.823 ; 29.823 ;
; ADR[4]       ; RAM_DATA[8]   ; 28.263 ; 28.263 ; 28.263 ; 28.263 ;
; ADR[4]       ; RAM_DATA[9]   ; 28.537 ; 28.537 ; 28.537 ; 28.537 ;
; ADR[4]       ; RAM_DATA[10]  ; 30.214 ; 30.214 ; 30.214 ; 30.214 ;
; ADR[4]       ; RAM_DATA[11]  ; 28.192 ; 28.192 ; 28.192 ; 28.192 ;
; ADR[4]       ; RAM_DATA[12]  ; 30.812 ; 30.812 ; 30.812 ; 30.812 ;
; ADR[4]       ; RAM_DATA[13]  ; 28.158 ; 28.158 ; 28.158 ; 28.158 ;
; ADR[4]       ; RAM_DATA[14]  ; 28.312 ; 28.312 ; 28.312 ; 28.312 ;
; ADR[4]       ; RAM_DATA[15]  ; 28.589 ; 28.589 ; 28.589 ; 28.589 ;
; ADR[5]       ; DATA[0]       ; 31.719 ; 31.505 ; 31.505 ; 31.719 ;
; ADR[5]       ; DATA[1]       ; 31.188 ; 30.975 ; 30.975 ; 31.188 ;
; ADR[5]       ; DATA[2]       ; 30.310 ; 29.877 ; 29.877 ; 30.310 ;
; ADR[5]       ; DATA[3]       ; 32.948 ; 32.948 ; 32.948 ; 32.948 ;
; ADR[5]       ; DATA[4]       ; 29.174 ; 29.174 ; 29.174 ; 29.174 ;
; ADR[5]       ; DATA[5]       ; 31.282 ; 31.282 ; 31.282 ; 31.282 ;
; ADR[5]       ; DATA[6]       ; 28.815 ; 28.815 ; 28.815 ; 28.815 ;
; ADR[5]       ; DATA[7]       ; 31.355 ; 31.355 ; 31.355 ; 31.355 ;
; ADR[5]       ; DATA[8]       ; 29.943 ; 29.729 ; 29.729 ; 29.943 ;
; ADR[5]       ; DATA[9]       ; 30.721 ; 30.508 ; 30.508 ; 30.721 ;
; ADR[5]       ; DATA[10]      ; 31.023 ; 30.590 ; 30.590 ; 31.023 ;
; ADR[5]       ; DATA[11]      ; 32.871 ; 32.871 ; 32.871 ; 32.871 ;
; ADR[5]       ; DATA[12]      ; 31.460 ; 31.460 ; 31.460 ; 31.460 ;
; ADR[5]       ; DATA[13]      ; 31.935 ; 31.935 ; 31.935 ; 31.935 ;
; ADR[5]       ; DATA[14]      ; 31.355 ; 31.355 ; 31.355 ; 31.355 ;
; ADR[5]       ; DATA[15]      ; 32.080 ; 32.080 ; 32.080 ; 32.080 ;
; ADR[5]       ; RAM_DATA[0]   ; 27.108 ; 26.894 ; 26.894 ; 27.108 ;
; ADR[5]       ; RAM_DATA[1]   ; 29.245 ; 29.032 ; 29.032 ; 29.245 ;
; ADR[5]       ; RAM_DATA[2]   ; 28.022 ; 27.589 ; 27.589 ; 28.022 ;
; ADR[5]       ; RAM_DATA[3]   ; 30.472 ; 30.472 ; 30.472 ; 30.472 ;
; ADR[5]       ; RAM_DATA[4]   ; 29.730 ; 29.730 ; 29.730 ; 29.730 ;
; ADR[5]       ; RAM_DATA[5]   ; 27.920 ; 27.920 ; 27.920 ; 27.920 ;
; ADR[5]       ; RAM_DATA[6]   ; 28.339 ; 28.339 ; 28.339 ; 28.339 ;
; ADR[5]       ; RAM_DATA[7]   ; 30.290 ; 30.290 ; 30.290 ; 30.290 ;
; ADR[5]       ; RAM_DATA[8]   ; 28.582 ; 28.368 ; 28.368 ; 28.582 ;
; ADR[5]       ; RAM_DATA[9]   ; 28.855 ; 28.642 ; 28.642 ; 28.855 ;
; ADR[5]       ; RAM_DATA[10]  ; 30.752 ; 30.319 ; 30.319 ; 30.752 ;
; ADR[5]       ; RAM_DATA[11]  ; 28.659 ; 28.659 ; 28.659 ; 28.659 ;
; ADR[5]       ; RAM_DATA[12]  ; 31.279 ; 31.279 ; 31.279 ; 31.279 ;
; ADR[5]       ; RAM_DATA[13]  ; 28.625 ; 28.625 ; 28.625 ; 28.625 ;
; ADR[5]       ; RAM_DATA[14]  ; 28.779 ; 28.779 ; 28.779 ; 28.779 ;
; ADR[5]       ; RAM_DATA[15]  ; 29.056 ; 29.056 ; 29.056 ; 29.056 ;
; ASn          ; ACSI_RDn      ; 22.214 ; 22.214 ; 22.214 ; 22.214 ;
; ASn          ; ACSI_WRn      ; 22.204 ; 22.204 ; 22.204 ; 22.204 ;
; ASn          ; ASn           ; 29.424 ; 29.424 ; 29.424 ; 29.424 ;
; ASn          ; BUTTONn       ; 17.200 ;        ;        ; 17.200 ;
; ASn          ; CA1_OUT       ; 20.078 ;        ;        ; 20.078 ;
; ASn          ; CD[0]         ; 28.045 ; 28.045 ; 28.045 ; 28.045 ;
; ASn          ; CD[1]         ; 27.530 ; 27.530 ; 27.530 ; 27.530 ;
; ASn          ; CD[2]         ; 26.971 ; 26.971 ; 26.971 ; 26.971 ;
; ASn          ; CD[3]         ; 28.510 ; 28.510 ; 28.510 ; 28.510 ;
; ASn          ; CD[4]         ; 27.452 ; 27.452 ; 27.452 ; 27.452 ;
; ASn          ; CD[5]         ; 26.616 ; 26.616 ; 26.616 ; 26.616 ;
; ASn          ; CD[6]         ; 29.290 ; 29.290 ; 29.290 ; 29.290 ;
; ASn          ; CD[7]         ; 26.969 ; 26.969 ; 26.969 ; 26.969 ;
; ASn          ; DATA[0]       ; 40.447 ; 40.447 ; 40.447 ; 40.447 ;
; ASn          ; DATA[1]       ; 37.848 ; 37.848 ; 37.848 ; 37.848 ;
; ASn          ; DATA[2]       ; 38.373 ; 38.686 ; 38.686 ; 38.373 ;
; ASn          ; DATA[3]       ; 39.042 ; 39.042 ; 39.042 ; 39.042 ;
; ASn          ; DATA[4]       ; 37.178 ; 37.178 ; 37.178 ; 37.178 ;
; ASn          ; DATA[5]       ; 39.074 ; 39.074 ; 39.074 ; 39.074 ;
; ASn          ; DATA[6]       ; 36.656 ; 36.656 ; 36.656 ; 36.656 ;
; ASn          ; DATA[7]       ; 38.590 ; 38.590 ; 38.590 ; 38.590 ;
; ASn          ; DATA[8]       ; 37.611 ; 37.611 ; 37.611 ; 37.611 ;
; ASn          ; DATA[9]       ; 38.091 ; 38.670 ; 38.670 ; 38.091 ;
; ASn          ; DATA[10]      ; 38.119 ; 38.119 ; 38.119 ; 38.119 ;
; ASn          ; DATA[11]      ; 40.845 ; 40.126 ; 40.126 ; 40.845 ;
; ASn          ; DATA[12]      ; 37.673 ; 38.113 ; 38.113 ; 37.673 ;
; ASn          ; DATA[13]      ; 38.817 ; 39.496 ; 39.496 ; 38.817 ;
; ASn          ; DATA[14]      ; 36.378 ; 36.378 ; 36.378 ; 36.378 ;
; ASn          ; DATA[15]      ; 37.127 ; 37.127 ; 37.127 ; 37.127 ;
; ASn          ; DTACKn        ; 30.192 ; 30.192 ; 30.192 ; 30.192 ;
; ASn          ; FC[0]         ; 30.303 ; 30.303 ; 30.303 ; 30.303 ;
; ASn          ; FC[1]         ; 29.763 ; 29.763 ; 29.763 ; 29.763 ;
; ASn          ; FC[2]         ; 29.763 ; 29.763 ; 29.763 ; 29.763 ;
; ASn          ; FLASH_CEn     ; 20.062 ;        ;        ; 20.062 ;
; ASn          ; FLASH_OEn     ; 21.281 ;        ;        ; 21.281 ;
; ASn          ; IDE_CS0n      ; 15.332 ;        ;        ; 15.332 ;
; ASn          ; IDE_CS1n      ; 15.024 ;        ;        ; 15.024 ;
; ASn          ; IDE_D_EN_INn  ; 15.673 ;        ;        ; 15.673 ;
; ASn          ; IDE_D_EN_OUTn ; 15.027 ;        ;        ; 15.027 ;
; ASn          ; IDE_IORDn     ; 15.148 ;        ;        ; 15.148 ;
; ASn          ; IDE_IOWRn     ; 15.024 ;        ;        ; 15.024 ;
; ASn          ; JOY_RHn       ; 15.313 ;        ;        ; 15.313 ;
; ASn          ; JOY_RLn       ; 17.333 ;        ;        ; 17.333 ;
; ASn          ; JOY_WEn       ;        ; 17.303 ; 17.303 ;        ;
; ASn          ; JOY_WL        ;        ; 14.557 ; 14.557 ;        ;
; ASn          ; LDSn          ; 30.727 ; 30.727 ; 30.727 ; 30.727 ;
; ASn          ; RAM_DATA[0]   ; 35.836 ; 35.836 ; 35.836 ; 35.836 ;
; ASn          ; RAM_DATA[1]   ; 35.905 ; 35.905 ; 35.905 ; 35.905 ;
; ASn          ; RAM_DATA[2]   ; 36.085 ; 36.398 ; 36.398 ; 36.085 ;
; ASn          ; RAM_DATA[3]   ; 36.566 ; 36.566 ; 36.566 ; 36.566 ;
; ASn          ; RAM_DATA[4]   ; 37.734 ; 37.734 ; 37.734 ; 37.734 ;
; ASn          ; RAM_DATA[5]   ; 35.712 ; 35.712 ; 35.712 ; 35.712 ;
; ASn          ; RAM_DATA[6]   ; 36.180 ; 36.180 ; 36.180 ; 36.180 ;
; ASn          ; RAM_DATA[7]   ; 37.525 ; 37.525 ; 37.525 ; 37.525 ;
; ASn          ; RAM_DATA[8]   ; 36.250 ; 36.250 ; 36.250 ; 36.250 ;
; ASn          ; RAM_DATA[9]   ; 36.225 ; 36.804 ; 36.804 ; 36.225 ;
; ASn          ; RAM_DATA[10]  ; 37.848 ; 37.848 ; 37.848 ; 37.848 ;
; ASn          ; RAM_DATA[11]  ; 36.633 ; 35.914 ; 35.914 ; 36.633 ;
; ASn          ; RAM_DATA[12]  ; 37.492 ; 37.932 ; 37.932 ; 37.492 ;
; ASn          ; RAM_DATA[13]  ; 35.507 ; 36.186 ; 36.186 ; 35.507 ;
; ASn          ; RAM_DATA[14]  ; 33.802 ; 33.802 ; 33.802 ; 33.802 ;
; ASn          ; RAM_DATA[15]  ; 34.103 ; 34.103 ; 34.103 ; 34.103 ;
; ASn          ; ROM0n         ; 17.866 ;        ;        ; 17.866 ;
; ASn          ; ROM1n         ; 19.503 ;        ;        ; 19.503 ;
; ASn          ; ROM2n         ; 18.100 ;        ;        ; 18.100 ;
; ASn          ; ROM3n         ; 17.070 ;        ;        ; 17.070 ;
; ASn          ; ROM4n         ; 16.435 ;        ;        ; 16.435 ;
; ASn          ; ROM5n         ; 19.189 ;        ;        ; 19.189 ;
; ASn          ; ROM6n         ; 17.402 ;        ;        ; 17.402 ;
; ASn          ; RWn           ; 31.019 ; 31.019 ; 31.019 ; 31.019 ;
; ASn          ; UDSn          ; 30.727 ; 30.727 ; 30.727 ; 30.727 ;
; CD[0]        ; DATA[0]       ; 23.621 ;        ;        ; 23.621 ;
; CD[0]        ; RAM_DATA[0]   ; 19.010 ;        ;        ; 19.010 ;
; CD[1]        ; DATA[1]       ; 22.583 ;        ;        ; 22.583 ;
; CD[1]        ; RAM_DATA[1]   ; 20.640 ;        ;        ; 20.640 ;
; CD[2]        ; DATA[2]       ; 22.712 ;        ;        ; 22.712 ;
; CD[2]        ; RAM_DATA[2]   ; 20.424 ;        ;        ; 20.424 ;
; CD[3]        ; DATA[3]       ; 23.925 ;        ;        ; 23.925 ;
; CD[3]        ; RAM_DATA[3]   ; 21.449 ;        ;        ; 21.449 ;
; CD[4]        ; DATA[4]       ; 20.506 ; 20.506 ; 20.506 ; 20.506 ;
; CD[4]        ; RAM_DATA[4]   ; 21.062 ; 21.062 ; 21.062 ; 21.062 ;
; CD[5]        ; DATA[5]       ; 22.302 ; 22.302 ; 22.302 ; 22.302 ;
; CD[5]        ; RAM_DATA[5]   ; 18.940 ; 18.940 ; 18.940 ; 18.940 ;
; CD[6]        ; DATA[6]       ; 22.900 ; 22.900 ; 22.900 ; 22.900 ;
; CD[6]        ; RAM_DATA[6]   ; 22.424 ; 22.424 ; 22.424 ; 22.424 ;
; CD[7]        ; DATA[7]       ; 24.199 ; 24.199 ; 24.199 ; 24.199 ;
; CD[7]        ; RAM_DATA[7]   ; 23.134 ; 23.134 ; 23.134 ; 23.134 ;
; COM_DCD      ; DATA[1]       ;        ; 25.421 ; 25.421 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 24.954 ; 24.954 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 23.478 ; 23.478 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 23.088 ; 23.088 ;        ;
; COM_RI       ; DATA[6]       ; 25.283 ; 25.283 ; 25.283 ; 25.283 ;
; COM_RI       ; DATA[14]      ; 27.823 ; 27.823 ; 27.823 ; 27.823 ;
; COM_RI       ; RAM_DATA[6]   ; 24.807 ; 24.807 ; 24.807 ; 24.807 ;
; COM_RI       ; RAM_DATA[14]  ; 25.247 ; 25.247 ; 25.247 ; 25.247 ;
; CONFIG[1]    ; DATA[15]      ; 25.288 ; 25.288 ; 25.288 ; 25.288 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 22.264 ; 22.264 ; 22.264 ; 22.264 ;
; CONFIG[2]    ; DATA[14]      ; 24.440 ; 24.440 ; 24.440 ; 24.440 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 21.864 ; 21.864 ; 21.864 ; 21.864 ;
; CONFIG[5]    ; ACSI_RDn      ; 24.981 ; 24.981 ; 24.981 ; 24.981 ;
; CONFIG[5]    ; ACSI_WRn      ; 24.971 ; 24.971 ; 24.971 ; 24.971 ;
; CONFIG[5]    ; ASn           ; 31.407 ; 31.407 ; 31.407 ; 31.407 ;
; CONFIG[5]    ; BUTTONn       ; 23.540 ; 20.931 ; 20.931 ; 23.540 ;
; CONFIG[5]    ; CA1_OUT       ; 22.845 ; 20.236 ; 20.236 ; 22.845 ;
; CONFIG[5]    ; CD[0]         ; 30.812 ; 30.812 ; 30.812 ; 30.812 ;
; CONFIG[5]    ; CD[1]         ; 30.297 ; 30.297 ; 30.297 ; 30.297 ;
; CONFIG[5]    ; CD[2]         ; 29.738 ; 29.738 ; 29.738 ; 29.738 ;
; CONFIG[5]    ; CD[3]         ; 31.277 ; 31.277 ; 31.277 ; 31.277 ;
; CONFIG[5]    ; CD[4]         ; 30.219 ; 30.219 ; 30.219 ; 30.219 ;
; CONFIG[5]    ; CD[5]         ; 29.383 ; 29.383 ; 29.383 ; 29.383 ;
; CONFIG[5]    ; CD[6]         ; 32.057 ; 32.057 ; 32.057 ; 32.057 ;
; CONFIG[5]    ; CD[7]         ; 29.736 ; 29.736 ; 29.736 ; 29.736 ;
; CONFIG[5]    ; DATA[0]       ; 42.552 ; 42.552 ; 42.552 ; 42.552 ;
; CONFIG[5]    ; DATA[1]       ; 41.600 ; 41.600 ; 41.600 ; 41.600 ;
; CONFIG[5]    ; DATA[2]       ; 40.515 ; 40.370 ; 40.370 ; 40.515 ;
; CONFIG[5]    ; DATA[3]       ; 40.367 ; 40.725 ; 40.725 ; 40.367 ;
; CONFIG[5]    ; DATA[4]       ; 39.227 ; 39.227 ; 39.227 ; 39.227 ;
; CONFIG[5]    ; DATA[5]       ; 43.002 ; 43.002 ; 43.002 ; 43.002 ;
; CONFIG[5]    ; DATA[6]       ; 40.080 ; 40.080 ; 40.080 ; 40.080 ;
; CONFIG[5]    ; DATA[7]       ; 40.362 ; 40.362 ; 40.362 ; 40.362 ;
; CONFIG[5]    ; DATA[8]       ; 39.968 ; 39.968 ; 39.968 ; 39.968 ;
; CONFIG[5]    ; DATA[9]       ; 41.712 ; 41.056 ; 41.056 ; 41.712 ;
; CONFIG[5]    ; DATA[10]      ; 42.047 ; 42.047 ; 42.047 ; 42.047 ;
; CONFIG[5]    ; DATA[11]      ; 44.773 ; 43.566 ; 43.566 ; 44.773 ;
; CONFIG[5]    ; DATA[12]      ; 40.332 ; 40.022 ; 40.022 ; 40.332 ;
; CONFIG[5]    ; DATA[13]      ; 42.887 ; 41.739 ; 41.739 ; 42.887 ;
; CONFIG[5]    ; DATA[14]      ; 40.407 ; 40.407 ; 40.407 ; 40.407 ;
; CONFIG[5]    ; DATA[15]      ; 40.567 ; 40.567 ; 40.567 ; 40.567 ;
; CONFIG[5]    ; DTACKn        ; 35.037 ; 35.037 ; 35.037 ; 35.037 ;
; CONFIG[5]    ; FC[0]         ; 32.286 ; 32.286 ; 32.286 ; 32.286 ;
; CONFIG[5]    ; FC[1]         ; 31.746 ; 31.746 ; 31.746 ; 31.746 ;
; CONFIG[5]    ; FC[2]         ; 31.746 ; 31.746 ; 31.746 ; 31.746 ;
; CONFIG[5]    ; FLASH_CEn     ; 25.633 ; 25.453 ; 25.453 ; 25.633 ;
; CONFIG[5]    ; FLASH_OEn     ; 26.852 ; 26.672 ; 26.672 ; 26.852 ;
; CONFIG[5]    ; IDE_CS0n      ; 24.369 ; 21.556 ; 21.556 ; 24.369 ;
; CONFIG[5]    ; IDE_CS1n      ; 23.442 ; 20.629 ; 20.629 ; 23.442 ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 23.736 ; 20.923 ; 20.923 ; 23.736 ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 23.567 ; 20.754 ; 20.754 ; 23.567 ;
; CONFIG[5]    ; IDE_IORDn     ; 22.616 ; 19.803 ; 19.803 ; 22.616 ;
; CONFIG[5]    ; IDE_IOWRn     ; 25.753 ; 22.940 ; 22.940 ; 25.753 ;
; CONFIG[5]    ; JOY_RHn       ; 23.347 ; 20.738 ; 20.738 ; 23.347 ;
; CONFIG[5]    ; JOY_RLn       ; 25.367 ; 22.758 ; 22.758 ; 25.367 ;
; CONFIG[5]    ; JOY_WEn       ; 22.728 ; 25.337 ; 25.337 ; 22.728 ;
; CONFIG[5]    ; JOY_WL        ; 19.982 ; 22.591 ; 22.591 ; 19.982 ;
; CONFIG[5]    ; LDSn          ; 32.710 ; 32.710 ; 32.710 ; 32.710 ;
; CONFIG[5]    ; RAM_BA[1]     ; 17.697 ; 21.675 ; 21.675 ; 17.697 ;
; CONFIG[5]    ; RAM_CAS0n     ; 17.337 ; 19.574 ; 19.574 ; 17.337 ;
; CONFIG[5]    ; RAM_CAS1n     ; 18.758 ; 16.521 ; 16.521 ; 18.758 ;
; CONFIG[5]    ; RAM_DATA[0]   ; 37.941 ; 37.941 ; 37.941 ; 37.941 ;
; CONFIG[5]    ; RAM_DATA[1]   ; 39.657 ; 39.657 ; 39.657 ; 39.657 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 38.227 ; 38.082 ; 38.082 ; 38.227 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 37.891 ; 38.249 ; 38.249 ; 37.891 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 39.783 ; 39.783 ; 39.783 ; 39.783 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 39.640 ; 39.640 ; 39.640 ; 39.640 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 39.604 ; 39.604 ; 39.604 ; 39.604 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 39.297 ; 39.297 ; 39.297 ; 39.297 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 38.607 ; 38.607 ; 38.607 ; 38.607 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 39.846 ; 39.190 ; 39.190 ; 39.846 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 41.776 ; 41.776 ; 41.776 ; 41.776 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 40.561 ; 39.354 ; 39.354 ; 40.561 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 40.151 ; 39.841 ; 39.841 ; 40.151 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 39.577 ; 38.429 ; 38.429 ; 39.577 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 37.831 ; 37.831 ; 37.831 ; 37.831 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 37.543 ; 37.543 ; 37.543 ; 37.543 ;
; CONFIG[5]    ; RAM_RAS0n     ; 19.373 ; 22.225 ; 22.225 ; 19.373 ;
; CONFIG[5]    ; RAM_RAS1n     ; 21.948 ; 19.096 ; 19.096 ; 21.948 ;
; CONFIG[5]    ; ROM0n         ; 23.245 ; 20.409 ; 20.409 ; 23.245 ;
; CONFIG[5]    ; ROM1n         ; 24.882 ; 22.046 ; 22.046 ; 24.882 ;
; CONFIG[5]    ; ROM2n         ; 23.671 ; 23.491 ; 23.491 ; 23.671 ;
; CONFIG[5]    ; ROM3n         ; 26.725 ; 23.912 ; 23.912 ; 26.725 ;
; CONFIG[5]    ; ROM4n         ; 26.093 ; 23.280 ; 23.280 ; 26.093 ;
; CONFIG[5]    ; ROM5n         ; 24.568 ; 21.732 ; 21.732 ; 24.568 ;
; CONFIG[5]    ; ROM6n         ; 27.057 ; 24.244 ; 24.244 ; 27.057 ;
; CONFIG[5]    ; RWn           ; 33.002 ; 33.002 ; 33.002 ; 33.002 ;
; CONFIG[5]    ; UDSn          ; 32.710 ; 32.710 ; 32.710 ; 32.710 ;
; DATA[0]      ; DATA[0]       ; 22.287 ;        ;        ; 22.287 ;
; DATA[0]      ; RAM_DATA[0]   ; 17.676 ;        ;        ; 17.676 ;
; DATA[1]      ; DATA[1]       ; 21.789 ;        ;        ; 21.789 ;
; DATA[1]      ; RAM_DATA[1]   ; 19.846 ;        ;        ; 19.846 ;
; DATA[2]      ; DATA[2]       ; 21.507 ;        ;        ; 21.507 ;
; DATA[2]      ; RAM_DATA[2]   ; 19.219 ;        ;        ; 19.219 ;
; DATA[3]      ; DATA[3]       ; 21.541 ;        ;        ; 21.541 ;
; DATA[3]      ; RAM_DATA[3]   ; 19.065 ;        ;        ; 19.065 ;
; DATA[4]      ; DATA[4]       ; 16.750 ; 16.750 ; 16.750 ; 16.750 ;
; DATA[4]      ; RAM_DATA[4]   ; 17.306 ; 17.306 ; 17.306 ; 17.306 ;
; DATA[5]      ; DATA[5]       ; 19.688 ;        ;        ; 19.688 ;
; DATA[5]      ; RAM_DATA[5]   ; 16.326 ;        ;        ; 16.326 ;
; DATA[6]      ; DATA[6]       ; 18.035 ; 18.035 ; 18.035 ; 18.035 ;
; DATA[6]      ; RAM_DATA[6]   ; 17.559 ; 17.559 ; 17.559 ; 17.559 ;
; DATA[7]      ; DATA[7]       ; 18.442 ;        ;        ; 18.442 ;
; DATA[7]      ; RAM_DATA[7]   ; 17.377 ;        ;        ; 17.377 ;
; DATA[8]      ; DATA[8]       ; 20.155 ;        ;        ; 20.155 ;
; DATA[8]      ; RAM_DATA[8]   ; 18.794 ;        ;        ; 18.794 ;
; DATA[9]      ; DATA[9]       ; 21.796 ;        ;        ; 21.796 ;
; DATA[9]      ; RAM_DATA[9]   ; 19.930 ;        ;        ; 19.930 ;
; DATA[10]     ; DATA[10]      ; 20.806 ;        ;        ; 20.806 ;
; DATA[10]     ; RAM_DATA[10]  ; 20.535 ;        ;        ; 20.535 ;
; DATA[11]     ; DATA[11]      ; 22.508 ;        ;        ; 22.508 ;
; DATA[11]     ; RAM_DATA[11]  ; 18.296 ;        ;        ; 18.296 ;
; DATA[12]     ; DATA[12]      ; 23.067 ;        ;        ; 23.067 ;
; DATA[12]     ; RAM_DATA[12]  ; 22.886 ;        ;        ; 22.886 ;
; DATA[13]     ; DATA[13]      ; 23.615 ;        ;        ; 23.615 ;
; DATA[13]     ; RAM_DATA[13]  ; 20.305 ;        ;        ; 20.305 ;
; DATA[14]     ; DATA[14]      ; 16.839 ;        ;        ; 16.839 ;
; DATA[14]     ; RAM_DATA[14]  ; 14.263 ;        ;        ; 14.263 ;
; DATA[15]     ; DATA[15]      ; 17.411 ;        ;        ; 17.411 ;
; DATA[15]     ; RAM_DATA[15]  ; 14.387 ;        ;        ; 14.387 ;
; FC[0]        ; ACSI_RDn      ; 21.864 ; 21.864 ; 21.864 ; 21.864 ;
; FC[0]        ; ACSI_WRn      ; 21.854 ; 21.854 ; 21.854 ; 21.854 ;
; FC[0]        ; ASn           ; 29.074 ; 29.074 ; 29.074 ; 29.074 ;
; FC[0]        ; BUTTONn       ; 19.259 ; 18.501 ; 18.501 ; 19.259 ;
; FC[0]        ; CA1_OUT       ; 19.728 ; 16.703 ; 16.703 ; 19.728 ;
; FC[0]        ; CD[0]         ; 27.695 ; 27.695 ; 27.695 ; 27.695 ;
; FC[0]        ; CD[1]         ; 27.180 ; 27.180 ; 27.180 ; 27.180 ;
; FC[0]        ; CD[2]         ; 26.621 ; 26.621 ; 26.621 ; 26.621 ;
; FC[0]        ; CD[3]         ; 28.160 ; 28.160 ; 28.160 ; 28.160 ;
; FC[0]        ; CD[4]         ; 27.102 ; 27.102 ; 27.102 ; 27.102 ;
; FC[0]        ; CD[5]         ; 26.266 ; 26.266 ; 26.266 ; 26.266 ;
; FC[0]        ; CD[6]         ; 28.940 ; 28.940 ; 28.940 ; 28.940 ;
; FC[0]        ; CD[7]         ; 26.619 ; 26.619 ; 26.619 ; 26.619 ;
; FC[0]        ; DATA[0]       ; 40.097 ; 40.097 ; 40.097 ; 40.097 ;
; FC[0]        ; DATA[1]       ; 39.808 ; 39.808 ; 39.808 ; 39.808 ;
; FC[0]        ; DATA[2]       ; 38.830 ; 38.830 ; 38.830 ; 38.830 ;
; FC[0]        ; DATA[3]       ; 38.891 ; 38.891 ; 38.891 ; 38.891 ;
; FC[0]        ; DATA[4]       ; 37.846 ; 37.846 ; 37.846 ; 37.846 ;
; FC[0]        ; DATA[5]       ; 41.168 ; 41.168 ; 41.168 ; 41.168 ;
; FC[0]        ; DATA[6]       ; 38.699 ; 38.699 ; 38.699 ; 38.699 ;
; FC[0]        ; DATA[7]       ; 38.981 ; 38.981 ; 38.981 ; 38.981 ;
; FC[0]        ; DATA[8]       ; 38.587 ; 38.587 ; 38.587 ; 38.587 ;
; FC[0]        ; DATA[9]       ; 39.878 ; 39.878 ; 39.878 ; 39.878 ;
; FC[0]        ; DATA[10]      ; 40.213 ; 40.213 ; 40.213 ; 40.213 ;
; FC[0]        ; DATA[11]      ; 42.939 ; 42.939 ; 42.939 ; 42.939 ;
; FC[0]        ; DATA[12]      ; 38.498 ; 38.498 ; 38.498 ; 38.498 ;
; FC[0]        ; DATA[13]      ; 39.879 ; 39.879 ; 39.879 ; 39.879 ;
; FC[0]        ; DATA[14]      ; 38.437 ; 38.437 ; 38.437 ; 38.437 ;
; FC[0]        ; DATA[15]      ; 39.186 ; 39.186 ; 39.186 ; 39.186 ;
; FC[0]        ; DTACKn        ; 29.842 ; 29.842 ; 29.842 ; 29.842 ;
; FC[0]        ; FC[0]         ; 29.953 ; 29.953 ; 29.953 ; 29.953 ;
; FC[0]        ; FC[1]         ; 29.413 ; 29.413 ; 29.413 ; 29.413 ;
; FC[0]        ; FC[2]         ; 29.413 ; 29.413 ; 29.413 ; 29.413 ;
; FC[0]        ; FLASH_CEn     ; 22.121 ; 21.850 ; 21.850 ; 22.121 ;
; FC[0]        ; FLASH_OEn     ; 23.340 ; 23.069 ; 23.069 ; 23.340 ;
; FC[0]        ; IDE_CS0n      ; 17.391 ;        ;        ; 17.391 ;
; FC[0]        ; IDE_CS1n      ; 17.083 ;        ;        ; 17.083 ;
; FC[0]        ; IDE_D_EN_INn  ; 17.732 ;        ;        ; 17.732 ;
; FC[0]        ; IDE_D_EN_OUTn ; 17.086 ;        ;        ; 17.086 ;
; FC[0]        ; IDE_IORDn     ; 17.207 ;        ;        ; 17.207 ;
; FC[0]        ; IDE_IOWRn     ; 17.083 ;        ;        ; 17.083 ;
; FC[0]        ; JOY_RHn       ; 18.472 ; 18.472 ; 18.472 ; 18.472 ;
; FC[0]        ; JOY_RLn       ; 20.501 ; 20.501 ; 20.501 ; 20.501 ;
; FC[0]        ; JOY_WEn       ; 20.471 ; 20.471 ; 20.471 ; 20.471 ;
; FC[0]        ; JOY_WL        ; 17.515 ; 17.515 ; 17.515 ; 17.515 ;
; FC[0]        ; LDSn          ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; FC[0]        ; RAM_DATA[0]   ; 35.486 ; 35.486 ; 35.486 ; 35.486 ;
; FC[0]        ; RAM_DATA[1]   ; 37.865 ; 37.865 ; 37.865 ; 37.865 ;
; FC[0]        ; RAM_DATA[2]   ; 36.542 ; 36.542 ; 36.542 ; 36.542 ;
; FC[0]        ; RAM_DATA[3]   ; 36.415 ; 36.415 ; 36.415 ; 36.415 ;
; FC[0]        ; RAM_DATA[4]   ; 38.402 ; 38.402 ; 38.402 ; 38.402 ;
; FC[0]        ; RAM_DATA[5]   ; 37.806 ; 37.806 ; 37.806 ; 37.806 ;
; FC[0]        ; RAM_DATA[6]   ; 38.223 ; 38.223 ; 38.223 ; 38.223 ;
; FC[0]        ; RAM_DATA[7]   ; 37.916 ; 37.916 ; 37.916 ; 37.916 ;
; FC[0]        ; RAM_DATA[8]   ; 37.226 ; 37.226 ; 37.226 ; 37.226 ;
; FC[0]        ; RAM_DATA[9]   ; 38.012 ; 38.012 ; 38.012 ; 38.012 ;
; FC[0]        ; RAM_DATA[10]  ; 39.942 ; 39.942 ; 39.942 ; 39.942 ;
; FC[0]        ; RAM_DATA[11]  ; 38.727 ; 38.727 ; 38.727 ; 38.727 ;
; FC[0]        ; RAM_DATA[12]  ; 38.317 ; 38.317 ; 38.317 ; 38.317 ;
; FC[0]        ; RAM_DATA[13]  ; 36.569 ; 36.569 ; 36.569 ; 36.569 ;
; FC[0]        ; RAM_DATA[14]  ; 35.861 ; 35.861 ; 35.861 ; 35.861 ;
; FC[0]        ; RAM_DATA[15]  ; 36.162 ; 36.162 ; 36.162 ; 36.162 ;
; FC[0]        ; ROM0n         ; 19.925 ; 19.363 ; 19.363 ; 19.925 ;
; FC[0]        ; ROM1n         ; 21.562 ; 21.000 ; 21.000 ; 21.562 ;
; FC[0]        ; ROM2n         ; 20.159 ; 19.888 ; 19.888 ; 20.159 ;
; FC[0]        ; ROM3n         ; 19.129 ; 18.858 ; 18.858 ; 19.129 ;
; FC[0]        ; ROM4n         ; 18.494 ; 18.223 ; 18.223 ; 18.494 ;
; FC[0]        ; ROM5n         ; 21.248 ; 20.686 ; 20.686 ; 21.248 ;
; FC[0]        ; ROM6n         ; 19.461 ; 19.190 ; 19.190 ; 19.461 ;
; FC[0]        ; RWn           ; 30.669 ; 30.669 ; 30.669 ; 30.669 ;
; FC[0]        ; UDSn          ; 30.377 ; 30.377 ; 30.377 ; 30.377 ;
; FC[1]        ; ACSI_RDn      ; 22.167 ; 22.167 ; 22.167 ; 22.167 ;
; FC[1]        ; ACSI_WRn      ; 22.157 ; 22.157 ; 22.157 ; 22.157 ;
; FC[1]        ; ASn           ; 29.377 ; 29.377 ; 29.377 ; 29.377 ;
; FC[1]        ; BUTTONn       ; 18.769 ; 16.502 ; 16.502 ; 18.769 ;
; FC[1]        ; CA1_OUT       ; 20.031 ; 17.012 ; 17.012 ; 20.031 ;
; FC[1]        ; CD[0]         ; 27.998 ; 27.998 ; 27.998 ; 27.998 ;
; FC[1]        ; CD[1]         ; 27.483 ; 27.483 ; 27.483 ; 27.483 ;
; FC[1]        ; CD[2]         ; 26.924 ; 26.924 ; 26.924 ; 26.924 ;
; FC[1]        ; CD[3]         ; 28.463 ; 28.463 ; 28.463 ; 28.463 ;
; FC[1]        ; CD[4]         ; 27.405 ; 27.405 ; 27.405 ; 27.405 ;
; FC[1]        ; CD[5]         ; 26.569 ; 26.569 ; 26.569 ; 26.569 ;
; FC[1]        ; CD[6]         ; 29.243 ; 29.243 ; 29.243 ; 29.243 ;
; FC[1]        ; CD[7]         ; 26.922 ; 26.922 ; 26.922 ; 26.922 ;
; FC[1]        ; DATA[0]       ; 40.400 ; 40.400 ; 40.400 ; 40.400 ;
; FC[1]        ; DATA[1]       ; 39.318 ; 39.318 ; 39.318 ; 39.318 ;
; FC[1]        ; DATA[2]       ; 38.340 ; 38.639 ; 38.639 ; 38.340 ;
; FC[1]        ; DATA[3]       ; 38.995 ; 38.995 ; 38.995 ; 38.995 ;
; FC[1]        ; DATA[4]       ; 37.356 ; 37.356 ; 37.356 ; 37.356 ;
; FC[1]        ; DATA[5]       ; 40.680 ; 40.680 ; 40.680 ; 40.680 ;
; FC[1]        ; DATA[6]       ; 38.209 ; 38.209 ; 38.209 ; 38.209 ;
; FC[1]        ; DATA[7]       ; 38.543 ; 38.543 ; 38.543 ; 38.543 ;
; FC[1]        ; DATA[8]       ; 38.097 ; 38.097 ; 38.097 ; 38.097 ;
; FC[1]        ; DATA[9]       ; 39.390 ; 39.390 ; 39.390 ; 39.390 ;
; FC[1]        ; DATA[10]      ; 39.725 ; 39.725 ; 39.725 ; 39.725 ;
; FC[1]        ; DATA[11]      ; 42.451 ; 42.451 ; 42.451 ; 42.451 ;
; FC[1]        ; DATA[12]      ; 38.010 ; 38.066 ; 38.066 ; 38.010 ;
; FC[1]        ; DATA[13]      ; 39.391 ; 39.449 ; 39.449 ; 39.391 ;
; FC[1]        ; DATA[14]      ; 37.947 ; 37.947 ; 37.947 ; 37.947 ;
; FC[1]        ; DATA[15]      ; 38.696 ; 38.696 ; 38.696 ; 38.696 ;
; FC[1]        ; DTACKn        ; 30.145 ; 30.145 ; 30.145 ; 30.145 ;
; FC[1]        ; FC[0]         ; 30.256 ; 30.256 ; 30.256 ; 30.256 ;
; FC[1]        ; FC[1]         ; 29.716 ; 29.716 ; 29.716 ; 29.716 ;
; FC[1]        ; FC[2]         ; 29.716 ; 29.716 ; 29.716 ; 29.716 ;
; FC[1]        ; FLASH_CEn     ; 21.631 ; 19.851 ; 19.851 ; 21.631 ;
; FC[1]        ; FLASH_OEn     ; 22.850 ; 21.070 ; 21.070 ; 22.850 ;
; FC[1]        ; IDE_CS0n      ; 16.901 ;        ;        ; 16.901 ;
; FC[1]        ; IDE_CS1n      ; 16.593 ;        ;        ; 16.593 ;
; FC[1]        ; IDE_D_EN_INn  ; 17.242 ;        ;        ; 17.242 ;
; FC[1]        ; IDE_D_EN_OUTn ; 16.596 ;        ;        ; 16.596 ;
; FC[1]        ; IDE_IORDn     ; 16.717 ;        ;        ; 16.717 ;
; FC[1]        ; IDE_IOWRn     ; 16.593 ;        ;        ; 16.593 ;
; FC[1]        ; JOY_RHn       ; 17.984 ; 17.984 ; 17.984 ; 17.984 ;
; FC[1]        ; JOY_RLn       ; 20.013 ; 20.013 ; 20.013 ; 20.013 ;
; FC[1]        ; JOY_WEn       ; 19.983 ; 19.983 ; 19.983 ; 19.983 ;
; FC[1]        ; JOY_WL        ; 17.027 ; 17.027 ; 17.027 ; 17.027 ;
; FC[1]        ; LDSn          ; 30.680 ; 30.680 ; 30.680 ; 30.680 ;
; FC[1]        ; RAM_DATA[0]   ; 35.789 ; 35.789 ; 35.789 ; 35.789 ;
; FC[1]        ; RAM_DATA[1]   ; 37.375 ; 37.375 ; 37.375 ; 37.375 ;
; FC[1]        ; RAM_DATA[2]   ; 36.052 ; 36.351 ; 36.351 ; 36.052 ;
; FC[1]        ; RAM_DATA[3]   ; 36.519 ; 36.519 ; 36.519 ; 36.519 ;
; FC[1]        ; RAM_DATA[4]   ; 37.912 ; 37.912 ; 37.912 ; 37.912 ;
; FC[1]        ; RAM_DATA[5]   ; 37.318 ; 37.318 ; 37.318 ; 37.318 ;
; FC[1]        ; RAM_DATA[6]   ; 37.733 ; 37.733 ; 37.733 ; 37.733 ;
; FC[1]        ; RAM_DATA[7]   ; 37.478 ; 37.478 ; 37.478 ; 37.478 ;
; FC[1]        ; RAM_DATA[8]   ; 36.736 ; 36.736 ; 36.736 ; 36.736 ;
; FC[1]        ; RAM_DATA[9]   ; 37.524 ; 37.524 ; 37.524 ; 37.524 ;
; FC[1]        ; RAM_DATA[10]  ; 39.454 ; 39.454 ; 39.454 ; 39.454 ;
; FC[1]        ; RAM_DATA[11]  ; 38.239 ; 38.239 ; 38.239 ; 38.239 ;
; FC[1]        ; RAM_DATA[12]  ; 37.829 ; 37.885 ; 37.885 ; 37.829 ;
; FC[1]        ; RAM_DATA[13]  ; 36.081 ; 36.139 ; 36.139 ; 36.081 ;
; FC[1]        ; RAM_DATA[14]  ; 35.371 ; 35.371 ; 35.371 ; 35.371 ;
; FC[1]        ; RAM_DATA[15]  ; 35.672 ; 35.672 ; 35.672 ; 35.672 ;
; FC[1]        ; ROM0n         ; 19.435 ; 17.364 ; 17.364 ; 19.435 ;
; FC[1]        ; ROM1n         ; 21.072 ; 19.001 ; 19.001 ; 21.072 ;
; FC[1]        ; ROM2n         ; 19.669 ; 17.889 ; 17.889 ; 19.669 ;
; FC[1]        ; ROM3n         ; 18.639 ; 16.859 ; 16.859 ; 18.639 ;
; FC[1]        ; ROM4n         ; 18.004 ; 16.224 ; 16.224 ; 18.004 ;
; FC[1]        ; ROM5n         ; 20.758 ; 18.687 ; 18.687 ; 20.758 ;
; FC[1]        ; ROM6n         ; 18.971 ; 17.191 ; 17.191 ; 18.971 ;
; FC[1]        ; RWn           ; 30.972 ; 30.972 ; 30.972 ; 30.972 ;
; FC[1]        ; UDSn          ; 30.680 ; 30.680 ; 30.680 ; 30.680 ;
; FC[2]        ; ACSI_RDn      ; 22.071 ; 22.071 ; 22.071 ; 22.071 ;
; FC[2]        ; ACSI_WRn      ; 22.061 ; 22.061 ; 22.061 ; 22.061 ;
; FC[2]        ; ASn           ; 29.281 ; 29.281 ; 29.281 ; 29.281 ;
; FC[2]        ; BUTTONn       ; 18.708 ;        ;        ; 18.708 ;
; FC[2]        ; CA1_OUT       ; 19.935 ; 16.916 ; 16.916 ; 19.935 ;
; FC[2]        ; CD[0]         ; 27.902 ; 27.902 ; 27.902 ; 27.902 ;
; FC[2]        ; CD[1]         ; 27.387 ; 27.387 ; 27.387 ; 27.387 ;
; FC[2]        ; CD[2]         ; 26.828 ; 26.828 ; 26.828 ; 26.828 ;
; FC[2]        ; CD[3]         ; 28.367 ; 28.367 ; 28.367 ; 28.367 ;
; FC[2]        ; CD[4]         ; 27.309 ; 27.309 ; 27.309 ; 27.309 ;
; FC[2]        ; CD[5]         ; 26.473 ; 26.473 ; 26.473 ; 26.473 ;
; FC[2]        ; CD[6]         ; 29.147 ; 29.147 ; 29.147 ; 29.147 ;
; FC[2]        ; CD[7]         ; 26.826 ; 26.826 ; 26.826 ; 26.826 ;
; FC[2]        ; DATA[0]       ; 40.304 ; 40.304 ; 40.304 ; 40.304 ;
; FC[2]        ; DATA[1]       ; 39.257 ; 39.257 ; 39.257 ; 39.257 ;
; FC[2]        ; DATA[2]       ; 38.279 ; 38.543 ; 38.543 ; 38.279 ;
; FC[2]        ; DATA[3]       ; 38.899 ; 38.899 ; 38.899 ; 38.899 ;
; FC[2]        ; DATA[4]       ; 37.295 ; 37.295 ; 37.295 ; 37.295 ;
; FC[2]        ; DATA[5]       ; 40.622 ; 40.622 ; 40.622 ; 40.622 ;
; FC[2]        ; DATA[6]       ; 38.148 ; 38.148 ; 38.148 ; 38.148 ;
; FC[2]        ; DATA[7]       ; 38.447 ; 38.447 ; 38.447 ; 38.447 ;
; FC[2]        ; DATA[8]       ; 38.036 ; 38.036 ; 38.036 ; 38.036 ;
; FC[2]        ; DATA[9]       ; 39.292 ; 39.332 ; 39.332 ; 39.292 ;
; FC[2]        ; DATA[10]      ; 39.667 ; 39.667 ; 39.667 ; 39.667 ;
; FC[2]        ; DATA[11]      ; 42.353 ; 42.393 ; 42.393 ; 42.353 ;
; FC[2]        ; DATA[12]      ; 37.912 ; 37.970 ; 37.970 ; 37.912 ;
; FC[2]        ; DATA[13]      ; 39.293 ; 39.353 ; 39.353 ; 39.293 ;
; FC[2]        ; DATA[14]      ; 37.886 ; 37.886 ; 37.886 ; 37.886 ;
; FC[2]        ; DATA[15]      ; 38.635 ; 38.635 ; 38.635 ; 38.635 ;
; FC[2]        ; DTACKn        ; 30.049 ; 30.049 ; 30.049 ; 30.049 ;
; FC[2]        ; FC[0]         ; 30.160 ; 30.160 ; 30.160 ; 30.160 ;
; FC[2]        ; FC[1]         ; 29.620 ; 29.620 ; 29.620 ; 29.620 ;
; FC[2]        ; FC[2]         ; 29.620 ; 29.620 ; 29.620 ; 29.620 ;
; FC[2]        ; FLASH_CEn     ; 21.570 ;        ;        ; 21.570 ;
; FC[2]        ; FLASH_OEn     ; 22.789 ;        ;        ; 22.789 ;
; FC[2]        ; IDE_CS0n      ; 16.840 ;        ;        ; 16.840 ;
; FC[2]        ; IDE_CS1n      ; 16.532 ;        ;        ; 16.532 ;
; FC[2]        ; IDE_D_EN_INn  ; 17.181 ;        ;        ; 17.181 ;
; FC[2]        ; IDE_D_EN_OUTn ; 16.535 ;        ;        ; 16.535 ;
; FC[2]        ; IDE_IORDn     ; 16.656 ;        ;        ; 16.656 ;
; FC[2]        ; IDE_IOWRn     ; 16.532 ;        ;        ; 16.532 ;
; FC[2]        ; JOY_RHn       ; 16.821 ; 17.926 ; 17.926 ; 16.821 ;
; FC[2]        ; JOY_RLn       ; 18.841 ; 19.955 ; 19.955 ; 18.841 ;
; FC[2]        ; JOY_WEn       ; 19.925 ; 18.811 ; 18.811 ; 19.925 ;
; FC[2]        ; JOY_WL        ; 16.969 ; 16.065 ; 16.065 ; 16.969 ;
; FC[2]        ; LDSn          ; 30.584 ; 30.584 ; 30.584 ; 30.584 ;
; FC[2]        ; RAM_DATA[0]   ; 35.693 ; 35.693 ; 35.693 ; 35.693 ;
; FC[2]        ; RAM_DATA[1]   ; 37.314 ; 37.314 ; 37.314 ; 37.314 ;
; FC[2]        ; RAM_DATA[2]   ; 35.991 ; 36.255 ; 36.255 ; 35.991 ;
; FC[2]        ; RAM_DATA[3]   ; 36.423 ; 36.423 ; 36.423 ; 36.423 ;
; FC[2]        ; RAM_DATA[4]   ; 37.851 ; 37.851 ; 37.851 ; 37.851 ;
; FC[2]        ; RAM_DATA[5]   ; 37.260 ; 37.260 ; 37.260 ; 37.260 ;
; FC[2]        ; RAM_DATA[6]   ; 37.672 ; 37.672 ; 37.672 ; 37.672 ;
; FC[2]        ; RAM_DATA[7]   ; 37.382 ; 37.382 ; 37.382 ; 37.382 ;
; FC[2]        ; RAM_DATA[8]   ; 36.675 ; 36.675 ; 36.675 ; 36.675 ;
; FC[2]        ; RAM_DATA[9]   ; 37.426 ; 37.466 ; 37.466 ; 37.426 ;
; FC[2]        ; RAM_DATA[10]  ; 39.396 ; 39.396 ; 39.396 ; 39.396 ;
; FC[2]        ; RAM_DATA[11]  ; 38.141 ; 38.181 ; 38.181 ; 38.141 ;
; FC[2]        ; RAM_DATA[12]  ; 37.731 ; 37.789 ; 37.789 ; 37.731 ;
; FC[2]        ; RAM_DATA[13]  ; 35.983 ; 36.043 ; 36.043 ; 35.983 ;
; FC[2]        ; RAM_DATA[14]  ; 35.310 ; 35.310 ; 35.310 ; 35.310 ;
; FC[2]        ; RAM_DATA[15]  ; 35.611 ; 35.611 ; 35.611 ; 35.611 ;
; FC[2]        ; ROM0n         ; 19.374 ;        ;        ; 19.374 ;
; FC[2]        ; ROM1n         ; 21.011 ;        ;        ; 21.011 ;
; FC[2]        ; ROM2n         ; 19.608 ;        ;        ; 19.608 ;
; FC[2]        ; ROM3n         ; 18.578 ;        ;        ; 18.578 ;
; FC[2]        ; ROM4n         ; 17.943 ;        ;        ; 17.943 ;
; FC[2]        ; ROM5n         ; 20.697 ;        ;        ; 20.697 ;
; FC[2]        ; ROM6n         ; 18.910 ;        ;        ; 18.910 ;
; FC[2]        ; RWn           ; 30.876 ; 30.876 ; 30.876 ; 30.876 ;
; FC[2]        ; UDSn          ; 30.584 ; 30.584 ; 30.584 ; 30.584 ;
; HDINTn       ; DATA[5]       ; 26.726 ; 26.726 ; 26.726 ; 26.726 ;
; HDINTn       ; DATA[13]      ; 27.379 ;        ;        ; 27.379 ;
; HDINTn       ; RAM_DATA[5]   ; 23.364 ; 23.364 ; 23.364 ; 23.364 ;
; HDINTn       ; RAM_DATA[13]  ; 24.069 ;        ;        ; 24.069 ;
; IDE_INTRQ    ; DATA[5]       ; 26.932 ; 26.932 ; 26.932 ; 26.932 ;
; IDE_INTRQ    ; DATA[13]      ;        ; 27.585 ; 27.585 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ; 23.570 ; 23.570 ; 23.570 ; 23.570 ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 24.275 ; 24.275 ;        ;
; LDSn         ; ACSI_RDn      ; 16.172 ; 16.172 ; 16.172 ; 16.172 ;
; LDSn         ; ACSI_WRn      ; 16.162 ; 16.162 ; 16.162 ; 16.162 ;
; LDSn         ; ASn           ; 28.228 ; 28.228 ; 28.228 ; 28.228 ;
; LDSn         ; BUTTONn       ; 17.903 ;        ;        ; 17.903 ;
; LDSn         ; CA1_OUT       ; 14.036 ;        ;        ; 14.036 ;
; LDSn         ; CD[0]         ; 22.003 ; 22.003 ; 22.003 ; 22.003 ;
; LDSn         ; CD[1]         ; 21.488 ; 21.488 ; 21.488 ; 21.488 ;
; LDSn         ; CD[2]         ; 20.929 ; 20.929 ; 20.929 ; 20.929 ;
; LDSn         ; CD[3]         ; 22.468 ; 22.468 ; 22.468 ; 22.468 ;
; LDSn         ; CD[4]         ; 21.410 ; 21.410 ; 21.410 ; 21.410 ;
; LDSn         ; CD[5]         ; 20.574 ; 20.574 ; 20.574 ; 20.574 ;
; LDSn         ; CD[6]         ; 23.248 ; 23.248 ; 23.248 ; 23.248 ;
; LDSn         ; CD[7]         ; 20.927 ; 20.927 ; 20.927 ; 20.927 ;
; LDSn         ; DATA[0]       ; 39.251 ; 39.251 ; 39.251 ; 39.251 ;
; LDSn         ; DATA[1]       ; 36.652 ; 36.652 ; 36.652 ; 36.652 ;
; LDSn         ; DATA[2]       ; 37.177 ; 37.490 ; 37.490 ; 37.177 ;
; LDSn         ; DATA[3]       ; 37.846 ; 37.846 ; 37.846 ; 37.846 ;
; LDSn         ; DATA[4]       ; 35.982 ; 35.982 ; 35.982 ; 35.982 ;
; LDSn         ; DATA[5]       ; 37.819 ; 37.819 ; 37.819 ; 37.819 ;
; LDSn         ; DATA[6]       ; 35.460 ; 35.460 ; 35.460 ; 35.460 ;
; LDSn         ; DATA[7]       ; 37.394 ; 37.394 ; 37.394 ; 37.394 ;
; LDSn         ; DATA[8]       ; 36.415 ; 36.415 ; 36.415 ; 36.415 ;
; LDSn         ; DATA[9]       ; 36.895 ; 37.474 ; 37.474 ; 36.895 ;
; LDSn         ; DATA[10]      ; 36.626 ; 36.626 ; 36.626 ; 36.626 ;
; LDSn         ; DATA[11]      ; 38.826 ; 39.352 ; 39.352 ; 38.826 ;
; LDSn         ; DATA[12]      ; 36.477 ; 36.917 ; 36.917 ; 36.477 ;
; LDSn         ; DATA[13]      ; 37.621 ; 38.300 ; 38.300 ; 37.621 ;
; LDSn         ; DATA[14]      ; 34.922 ; 34.922 ; 34.922 ; 34.922 ;
; LDSn         ; DATA[15]      ; 35.827 ; 35.827 ; 35.827 ; 35.827 ;
; LDSn         ; DTACKn        ; 27.380 ; 27.380 ; 27.380 ; 27.380 ;
; LDSn         ; FC[0]         ; 29.107 ; 29.107 ; 29.107 ; 29.107 ;
; LDSn         ; FC[1]         ; 28.567 ; 28.567 ; 28.567 ; 28.567 ;
; LDSn         ; FC[2]         ; 28.567 ; 28.567 ; 28.567 ; 28.567 ;
; LDSn         ; IDE_IORDn     ; 15.219 ;        ;        ; 15.219 ;
; LDSn         ; IDE_IOWRn     ; 15.145 ;        ;        ; 15.145 ;
; LDSn         ; JOY_RLn       ; 17.022 ;        ;        ; 17.022 ;
; LDSn         ; JOY_WEn       ;        ; 16.992 ; 16.992 ;        ;
; LDSn         ; JOY_WL        ;        ; 14.045 ; 14.045 ;        ;
; LDSn         ; LDSn          ; 29.531 ; 29.531 ; 29.531 ; 29.531 ;
; LDSn         ; RAM_CAS0n     ; 21.179 ;        ;        ; 21.179 ;
; LDSn         ; RAM_CAS1n     ; 20.361 ;        ;        ; 20.361 ;
; LDSn         ; RAM_DATA[0]   ; 34.640 ; 34.640 ; 34.640 ; 34.640 ;
; LDSn         ; RAM_DATA[1]   ; 34.709 ; 34.709 ; 34.709 ; 34.709 ;
; LDSn         ; RAM_DATA[2]   ; 34.889 ; 35.202 ; 35.202 ; 34.889 ;
; LDSn         ; RAM_DATA[3]   ; 35.370 ; 35.370 ; 35.370 ; 35.370 ;
; LDSn         ; RAM_DATA[4]   ; 36.538 ; 36.538 ; 36.538 ; 36.538 ;
; LDSn         ; RAM_DATA[5]   ; 34.457 ; 34.457 ; 34.457 ; 34.457 ;
; LDSn         ; RAM_DATA[6]   ; 34.984 ; 34.984 ; 34.984 ; 34.984 ;
; LDSn         ; RAM_DATA[7]   ; 36.329 ; 36.329 ; 36.329 ; 36.329 ;
; LDSn         ; RAM_DATA[8]   ; 35.054 ; 35.054 ; 35.054 ; 35.054 ;
; LDSn         ; RAM_DATA[9]   ; 35.029 ; 35.608 ; 35.608 ; 35.029 ;
; LDSn         ; RAM_DATA[10]  ; 36.355 ; 36.355 ; 36.355 ; 36.355 ;
; LDSn         ; RAM_DATA[11]  ; 34.614 ; 35.140 ; 35.140 ; 34.614 ;
; LDSn         ; RAM_DATA[12]  ; 36.296 ; 36.736 ; 36.736 ; 36.296 ;
; LDSn         ; RAM_DATA[13]  ; 34.311 ; 34.990 ; 34.990 ; 34.311 ;
; LDSn         ; RAM_DATA[14]  ; 32.346 ; 32.346 ; 32.346 ; 32.346 ;
; LDSn         ; RAM_DATA[15]  ; 32.803 ; 32.803 ; 32.803 ; 32.803 ;
; LDSn         ; RAM_DQM0H     ; 26.091 ; 25.661 ; 25.661 ; 26.091 ;
; LDSn         ; RAM_DQM0L     ; 24.410 ; 24.031 ; 24.031 ; 24.410 ;
; LDSn         ; RAM_DQM1H     ; 26.284 ; 25.854 ; 25.854 ; 26.284 ;
; LDSn         ; RAM_DQM1L     ; 24.400 ; 24.021 ; 24.021 ; 24.400 ;
; LDSn         ; RWn           ; 29.823 ; 29.823 ; 29.823 ; 29.823 ;
; LDSn         ; UDSn          ; 29.531 ; 29.531 ; 29.531 ; 29.531 ;
; LPT_BSY      ; DATA[0]       ; 23.759 ;        ;        ; 23.759 ;
; LPT_BSY      ; DATA[8]       ; 21.983 ;        ;        ; 21.983 ;
; LPT_BSY      ; RAM_DATA[0]   ; 19.148 ;        ;        ; 19.148 ;
; LPT_BSY      ; RAM_DATA[8]   ; 20.622 ;        ;        ; 20.622 ;
; LPT_D[0]     ; DATA[0]       ; 22.797 ;        ;        ; 22.797 ;
; LPT_D[0]     ; DATA[8]       ; 21.021 ;        ;        ; 21.021 ;
; LPT_D[0]     ; RAM_DATA[0]   ; 18.186 ;        ;        ; 18.186 ;
; LPT_D[0]     ; RAM_DATA[8]   ; 19.660 ;        ;        ; 19.660 ;
; LPT_D[1]     ; DATA[1]       ; 22.129 ;        ;        ; 22.129 ;
; LPT_D[1]     ; DATA[9]       ; 21.856 ;        ;        ; 21.856 ;
; LPT_D[1]     ; RAM_DATA[1]   ; 20.186 ;        ;        ; 20.186 ;
; LPT_D[1]     ; RAM_DATA[9]   ; 19.990 ;        ;        ; 19.990 ;
; LPT_D[2]     ; DATA[2]       ; 21.883 ;        ;        ; 21.883 ;
; LPT_D[2]     ; DATA[10]      ; 21.572 ;        ;        ; 21.572 ;
; LPT_D[2]     ; RAM_DATA[2]   ; 19.595 ;        ;        ; 19.595 ;
; LPT_D[2]     ; RAM_DATA[10]  ; 21.301 ;        ;        ; 21.301 ;
; LPT_D[3]     ; DATA[3]       ; 23.208 ;        ;        ; 23.208 ;
; LPT_D[3]     ; DATA[11]      ; 24.946 ;        ;        ; 24.946 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 20.732 ;        ;        ; 20.732 ;
; LPT_D[3]     ; RAM_DATA[11]  ; 20.734 ;        ;        ; 20.734 ;
; LPT_D[4]     ; DATA[4]       ; 25.353 ; 25.353 ; 25.353 ; 25.353 ;
; LPT_D[4]     ; DATA[12]      ; 24.867 ;        ;        ; 24.867 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 25.909 ; 25.909 ; 25.909 ; 25.909 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 24.686 ;        ;        ; 24.686 ;
; LPT_D[5]     ; DATA[5]       ; 25.140 ; 25.140 ; 25.140 ; 25.140 ;
; LPT_D[5]     ; DATA[13]      ; 23.875 ;        ;        ; 23.875 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 21.778 ; 21.778 ; 21.778 ; 21.778 ;
; LPT_D[5]     ; RAM_DATA[13]  ; 20.565 ;        ;        ; 20.565 ;
; LPT_D[6]     ; DATA[6]       ; 25.178 ; 25.178 ; 25.178 ; 25.178 ;
; LPT_D[6]     ; DATA[14]      ; 24.375 ; 24.375 ; 24.375 ; 24.375 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 24.702 ; 24.702 ; 24.702 ; 24.702 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 21.799 ; 21.799 ; 21.799 ; 21.799 ;
; LPT_D[7]     ; DATA[7]       ; 23.518 ; 23.518 ; 23.518 ; 23.518 ;
; LPT_D[7]     ; DATA[15]      ; 24.533 ; 24.533 ; 24.533 ; 24.533 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 22.453 ; 22.453 ; 22.453 ; 22.453 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 21.509 ; 21.509 ; 21.509 ; 21.509 ;
; MIDI_IN      ; MIDI_TLR      ; 8.877  ;        ;        ; 8.877  ;
; RAM_DATA[0]  ; DATA[0]       ; 26.884 ;        ;        ; 26.884 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 22.273 ;        ;        ; 22.273 ;
; RAM_DATA[1]  ; DATA[1]       ; 24.806 ;        ;        ; 24.806 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 22.863 ;        ;        ; 22.863 ;
; RAM_DATA[2]  ; DATA[2]       ; 23.683 ;        ;        ; 23.683 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 21.395 ;        ;        ; 21.395 ;
; RAM_DATA[3]  ; DATA[3]       ; 24.444 ;        ;        ; 24.444 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 21.968 ;        ;        ; 21.968 ;
; RAM_DATA[4]  ; DATA[4]       ; 21.575 ; 21.575 ; 21.575 ; 21.575 ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 22.131 ; 22.131 ; 22.131 ; 22.131 ;
; RAM_DATA[5]  ; DATA[5]       ; 25.171 ; 25.171 ; 25.171 ; 25.171 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 21.809 ; 21.809 ; 21.809 ; 21.809 ;
; RAM_DATA[6]  ; DATA[6]       ; 26.141 ; 26.141 ; 26.141 ; 26.141 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 25.665 ; 25.665 ; 25.665 ; 25.665 ;
; RAM_DATA[7]  ; DATA[7]       ; 22.325 ; 22.325 ; 22.325 ; 22.325 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 21.260 ; 21.260 ; 21.260 ; 21.260 ;
; RAM_DATA[8]  ; DATA[8]       ; 23.154 ;        ;        ; 23.154 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 21.793 ;        ;        ; 21.793 ;
; RAM_DATA[9]  ; DATA[9]       ; 23.861 ;        ;        ; 23.861 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 21.995 ;        ;        ; 21.995 ;
; RAM_DATA[10] ; DATA[10]      ; 23.206 ;        ;        ; 23.206 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 22.935 ;        ;        ; 22.935 ;
; RAM_DATA[11] ; DATA[11]      ; 26.329 ;        ;        ; 26.329 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 22.117 ;        ;        ; 22.117 ;
; RAM_DATA[12] ; DATA[12]      ; 25.925 ;        ;        ; 25.925 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 25.744 ;        ;        ; 25.744 ;
; RAM_DATA[13] ; DATA[13]      ; 25.900 ;        ;        ; 25.900 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 22.590 ;        ;        ; 22.590 ;
; RAM_DATA[14] ; DATA[14]      ; 25.651 ; 25.651 ; 25.651 ; 25.651 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 23.075 ; 23.075 ; 23.075 ; 23.075 ;
; RAM_DATA[15] ; DATA[15]      ; 26.410 ; 26.410 ; 26.410 ; 26.410 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 23.386 ; 23.386 ; 23.386 ; 23.386 ;
; RWn          ; ACSI_RDn      ; 17.106 ; 17.106 ; 17.106 ; 17.106 ;
; RWn          ; ACSI_WRn      ; 17.096 ; 17.096 ; 17.096 ; 17.096 ;
; RWn          ; ASn           ; 25.644 ; 25.644 ; 25.644 ; 25.644 ;
; RWn          ; BUTTONn       ;        ; 21.271 ; 21.271 ;        ;
; RWn          ; CA1_OUT       ;        ; 14.970 ; 14.970 ;        ;
; RWn          ; CD[0]         ; 22.937 ; 22.937 ; 22.937 ; 22.937 ;
; RWn          ; CD[1]         ; 22.422 ; 22.422 ; 22.422 ; 22.422 ;
; RWn          ; CD[2]         ; 21.863 ; 21.863 ; 21.863 ; 21.863 ;
; RWn          ; CD[3]         ; 23.402 ; 23.402 ; 23.402 ; 23.402 ;
; RWn          ; CD[4]         ; 22.344 ; 22.344 ; 22.344 ; 22.344 ;
; RWn          ; CD[5]         ; 21.508 ; 21.508 ; 21.508 ; 21.508 ;
; RWn          ; CD[6]         ; 24.182 ; 24.182 ; 24.182 ; 24.182 ;
; RWn          ; CD[7]         ; 21.861 ; 21.861 ; 21.861 ; 21.861 ;
; RWn          ; DATA[0]       ; 40.383 ; 41.014 ; 41.014 ; 40.383 ;
; RWn          ; DATA[1]       ; 39.852 ; 39.852 ; 39.852 ; 39.852 ;
; RWn          ; DATA[2]       ; 38.755 ; 38.755 ; 38.755 ; 38.755 ;
; RWn          ; DATA[3]       ; 41.012 ; 41.012 ; 41.012 ; 41.012 ;
; RWn          ; DATA[4]       ; 37.238 ; 37.238 ; 37.238 ; 37.238 ;
; RWn          ; DATA[5]       ; 39.346 ; 39.346 ; 39.346 ; 39.346 ;
; RWn          ; DATA[6]       ; 36.879 ; 36.879 ; 36.879 ; 36.879 ;
; RWn          ; DATA[7]       ; 39.419 ; 39.419 ; 39.419 ; 39.419 ;
; RWn          ; DATA[8]       ; 38.607 ; 38.607 ; 38.607 ; 38.607 ;
; RWn          ; DATA[9]       ; 39.385 ; 39.385 ; 39.385 ; 39.385 ;
; RWn          ; DATA[10]      ; 39.468 ; 39.468 ; 39.468 ; 39.468 ;
; RWn          ; DATA[11]      ; 40.935 ; 40.935 ; 40.935 ; 40.935 ;
; RWn          ; DATA[12]      ; 39.524 ; 39.524 ; 39.524 ; 39.524 ;
; RWn          ; DATA[13]      ; 40.158 ; 40.717 ; 40.717 ; 40.158 ;
; RWn          ; DATA[14]      ; 39.419 ; 39.419 ; 39.419 ; 39.419 ;
; RWn          ; DATA[15]      ; 40.144 ; 40.144 ; 40.144 ; 40.144 ;
; RWn          ; DTACKn        ; 30.748 ; 30.748 ; 30.748 ; 30.748 ;
; RWn          ; FC[0]         ; 26.523 ; 26.523 ; 26.523 ; 26.523 ;
; RWn          ; FC[1]         ; 25.983 ; 25.983 ; 25.983 ; 25.983 ;
; RWn          ; FC[2]         ; 25.983 ; 25.983 ; 25.983 ; 25.983 ;
; RWn          ; FLASH_CEn     ;        ; 24.017 ; 24.017 ;        ;
; RWn          ; FLASH_OEn     ;        ; 25.236 ; 25.236 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 19.342 ; 19.342 ;        ;
; RWn          ; IDE_D_EN_OUTn ; 18.808 ;        ;        ; 18.808 ;
; RWn          ; IDE_IORDn     ;        ; 18.992 ; 18.992 ;        ;
; RWn          ; IDE_IOWRn     ; 19.035 ;        ;        ; 19.035 ;
; RWn          ; JOY_RHn       ; 20.869 ; 20.869 ; 20.869 ; 20.869 ;
; RWn          ; JOY_RLn       ; 22.898 ; 22.898 ; 22.898 ; 22.898 ;
; RWn          ; JOY_WEn       ; 22.868 ; 22.868 ; 22.868 ; 22.868 ;
; RWn          ; JOY_WL        ; 19.912 ; 19.912 ; 19.912 ; 19.912 ;
; RWn          ; LDSn          ; 26.947 ; 26.947 ; 26.947 ; 26.947 ;
; RWn          ; RAM_DATA[0]   ; 35.772 ; 36.403 ; 36.403 ; 35.772 ;
; RWn          ; RAM_DATA[1]   ; 37.909 ; 37.909 ; 37.909 ; 37.909 ;
; RWn          ; RAM_DATA[2]   ; 36.467 ; 36.467 ; 36.467 ; 36.467 ;
; RWn          ; RAM_DATA[3]   ; 38.536 ; 38.536 ; 38.536 ; 38.536 ;
; RWn          ; RAM_DATA[4]   ; 37.794 ; 37.794 ; 37.794 ; 37.794 ;
; RWn          ; RAM_DATA[5]   ; 35.984 ; 35.984 ; 35.984 ; 35.984 ;
; RWn          ; RAM_DATA[6]   ; 36.403 ; 36.403 ; 36.403 ; 36.403 ;
; RWn          ; RAM_DATA[7]   ; 38.354 ; 38.354 ; 38.354 ; 38.354 ;
; RWn          ; RAM_DATA[8]   ; 37.246 ; 37.246 ; 37.246 ; 37.246 ;
; RWn          ; RAM_DATA[9]   ; 37.519 ; 37.519 ; 37.519 ; 37.519 ;
; RWn          ; RAM_DATA[10]  ; 39.197 ; 39.197 ; 39.197 ; 39.197 ;
; RWn          ; RAM_DATA[11]  ; 36.723 ; 36.723 ; 36.723 ; 36.723 ;
; RWn          ; RAM_DATA[12]  ; 39.343 ; 39.343 ; 39.343 ; 39.343 ;
; RWn          ; RAM_DATA[13]  ; 36.848 ; 37.407 ; 37.407 ; 36.848 ;
; RWn          ; RAM_DATA[14]  ; 36.843 ; 36.843 ; 36.843 ; 36.843 ;
; RWn          ; RAM_DATA[15]  ; 37.120 ; 37.120 ; 37.120 ; 37.120 ;
; RWn          ; RAM_DQM0H     ;        ; 18.959 ; 18.959 ;        ;
; RWn          ; RAM_DQM0L     ;        ; 17.328 ; 17.328 ;        ;
; RWn          ; RAM_DQM1H     ;        ; 19.152 ; 19.152 ;        ;
; RWn          ; RAM_DQM1L     ;        ; 17.318 ; 17.318 ;        ;
; RWn          ; RAM_WEn       ; 20.396 ;        ;        ; 20.396 ;
; RWn          ; ROM0n         ;        ; 21.254 ; 21.254 ;        ;
; RWn          ; ROM1n         ;        ; 22.891 ; 22.891 ;        ;
; RWn          ; ROM2n         ;        ; 22.055 ; 22.055 ;        ;
; RWn          ; ROM3n         ;        ; 21.025 ; 21.025 ;        ;
; RWn          ; ROM4n         ;        ; 20.390 ; 20.390 ;        ;
; RWn          ; ROM5n         ;        ; 22.577 ; 22.577 ;        ;
; RWn          ; ROM6n         ;        ; 21.357 ; 21.357 ;        ;
; RWn          ; RWn           ; 27.239 ; 27.239 ; 27.239 ; 27.239 ;
; RWn          ; UDSn          ; 26.947 ; 26.947 ; 26.947 ; 26.947 ;
; SCSI_ACKn    ; CD[0]         ; 17.047 ; 17.047 ; 17.047 ; 17.047 ;
; SCSI_ATNn    ; CD[1]         ; 18.828 ; 18.828 ; 18.828 ; 18.828 ;
; SCSI_BSYn    ; CD[6]         ;        ; 14.677 ; 14.677 ;        ;
; SCSI_D[0]    ; CD[0]         ; 18.516 ; 18.516 ; 18.516 ; 18.516 ;
; SCSI_D[1]    ; CD[1]         ; 17.833 ; 17.833 ; 17.833 ; 17.833 ;
; SCSI_D[2]    ; CD[2]         ;        ; 16.505 ; 16.505 ;        ;
; SCSI_D[3]    ; CD[3]         ; 19.369 ; 19.369 ; 19.369 ; 19.369 ;
; SCSI_D[4]    ; CD[4]         ; 13.423 ; 13.423 ; 13.423 ; 13.423 ;
; SCSI_D[5]    ; CD[5]         ; 12.859 ; 12.859 ; 12.859 ; 12.859 ;
; SCSI_D[6]    ; CD[6]         ; 16.352 ; 16.352 ; 16.352 ; 16.352 ;
; SCSI_D[7]    ; CD[7]         ;        ; 16.836 ; 16.836 ;        ;
; SCSI_DCn     ; CD[3]         ; 19.850 ; 19.850 ; 19.850 ; 19.850 ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 15.389 ; 15.389 ; 15.389 ; 15.389 ;
; SCSI_DCn     ; SCSI_D[0]     ; 17.015 ; 17.015 ; 17.015 ; 17.015 ;
; SCSI_DCn     ; SCSI_D[1]     ; 17.015 ; 17.015 ; 17.015 ; 17.015 ;
; SCSI_DCn     ; SCSI_D[2]     ; 17.219 ; 17.219 ; 17.219 ; 17.219 ;
; SCSI_DCn     ; SCSI_D[3]     ; 17.219 ; 17.219 ; 17.219 ; 17.219 ;
; SCSI_DCn     ; SCSI_D[4]     ; 17.242 ; 17.242 ; 17.242 ; 17.242 ;
; SCSI_DCn     ; SCSI_D[5]     ; 17.242 ; 17.242 ; 17.242 ; 17.242 ;
; SCSI_DCn     ; SCSI_D[6]     ; 17.252 ; 17.252 ; 17.252 ; 17.252 ;
; SCSI_DCn     ; SCSI_D[7]     ; 17.252 ; 17.252 ; 17.252 ; 17.252 ;
; SCSI_DCn     ; SCSI_DP       ; 17.025 ; 17.025 ; 17.025 ; 17.025 ;
; SCSI_DP      ; CD[0]         ; 17.420 ; 17.420 ; 17.420 ; 17.420 ;
; SCSI_IOn     ; CD[2]         ;        ; 16.223 ; 16.223 ;        ;
; SCSI_IOn     ; CD[3]         ; 20.247 ; 20.247 ; 20.247 ; 20.247 ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 15.786 ; 15.786 ; 15.786 ; 15.786 ;
; SCSI_IOn     ; SCSI_D[0]     ; 17.412 ; 17.412 ; 17.412 ; 17.412 ;
; SCSI_IOn     ; SCSI_D[1]     ; 17.412 ; 17.412 ; 17.412 ; 17.412 ;
; SCSI_IOn     ; SCSI_D[2]     ; 17.616 ; 17.616 ; 17.616 ; 17.616 ;
; SCSI_IOn     ; SCSI_D[3]     ; 17.616 ; 17.616 ; 17.616 ; 17.616 ;
; SCSI_IOn     ; SCSI_D[4]     ; 17.639 ; 17.639 ; 17.639 ; 17.639 ;
; SCSI_IOn     ; SCSI_D[5]     ; 17.639 ; 17.639 ; 17.639 ; 17.639 ;
; SCSI_IOn     ; SCSI_D[6]     ; 17.649 ; 17.649 ; 17.649 ; 17.649 ;
; SCSI_IOn     ; SCSI_D[7]     ; 17.649 ; 17.649 ; 17.649 ; 17.649 ;
; SCSI_IOn     ; SCSI_DP       ; 17.422 ; 17.422 ; 17.422 ; 17.422 ;
; SCSI_IOn     ; SCSI_RDn      ; 12.208 ;        ;        ; 12.208 ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 12.176 ; 12.176 ;        ;
; SCSI_MSGn    ; CD[3]         ; 19.442 ; 19.442 ; 19.442 ; 19.442 ;
; SCSI_MSGn    ; CD[4]         ;        ; 12.341 ; 12.341 ;        ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 14.981 ; 14.981 ; 14.981 ; 14.981 ;
; SCSI_MSGn    ; SCSI_D[0]     ; 16.607 ; 16.607 ; 16.607 ; 16.607 ;
; SCSI_MSGn    ; SCSI_D[1]     ; 16.607 ; 16.607 ; 16.607 ; 16.607 ;
; SCSI_MSGn    ; SCSI_D[2]     ; 16.811 ; 16.811 ; 16.811 ; 16.811 ;
; SCSI_MSGn    ; SCSI_D[3]     ; 16.811 ; 16.811 ; 16.811 ; 16.811 ;
; SCSI_MSGn    ; SCSI_D[4]     ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; SCSI_MSGn    ; SCSI_D[5]     ; 16.834 ; 16.834 ; 16.834 ; 16.834 ;
; SCSI_MSGn    ; SCSI_D[6]     ; 16.844 ; 16.844 ; 16.844 ; 16.844 ;
; SCSI_MSGn    ; SCSI_D[7]     ; 16.844 ; 16.844 ; 16.844 ; 16.844 ;
; SCSI_MSGn    ; SCSI_DP       ; 16.617 ; 16.617 ; 16.617 ; 16.617 ;
; SCSI_REQn    ; CD[3]         ; 19.496 ; 19.496 ; 19.496 ; 19.496 ;
; SCSI_REQn    ; CD[5]         ;        ; 12.083 ; 12.083 ;        ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 15.035 ;        ;        ; 15.035 ;
; SCSI_REQn    ; SCSI_D[0]     ; 16.661 ; 16.661 ; 16.661 ; 16.661 ;
; SCSI_REQn    ; SCSI_D[1]     ; 16.661 ; 16.661 ; 16.661 ; 16.661 ;
; SCSI_REQn    ; SCSI_D[2]     ; 16.865 ; 16.865 ; 16.865 ; 16.865 ;
; SCSI_REQn    ; SCSI_D[3]     ; 16.865 ; 16.865 ; 16.865 ; 16.865 ;
; SCSI_REQn    ; SCSI_D[4]     ; 16.888 ; 16.888 ; 16.888 ; 16.888 ;
; SCSI_REQn    ; SCSI_D[5]     ; 16.888 ; 16.888 ; 16.888 ; 16.888 ;
; SCSI_REQn    ; SCSI_D[6]     ; 16.898 ; 16.898 ; 16.898 ; 16.898 ;
; SCSI_REQn    ; SCSI_D[7]     ; 16.898 ; 16.898 ; 16.898 ; 16.898 ;
; SCSI_REQn    ; SCSI_DP       ; 16.671 ; 16.671 ; 16.671 ; 16.671 ;
; SCSI_RSTn    ; CD[7]         ;        ; 15.894 ; 15.894 ;        ;
; SCSI_SELn    ; CD[1]         ; 17.164 ; 17.164 ; 17.164 ; 17.164 ;
; SD_AVR_ENn   ; RESETn        ;        ; 14.448 ; 14.448 ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 14.563 ; 14.563 ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 14.608 ; 14.608 ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 12.038 ;        ;        ; 12.038 ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 12.534 ;        ;        ; 12.534 ;
; SD_RESETn    ; COM_TxD       ; 17.660 ; 17.660 ; 17.660 ; 17.660 ;
; UDSn         ; ACSI_RDn      ; 19.826 ; 19.826 ; 19.826 ; 19.826 ;
; UDSn         ; ACSI_WRn      ; 19.816 ; 19.816 ; 19.816 ; 19.816 ;
; UDSn         ; ASn           ; 27.851 ; 27.851 ; 27.851 ; 27.851 ;
; UDSn         ; CA1_OUT       ; 17.690 ;        ;        ; 17.690 ;
; UDSn         ; CD[0]         ; 25.657 ; 25.657 ; 25.657 ; 25.657 ;
; UDSn         ; CD[1]         ; 25.142 ; 25.142 ; 25.142 ; 25.142 ;
; UDSn         ; CD[2]         ; 24.583 ; 24.583 ; 24.583 ; 24.583 ;
; UDSn         ; CD[3]         ; 26.122 ; 26.122 ; 26.122 ; 26.122 ;
; UDSn         ; CD[4]         ; 25.064 ; 25.064 ; 25.064 ; 25.064 ;
; UDSn         ; CD[5]         ; 24.228 ; 24.228 ; 24.228 ; 24.228 ;
; UDSn         ; CD[6]         ; 26.902 ; 26.902 ; 26.902 ; 26.902 ;
; UDSn         ; CD[7]         ; 24.581 ; 24.581 ; 24.581 ; 24.581 ;
; UDSn         ; DATA[0]       ; 39.108 ; 39.108 ; 39.108 ; 39.108 ;
; UDSn         ; DATA[1]       ; 39.094 ; 39.094 ; 39.094 ; 39.094 ;
; UDSn         ; DATA[2]       ; 38.116 ; 38.116 ; 38.116 ; 38.116 ;
; UDSn         ; DATA[3]       ; 37.784 ; 38.142 ; 38.142 ; 37.784 ;
; UDSn         ; DATA[4]       ; 37.132 ; 37.132 ; 37.132 ; 37.132 ;
; UDSn         ; DATA[5]       ; 40.419 ; 40.419 ; 40.419 ; 40.419 ;
; UDSn         ; DATA[6]       ; 37.985 ; 37.985 ; 37.985 ; 37.985 ;
; UDSn         ; DATA[7]       ; 38.267 ; 38.267 ; 38.267 ; 38.267 ;
; UDSn         ; DATA[8]       ; 37.873 ; 37.873 ; 37.873 ; 37.873 ;
; UDSn         ; DATA[9]       ; 39.129 ; 38.820 ; 38.820 ; 39.129 ;
; UDSn         ; DATA[10]      ; 39.464 ; 39.464 ; 39.464 ; 39.464 ;
; UDSn         ; DATA[11]      ; 42.190 ; 41.471 ; 41.471 ; 42.190 ;
; UDSn         ; DATA[12]      ; 37.749 ; 36.540 ; 36.540 ; 37.749 ;
; UDSn         ; DATA[13]      ; 39.130 ; 38.549 ; 38.549 ; 39.130 ;
; UDSn         ; DATA[14]      ; 37.567 ; 37.567 ; 37.567 ; 37.567 ;
; UDSn         ; DATA[15]      ; 38.472 ; 38.472 ; 38.472 ; 38.472 ;
; UDSn         ; DTACKn        ; 28.203 ; 28.203 ; 28.203 ; 28.203 ;
; UDSn         ; FC[0]         ; 28.730 ; 28.730 ; 28.730 ; 28.730 ;
; UDSn         ; FC[1]         ; 28.190 ; 28.190 ; 28.190 ; 28.190 ;
; UDSn         ; FC[2]         ; 28.190 ; 28.190 ; 28.190 ; 28.190 ;
; UDSn         ; JOY_RHn       ; 16.263 ;        ;        ; 16.263 ;
; UDSn         ; LDSn          ; 29.154 ; 29.154 ; 29.154 ; 29.154 ;
; UDSn         ; RAM_CAS0n     ; 20.534 ;        ;        ; 20.534 ;
; UDSn         ; RAM_CAS1n     ; 19.716 ;        ;        ; 19.716 ;
; UDSn         ; RAM_DATA[0]   ; 34.497 ; 34.497 ; 34.497 ; 34.497 ;
; UDSn         ; RAM_DATA[1]   ; 37.151 ; 37.151 ; 37.151 ; 37.151 ;
; UDSn         ; RAM_DATA[2]   ; 35.828 ; 35.828 ; 35.828 ; 35.828 ;
; UDSn         ; RAM_DATA[3]   ; 35.308 ; 35.666 ; 35.666 ; 35.308 ;
; UDSn         ; RAM_DATA[4]   ; 37.688 ; 37.688 ; 37.688 ; 37.688 ;
; UDSn         ; RAM_DATA[5]   ; 37.057 ; 37.057 ; 37.057 ; 37.057 ;
; UDSn         ; RAM_DATA[6]   ; 37.509 ; 37.509 ; 37.509 ; 37.509 ;
; UDSn         ; RAM_DATA[7]   ; 37.202 ; 37.202 ; 37.202 ; 37.202 ;
; UDSn         ; RAM_DATA[8]   ; 36.512 ; 36.512 ; 36.512 ; 36.512 ;
; UDSn         ; RAM_DATA[9]   ; 37.263 ; 36.954 ; 36.954 ; 37.263 ;
; UDSn         ; RAM_DATA[10]  ; 39.193 ; 39.193 ; 39.193 ; 39.193 ;
; UDSn         ; RAM_DATA[11]  ; 37.978 ; 37.259 ; 37.259 ; 37.978 ;
; UDSn         ; RAM_DATA[12]  ; 37.568 ; 36.359 ; 36.359 ; 37.568 ;
; UDSn         ; RAM_DATA[13]  ; 35.820 ; 35.239 ; 35.239 ; 35.820 ;
; UDSn         ; RAM_DATA[14]  ; 34.991 ; 34.991 ; 34.991 ; 34.991 ;
; UDSn         ; RAM_DATA[15]  ; 35.448 ; 35.448 ; 35.448 ; 35.448 ;
; UDSn         ; RAM_DQM0H     ; 25.446 ; 25.016 ; 25.016 ; 25.446 ;
; UDSn         ; RAM_DQM0L     ; 23.765 ; 23.386 ; 23.386 ; 23.765 ;
; UDSn         ; RAM_DQM1H     ; 25.639 ; 25.209 ; 25.209 ; 25.639 ;
; UDSn         ; RAM_DQM1L     ; 23.755 ; 23.376 ; 23.376 ; 23.755 ;
; UDSn         ; RWn           ; 29.446 ; 29.446 ; 29.446 ; 29.446 ;
; UDSn         ; UDSn          ; 29.154 ; 29.154 ; 29.154 ; 29.154 ;
+--------------+---------------+--------+--------+--------+--------+


+------------------------------------------------------------------+
; Minimum Progagation Delay                                        ;
+--------------+---------------+--------+--------+--------+--------+
; Input Port   ; Output Port   ; RR     ; RF     ; FR     ; FF     ;
+--------------+---------------+--------+--------+--------+--------+
; ADR[1]       ; DATA[0]       ; 11.432 ; 11.432 ; 11.432 ; 11.432 ;
; ADR[1]       ; DATA[1]       ; 11.044 ; 11.044 ; 11.044 ; 11.044 ;
; ADR[1]       ; DATA[2]       ; 10.838 ; 10.757 ; 10.757 ; 10.838 ;
; ADR[1]       ; DATA[3]       ; 11.211 ; 11.570 ; 11.570 ; 11.211 ;
; ADR[1]       ; DATA[4]       ; 10.228 ; 10.228 ; 10.228 ; 10.228 ;
; ADR[1]       ; DATA[5]       ; 11.343 ; 11.343 ; 11.343 ; 11.343 ;
; ADR[1]       ; DATA[6]       ; 10.463 ; 10.463 ; 10.463 ; 10.463 ;
; ADR[1]       ; DATA[7]       ; 11.040 ; 11.040 ; 11.040 ; 11.040 ;
; ADR[1]       ; DATA[8]       ; 10.629 ; 10.629 ; 10.629 ; 10.629 ;
; ADR[1]       ; DATA[9]       ; 10.487 ; 10.487 ; 10.487 ; 10.487 ;
; ADR[1]       ; DATA[10]      ; 10.819 ; 10.738 ; 10.738 ; 10.819 ;
; ADR[1]       ; DATA[11]      ; 11.902 ; 11.608 ; 11.608 ; 11.902 ;
; ADR[1]       ; DATA[12]      ; 10.953 ; 10.953 ; 10.953 ; 10.953 ;
; ADR[1]       ; DATA[13]      ; 11.237 ; 11.236 ; 11.236 ; 11.237 ;
; ADR[1]       ; DATA[14]      ; 11.299 ; 11.299 ; 11.299 ; 11.299 ;
; ADR[1]       ; DATA[15]      ; 11.380 ; 11.380 ; 11.380 ; 11.380 ;
; ADR[1]       ; RAM_DATA[0]   ; 9.611  ; 9.611  ; 9.611  ; 9.611  ;
; ADR[1]       ; RAM_DATA[1]   ; 10.129 ; 10.129 ; 10.129 ; 10.129 ;
; ADR[1]       ; RAM_DATA[2]   ; 9.995  ; 9.914  ; 9.914  ; 9.995  ;
; ADR[1]       ; RAM_DATA[3]   ; 10.308 ; 10.667 ; 10.667 ; 10.308 ;
; ADR[1]       ; RAM_DATA[4]   ; 10.357 ; 10.357 ; 10.357 ; 10.357 ;
; ADR[1]       ; RAM_DATA[5]   ; 10.002 ; 10.002 ; 10.002 ; 10.002 ;
; ADR[1]       ; RAM_DATA[6]   ; 10.294 ; 10.294 ; 10.294 ; 10.294 ;
; ADR[1]       ; RAM_DATA[7]   ; 10.722 ; 10.722 ; 10.722 ; 10.722 ;
; ADR[1]       ; RAM_DATA[8]   ; 10.240 ; 10.240 ; 10.240 ; 10.240 ;
; ADR[1]       ; RAM_DATA[9]   ; 9.858  ; 9.858  ; 9.858  ; 9.858  ;
; ADR[1]       ; RAM_DATA[10]  ; 10.956 ; 10.875 ; 10.875 ; 10.956 ;
; ADR[1]       ; RAM_DATA[11]  ; 10.267 ; 9.973  ; 9.973  ; 10.267 ;
; ADR[1]       ; RAM_DATA[12]  ; 11.017 ; 11.017 ; 11.017 ; 11.017 ;
; ADR[1]       ; RAM_DATA[13]  ; 10.088 ; 10.087 ; 10.087 ; 10.088 ;
; ADR[1]       ; RAM_DATA[14]  ; 10.415 ; 10.415 ; 10.415 ; 10.415 ;
; ADR[1]       ; RAM_DATA[15]  ; 10.338 ; 10.338 ; 10.338 ; 10.338 ;
; ADR[2]       ; DATA[0]       ; 11.523 ; 11.823 ; 11.823 ; 11.523 ;
; ADR[2]       ; DATA[1]       ; 11.513 ; 11.597 ; 11.597 ; 11.513 ;
; ADR[2]       ; DATA[2]       ; 11.280 ; 11.212 ; 11.212 ; 11.280 ;
; ADR[2]       ; DATA[3]       ; 11.665 ; 12.025 ; 12.025 ; 11.665 ;
; ADR[2]       ; DATA[4]       ; 10.606 ; 10.606 ; 10.606 ; 10.606 ;
; ADR[2]       ; DATA[5]       ; 11.095 ; 11.095 ; 11.095 ; 11.095 ;
; ADR[2]       ; DATA[6]       ; 10.707 ; 10.707 ; 10.707 ; 10.707 ;
; ADR[2]       ; DATA[7]       ; 11.494 ; 11.494 ; 11.494 ; 11.494 ;
; ADR[2]       ; DATA[8]       ; 10.720 ; 11.020 ; 11.020 ; 10.720 ;
; ADR[2]       ; DATA[9]       ; 10.956 ; 11.040 ; 11.040 ; 10.956 ;
; ADR[2]       ; DATA[10]      ; 11.261 ; 11.193 ; 11.193 ; 11.261 ;
; ADR[2]       ; DATA[11]      ; 12.254 ; 12.063 ; 12.063 ; 12.254 ;
; ADR[2]       ; DATA[12]      ; 11.331 ; 11.405 ; 11.405 ; 11.331 ;
; ADR[2]       ; DATA[13]      ; 10.989 ; 10.989 ; 10.989 ; 10.989 ;
; ADR[2]       ; DATA[14]      ; 11.543 ; 11.543 ; 11.543 ; 11.543 ;
; ADR[2]       ; DATA[15]      ; 11.744 ; 11.744 ; 11.744 ; 11.744 ;
; ADR[2]       ; RAM_DATA[0]   ; 9.702  ; 10.002 ; 10.002 ; 9.702  ;
; ADR[2]       ; RAM_DATA[1]   ; 10.598 ; 10.682 ; 10.682 ; 10.598 ;
; ADR[2]       ; RAM_DATA[2]   ; 10.437 ; 10.369 ; 10.369 ; 10.437 ;
; ADR[2]       ; RAM_DATA[3]   ; 10.762 ; 11.122 ; 11.122 ; 10.762 ;
; ADR[2]       ; RAM_DATA[4]   ; 10.735 ; 10.735 ; 10.735 ; 10.735 ;
; ADR[2]       ; RAM_DATA[5]   ; 9.754  ; 9.754  ; 9.754  ; 9.754  ;
; ADR[2]       ; RAM_DATA[6]   ; 10.538 ; 10.538 ; 10.538 ; 10.538 ;
; ADR[2]       ; RAM_DATA[7]   ; 11.176 ; 11.176 ; 11.176 ; 11.176 ;
; ADR[2]       ; RAM_DATA[8]   ; 10.331 ; 10.631 ; 10.631 ; 10.331 ;
; ADR[2]       ; RAM_DATA[9]   ; 10.327 ; 10.411 ; 10.411 ; 10.327 ;
; ADR[2]       ; RAM_DATA[10]  ; 11.398 ; 11.330 ; 11.330 ; 11.398 ;
; ADR[2]       ; RAM_DATA[11]  ; 10.619 ; 10.428 ; 10.428 ; 10.619 ;
; ADR[2]       ; RAM_DATA[12]  ; 11.395 ; 11.469 ; 11.469 ; 11.395 ;
; ADR[2]       ; RAM_DATA[13]  ; 9.840  ; 9.840  ; 9.840  ; 9.840  ;
; ADR[2]       ; RAM_DATA[14]  ; 10.659 ; 10.659 ; 10.659 ; 10.659 ;
; ADR[2]       ; RAM_DATA[15]  ; 10.702 ; 10.702 ; 10.702 ; 10.702 ;
; ADR[3]       ; DATA[0]       ; 11.456 ; 11.456 ; 11.456 ; 11.456 ;
; ADR[3]       ; DATA[1]       ; 11.370 ; 11.221 ; 11.221 ; 11.370 ;
; ADR[3]       ; DATA[2]       ; 10.776 ; 10.680 ; 10.680 ; 10.776 ;
; ADR[3]       ; DATA[3]       ; 11.173 ; 11.171 ; 11.171 ; 11.173 ;
; ADR[3]       ; DATA[4]       ; 10.226 ; 10.226 ; 10.226 ; 10.226 ;
; ADR[3]       ; DATA[5]       ; 11.330 ; 11.330 ; 11.330 ; 11.330 ;
; ADR[3]       ; DATA[6]       ; 10.258 ; 10.258 ; 10.258 ; 10.258 ;
; ADR[3]       ; DATA[7]       ; 11.000 ; 11.000 ; 11.000 ; 11.000 ;
; ADR[3]       ; DATA[8]       ; 10.653 ; 10.653 ; 10.653 ; 10.653 ;
; ADR[3]       ; DATA[9]       ; 10.859 ; 10.664 ; 10.664 ; 10.859 ;
; ADR[3]       ; DATA[10]      ; 10.757 ; 10.661 ; 10.661 ; 10.757 ;
; ADR[3]       ; DATA[11]      ; 11.646 ; 11.562 ; 11.562 ; 11.646 ;
; ADR[3]       ; DATA[12]      ; 11.042 ; 10.951 ; 10.951 ; 11.042 ;
; ADR[3]       ; DATA[13]      ; 11.196 ; 11.198 ; 11.198 ; 11.196 ;
; ADR[3]       ; DATA[14]      ; 11.094 ; 11.094 ; 11.094 ; 11.094 ;
; ADR[3]       ; DATA[15]      ; 11.182 ; 11.182 ; 11.182 ; 11.182 ;
; ADR[3]       ; RAM_DATA[0]   ; 9.635  ; 9.635  ; 9.635  ; 9.635  ;
; ADR[3]       ; RAM_DATA[1]   ; 10.455 ; 10.306 ; 10.306 ; 10.455 ;
; ADR[3]       ; RAM_DATA[2]   ; 9.933  ; 9.837  ; 9.837  ; 9.933  ;
; ADR[3]       ; RAM_DATA[3]   ; 10.270 ; 10.268 ; 10.268 ; 10.270 ;
; ADR[3]       ; RAM_DATA[4]   ; 10.355 ; 10.355 ; 10.355 ; 10.355 ;
; ADR[3]       ; RAM_DATA[5]   ; 9.989  ; 9.989  ; 9.989  ; 9.989  ;
; ADR[3]       ; RAM_DATA[6]   ; 10.089 ; 10.089 ; 10.089 ; 10.089 ;
; ADR[3]       ; RAM_DATA[7]   ; 10.682 ; 10.682 ; 10.682 ; 10.682 ;
; ADR[3]       ; RAM_DATA[8]   ; 10.264 ; 10.264 ; 10.264 ; 10.264 ;
; ADR[3]       ; RAM_DATA[9]   ; 10.230 ; 10.035 ; 10.035 ; 10.230 ;
; ADR[3]       ; RAM_DATA[10]  ; 10.894 ; 10.798 ; 10.798 ; 10.894 ;
; ADR[3]       ; RAM_DATA[11]  ; 10.011 ; 9.927  ; 9.927  ; 10.011 ;
; ADR[3]       ; RAM_DATA[12]  ; 11.106 ; 11.015 ; 11.015 ; 11.106 ;
; ADR[3]       ; RAM_DATA[13]  ; 10.047 ; 10.049 ; 10.049 ; 10.047 ;
; ADR[3]       ; RAM_DATA[14]  ; 10.210 ; 10.210 ; 10.210 ; 10.210 ;
; ADR[3]       ; RAM_DATA[15]  ; 10.140 ; 10.140 ; 10.140 ; 10.140 ;
; ADR[4]       ; DATA[0]       ; 11.605 ; 11.605 ; 11.605 ; 11.605 ;
; ADR[4]       ; DATA[1]       ; 11.150 ; 11.250 ; 11.250 ; 11.150 ;
; ADR[4]       ; DATA[2]       ; 10.561 ; 10.829 ; 10.829 ; 10.561 ;
; ADR[4]       ; DATA[3]       ; 11.265 ; 11.053 ; 11.053 ; 11.265 ;
; ADR[4]       ; DATA[4]       ; 10.388 ; 10.388 ; 10.388 ; 10.388 ;
; ADR[4]       ; DATA[5]       ; 11.334 ; 11.334 ; 11.334 ; 11.334 ;
; ADR[4]       ; DATA[6]       ; 10.267 ; 10.267 ; 10.267 ; 10.267 ;
; ADR[4]       ; DATA[7]       ; 10.882 ; 10.882 ; 10.882 ; 10.882 ;
; ADR[4]       ; DATA[8]       ; 10.802 ; 10.776 ; 10.776 ; 10.802 ;
; ADR[4]       ; DATA[9]       ; 10.593 ; 10.773 ; 10.773 ; 10.593 ;
; ADR[4]       ; DATA[10]      ; 10.542 ; 10.806 ; 10.806 ; 10.542 ;
; ADR[4]       ; DATA[11]      ; 11.412 ; 11.706 ; 11.706 ; 11.412 ;
; ADR[4]       ; DATA[12]      ; 10.924 ; 11.090 ; 11.090 ; 10.924 ;
; ADR[4]       ; DATA[13]      ; 11.078 ; 11.216 ; 11.216 ; 11.078 ;
; ADR[4]       ; DATA[14]      ; 11.103 ; 11.103 ; 11.103 ; 11.103 ;
; ADR[4]       ; DATA[15]      ; 11.222 ; 11.222 ; 11.222 ; 11.222 ;
; ADR[4]       ; RAM_DATA[0]   ; 9.784  ; 9.784  ; 9.784  ; 9.784  ;
; ADR[4]       ; RAM_DATA[1]   ; 10.235 ; 10.335 ; 10.335 ; 10.235 ;
; ADR[4]       ; RAM_DATA[2]   ; 9.718  ; 9.986  ; 9.986  ; 9.718  ;
; ADR[4]       ; RAM_DATA[3]   ; 10.362 ; 10.150 ; 10.150 ; 10.362 ;
; ADR[4]       ; RAM_DATA[4]   ; 10.517 ; 10.517 ; 10.517 ; 10.517 ;
; ADR[4]       ; RAM_DATA[5]   ; 9.993  ; 9.993  ; 9.993  ; 9.993  ;
; ADR[4]       ; RAM_DATA[6]   ; 10.098 ; 10.098 ; 10.098 ; 10.098 ;
; ADR[4]       ; RAM_DATA[7]   ; 10.564 ; 10.564 ; 10.564 ; 10.564 ;
; ADR[4]       ; RAM_DATA[8]   ; 10.413 ; 10.387 ; 10.387 ; 10.413 ;
; ADR[4]       ; RAM_DATA[9]   ; 9.964  ; 10.144 ; 10.144 ; 9.964  ;
; ADR[4]       ; RAM_DATA[10]  ; 10.679 ; 10.943 ; 10.943 ; 10.679 ;
; ADR[4]       ; RAM_DATA[11]  ; 9.777  ; 10.071 ; 10.071 ; 9.777  ;
; ADR[4]       ; RAM_DATA[12]  ; 10.988 ; 11.154 ; 11.154 ; 10.988 ;
; ADR[4]       ; RAM_DATA[13]  ; 9.929  ; 10.067 ; 10.067 ; 9.929  ;
; ADR[4]       ; RAM_DATA[14]  ; 10.219 ; 10.219 ; 10.219 ; 10.219 ;
; ADR[4]       ; RAM_DATA[15]  ; 10.180 ; 10.180 ; 10.180 ; 10.180 ;
; ADR[5]       ; DATA[0]       ; 11.722 ; 11.832 ; 11.832 ; 11.722 ;
; ADR[5]       ; DATA[1]       ; 11.293 ; 11.508 ; 11.508 ; 11.293 ;
; ADR[5]       ; DATA[2]       ; 11.040 ; 10.919 ; 10.919 ; 11.040 ;
; ADR[5]       ; DATA[3]       ; 11.096 ; 11.463 ; 11.463 ; 11.096 ;
; ADR[5]       ; DATA[4]       ; 10.703 ; 10.703 ; 10.703 ; 10.703 ;
; ADR[5]       ; DATA[5]       ; 11.405 ; 11.405 ; 11.405 ; 11.405 ;
; ADR[5]       ; DATA[6]       ; 10.558 ; 10.558 ; 10.558 ; 10.558 ;
; ADR[5]       ; DATA[7]       ; 10.925 ; 10.925 ; 10.925 ; 10.925 ;
; ADR[5]       ; DATA[8]       ; 10.819 ; 11.029 ; 11.029 ; 10.819 ;
; ADR[5]       ; DATA[9]       ; 11.131 ; 10.951 ; 10.951 ; 11.131 ;
; ADR[5]       ; DATA[10]      ; 10.849 ; 10.900 ; 10.900 ; 10.849 ;
; ADR[5]       ; DATA[11]      ; 12.064 ; 11.770 ; 11.770 ; 12.064 ;
; ADR[5]       ; DATA[12]      ; 11.133 ; 10.967 ; 10.967 ; 11.133 ;
; ADR[5]       ; DATA[13]      ; 11.259 ; 11.121 ; 11.121 ; 11.259 ;
; ADR[5]       ; DATA[14]      ; 11.240 ; 11.240 ; 11.240 ; 11.240 ;
; ADR[5]       ; DATA[15]      ; 11.265 ; 11.265 ; 11.265 ; 11.265 ;
; ADR[5]       ; RAM_DATA[0]   ; 9.901  ; 10.011 ; 10.011 ; 9.901  ;
; ADR[5]       ; RAM_DATA[1]   ; 10.378 ; 10.593 ; 10.593 ; 10.378 ;
; ADR[5]       ; RAM_DATA[2]   ; 10.197 ; 10.076 ; 10.076 ; 10.197 ;
; ADR[5]       ; RAM_DATA[3]   ; 10.193 ; 10.560 ; 10.560 ; 10.193 ;
; ADR[5]       ; RAM_DATA[4]   ; 10.832 ; 10.832 ; 10.832 ; 10.832 ;
; ADR[5]       ; RAM_DATA[5]   ; 10.064 ; 10.064 ; 10.064 ; 10.064 ;
; ADR[5]       ; RAM_DATA[6]   ; 10.389 ; 10.389 ; 10.389 ; 10.389 ;
; ADR[5]       ; RAM_DATA[7]   ; 10.607 ; 10.607 ; 10.607 ; 10.607 ;
; ADR[5]       ; RAM_DATA[8]   ; 10.430 ; 10.640 ; 10.640 ; 10.430 ;
; ADR[5]       ; RAM_DATA[9]   ; 10.502 ; 10.322 ; 10.322 ; 10.502 ;
; ADR[5]       ; RAM_DATA[10]  ; 10.986 ; 11.037 ; 11.037 ; 10.986 ;
; ADR[5]       ; RAM_DATA[11]  ; 10.429 ; 10.135 ; 10.135 ; 10.429 ;
; ADR[5]       ; RAM_DATA[12]  ; 11.197 ; 11.031 ; 11.031 ; 11.197 ;
; ADR[5]       ; RAM_DATA[13]  ; 10.110 ; 9.972  ; 9.972  ; 10.110 ;
; ADR[5]       ; RAM_DATA[14]  ; 10.356 ; 10.356 ; 10.356 ; 10.356 ;
; ADR[5]       ; RAM_DATA[15]  ; 10.223 ; 10.223 ; 10.223 ; 10.223 ;
; ASn          ; ACSI_RDn      ; 10.109 ; 10.109 ; 10.109 ; 10.109 ;
; ASn          ; ACSI_WRn      ; 10.099 ; 10.099 ; 10.099 ; 10.099 ;
; ASn          ; ASn           ; 10.471 ; 10.471 ; 10.471 ; 10.471 ;
; ASn          ; BUTTONn       ; 8.032  ;        ;        ; 8.032  ;
; ASn          ; CA1_OUT       ; 9.144  ;        ;        ; 9.144  ;
; ASn          ; CD[0]         ; 10.190 ; 10.190 ; 10.190 ; 10.190 ;
; ASn          ; CD[1]         ; 10.182 ; 10.182 ; 10.182 ; 10.182 ;
; ASn          ; CD[2]         ; 10.024 ; 10.024 ; 10.024 ; 10.024 ;
; ASn          ; CD[3]         ; 10.182 ; 10.182 ; 10.182 ; 10.182 ;
; ASn          ; CD[4]         ; 10.031 ; 10.031 ; 10.031 ; 10.031 ;
; ASn          ; CD[5]         ; 10.031 ; 10.031 ; 10.031 ; 10.031 ;
; ASn          ; CD[6]         ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; ASn          ; CD[7]         ; 10.000 ; 10.000 ; 10.000 ; 10.000 ;
; ASn          ; DATA[0]       ; 10.533 ; 10.533 ; 10.533 ; 10.533 ;
; ASn          ; DATA[1]       ; 10.533 ; 10.533 ; 10.533 ; 10.533 ;
; ASn          ; DATA[2]       ; 10.513 ; 10.513 ; 10.513 ; 10.513 ;
; ASn          ; DATA[3]       ; 10.513 ; 10.513 ; 10.513 ; 10.513 ;
; ASn          ; DATA[4]       ; 9.976  ; 9.976  ; 9.976  ; 9.976  ;
; ASn          ; DATA[5]       ; 10.427 ; 10.427 ; 10.427 ; 10.427 ;
; ASn          ; DATA[6]       ; 9.821  ; 9.821  ; 9.821  ; 9.821  ;
; ASn          ; DATA[7]       ; 10.081 ; 10.081 ; 10.081 ; 10.081 ;
; ASn          ; DATA[8]       ; 10.225 ; 10.225 ; 10.225 ; 10.225 ;
; ASn          ; DATA[9]       ; 10.346 ; 10.346 ; 10.346 ; 10.346 ;
; ASn          ; DATA[10]      ; 10.369 ; 10.371 ; 10.371 ; 10.369 ;
; ASn          ; DATA[11]      ; 10.371 ; 10.371 ; 10.371 ; 10.371 ;
; ASn          ; DATA[12]      ; 10.007 ; 10.007 ; 10.007 ; 10.007 ;
; ASn          ; DATA[13]      ; 10.376 ; 10.376 ; 10.376 ; 10.376 ;
; ASn          ; DATA[14]      ; 9.579  ; 9.579  ; 9.579  ; 9.579  ;
; ASn          ; DATA[15]      ; 9.748  ; 9.748  ; 9.748  ; 9.748  ;
; ASn          ; DTACKn        ; 8.850  ; 8.850  ; 8.850  ; 8.850  ;
; ASn          ; FC[0]         ; 10.752 ; 10.752 ; 10.752 ; 10.752 ;
; ASn          ; FC[1]         ; 10.560 ; 10.560 ; 10.560 ; 10.560 ;
; ASn          ; FC[2]         ; 10.560 ; 10.560 ; 10.560 ; 10.560 ;
; ASn          ; FLASH_CEn     ; 9.331  ;        ;        ; 9.331  ;
; ASn          ; FLASH_OEn     ; 9.829  ;        ;        ; 9.829  ;
; ASn          ; IDE_CS0n      ; 7.334  ;        ;        ; 7.334  ;
; ASn          ; IDE_CS1n      ; 7.227  ;        ;        ; 7.227  ;
; ASn          ; IDE_D_EN_INn  ; 7.462  ;        ;        ; 7.462  ;
; ASn          ; IDE_D_EN_OUTn ; 7.242  ;        ;        ; 7.242  ;
; ASn          ; IDE_IORDn     ; 7.286  ;        ;        ; 7.286  ;
; ASn          ; IDE_IOWRn     ; 7.291  ;        ;        ; 7.291  ;
; ASn          ; JOY_RHn       ; 7.234  ;        ;        ; 7.234  ;
; ASn          ; JOY_RLn       ; 8.141  ;        ;        ; 8.141  ;
; ASn          ; JOY_WEn       ;        ; 8.113  ; 8.113  ;        ;
; ASn          ; JOY_WL        ;        ; 6.955  ; 6.955  ;        ;
; ASn          ; LDSn          ; 10.938 ; 10.938 ; 10.938 ; 10.938 ;
; ASn          ; RAM_DATA[0]   ; 9.240  ; 9.056  ; 9.056  ; 9.240  ;
; ASn          ; RAM_DATA[1]   ; 9.798  ; 9.630  ; 9.630  ; 9.798  ;
; ASn          ; RAM_DATA[2]   ; 9.762  ; 9.762  ; 9.762  ; 9.762  ;
; ASn          ; RAM_DATA[3]   ; 9.769  ; 9.769  ; 9.769  ; 9.769  ;
; ASn          ; RAM_DATA[4]   ; 10.105 ; 10.105 ; 10.105 ; 10.105 ;
; ASn          ; RAM_DATA[5]   ; 9.794  ; 9.794  ; 9.794  ; 9.794  ;
; ASn          ; RAM_DATA[6]   ; 9.652  ; 9.652  ; 9.652  ; 9.652  ;
; ASn          ; RAM_DATA[7]   ; 9.763  ; 9.763  ; 9.763  ; 9.763  ;
; ASn          ; RAM_DATA[8]   ; 9.836  ; 9.836  ; 9.836  ; 9.836  ;
; ASn          ; RAM_DATA[9]   ; 9.905  ; 9.889  ; 9.889  ; 9.905  ;
; ASn          ; RAM_DATA[10]  ; 10.506 ; 10.558 ; 10.558 ; 10.506 ;
; ASn          ; RAM_DATA[11]  ; 9.912  ; 9.912  ; 9.912  ; 9.912  ;
; ASn          ; RAM_DATA[12]  ; 10.071 ; 10.071 ; 10.071 ; 10.071 ;
; ASn          ; RAM_DATA[13]  ; 10.110 ; 10.110 ; 10.110 ; 10.110 ;
; ASn          ; RAM_DATA[14]  ; 8.695  ; 8.695  ; 8.695  ; 8.695  ;
; ASn          ; RAM_DATA[15]  ; 8.706  ; 8.706  ; 8.706  ; 8.706  ;
; ASn          ; ROM0n         ; 8.356  ;        ;        ; 8.356  ;
; ASn          ; ROM1n         ; 9.187  ;        ;        ; 9.187  ;
; ASn          ; ROM2n         ; 8.505  ;        ;        ; 8.505  ;
; ASn          ; ROM3n         ; 8.015  ;        ;        ; 8.015  ;
; ASn          ; ROM4n         ; 7.827  ;        ;        ; 7.827  ;
; ASn          ; ROM5n         ; 9.036  ;        ;        ; 9.036  ;
; ASn          ; ROM6n         ; 8.250  ;        ;        ; 8.250  ;
; ASn          ; RWn           ; 11.034 ; 11.034 ; 11.034 ; 11.034 ;
; ASn          ; UDSn          ; 10.938 ; 10.938 ; 10.938 ; 10.938 ;
; CD[0]        ; DATA[0]       ; 10.525 ;        ;        ; 10.525 ;
; CD[0]        ; RAM_DATA[0]   ; 8.704  ;        ;        ; 8.704  ;
; CD[1]        ; DATA[1]       ; 10.005 ;        ;        ; 10.005 ;
; CD[1]        ; RAM_DATA[1]   ; 9.090  ;        ;        ; 9.090  ;
; CD[2]        ; DATA[2]       ; 10.162 ;        ;        ; 10.162 ;
; CD[2]        ; RAM_DATA[2]   ; 9.319  ;        ;        ; 9.319  ;
; CD[3]        ; DATA[3]       ; 10.805 ;        ;        ; 10.805 ;
; CD[3]        ; RAM_DATA[3]   ; 9.902  ;        ;        ; 9.902  ;
; CD[4]        ; DATA[4]       ; 9.384  ; 9.384  ; 9.384  ; 9.384  ;
; CD[4]        ; RAM_DATA[4]   ; 9.513  ; 9.513  ; 9.513  ; 9.513  ;
; CD[5]        ; DATA[5]       ; 10.227 ; 10.227 ; 10.227 ; 10.227 ;
; CD[5]        ; RAM_DATA[5]   ; 8.886  ; 8.886  ; 8.886  ; 8.886  ;
; CD[6]        ; DATA[6]       ; 10.225 ; 10.225 ; 10.225 ; 10.225 ;
; CD[6]        ; RAM_DATA[6]   ; 10.056 ; 10.056 ; 10.056 ; 10.056 ;
; CD[7]        ; DATA[7]       ; 10.825 ; 10.825 ; 10.825 ; 10.825 ;
; CD[7]        ; RAM_DATA[7]   ; 10.507 ; 10.507 ; 10.507 ; 10.507 ;
; COM_DCD      ; DATA[1]       ;        ; 11.516 ; 11.516 ;        ;
; COM_DCD      ; DATA[9]       ;        ; 10.959 ; 10.959 ;        ;
; COM_DCD      ; RAM_DATA[1]   ;        ; 10.601 ; 10.601 ;        ;
; COM_DCD      ; RAM_DATA[9]   ;        ; 10.330 ; 10.330 ;        ;
; COM_RI       ; DATA[6]       ; 11.269 ; 11.269 ; 11.269 ; 11.269 ;
; COM_RI       ; DATA[14]      ; 12.105 ; 12.105 ; 12.105 ; 12.105 ;
; COM_RI       ; RAM_DATA[6]   ; 11.100 ; 11.100 ; 11.100 ; 11.100 ;
; COM_RI       ; RAM_DATA[14]  ; 11.221 ; 11.221 ; 11.221 ; 11.221 ;
; CONFIG[1]    ; DATA[15]      ; 11.093 ; 11.093 ; 11.093 ; 11.093 ;
; CONFIG[1]    ; RAM_DATA[15]  ; 10.051 ; 10.051 ; 10.051 ; 10.051 ;
; CONFIG[2]    ; DATA[14]      ; 10.751 ; 10.751 ; 10.751 ; 10.751 ;
; CONFIG[2]    ; RAM_DATA[14]  ; 9.867  ; 9.867  ; 9.867  ; 9.867  ;
; CONFIG[5]    ; ACSI_RDn      ; 9.675  ; 9.675  ; 9.675  ; 9.675  ;
; CONFIG[5]    ; ACSI_WRn      ; 9.665  ; 9.665  ; 9.665  ; 9.665  ;
; CONFIG[5]    ; ASn           ; 10.822 ; 10.822 ; 10.822 ; 10.822 ;
; CONFIG[5]    ; BUTTONn       ; 8.979  ; 9.116  ; 9.116  ; 8.979  ;
; CONFIG[5]    ; CA1_OUT       ; 8.710  ; 8.847  ; 8.847  ; 8.710  ;
; CONFIG[5]    ; CD[0]         ; 9.756  ; 9.756  ; 9.756  ; 9.756  ;
; CONFIG[5]    ; CD[1]         ; 9.748  ; 9.748  ; 9.748  ; 9.748  ;
; CONFIG[5]    ; CD[2]         ; 9.590  ; 9.590  ; 9.590  ; 9.590  ;
; CONFIG[5]    ; CD[3]         ; 9.748  ; 9.748  ; 9.748  ; 9.748  ;
; CONFIG[5]    ; CD[4]         ; 9.597  ; 9.597  ; 9.597  ; 9.597  ;
; CONFIG[5]    ; CD[5]         ; 9.597  ; 9.597  ; 9.597  ; 9.597  ;
; CONFIG[5]    ; CD[6]         ; 9.566  ; 9.566  ; 9.566  ; 9.566  ;
; CONFIG[5]    ; CD[7]         ; 9.566  ; 9.566  ; 9.566  ; 9.566  ;
; CONFIG[5]    ; DATA[0]       ; 11.208 ; 11.208 ; 11.208 ; 11.208 ;
; CONFIG[5]    ; DATA[1]       ; 11.208 ; 11.208 ; 11.208 ; 11.208 ;
; CONFIG[5]    ; DATA[2]       ; 11.063 ; 11.063 ; 11.063 ; 11.063 ;
; CONFIG[5]    ; DATA[3]       ; 11.178 ; 11.178 ; 11.178 ; 11.178 ;
; CONFIG[5]    ; DATA[4]       ; 11.082 ; 11.082 ; 11.082 ; 11.082 ;
; CONFIG[5]    ; DATA[5]       ; 11.102 ; 11.102 ; 11.102 ; 11.102 ;
; CONFIG[5]    ; DATA[6]       ; 10.927 ; 10.927 ; 10.927 ; 10.927 ;
; CONFIG[5]    ; DATA[7]       ; 11.002 ; 11.002 ; 11.002 ; 11.002 ;
; CONFIG[5]    ; DATA[8]       ; 10.926 ; 10.926 ; 10.926 ; 10.926 ;
; CONFIG[5]    ; DATA[9]       ; 11.021 ; 11.021 ; 11.021 ; 11.021 ;
; CONFIG[5]    ; DATA[10]      ; 10.863 ; 10.863 ; 10.863 ; 10.863 ;
; CONFIG[5]    ; DATA[11]      ; 11.046 ; 11.046 ; 11.046 ; 11.046 ;
; CONFIG[5]    ; DATA[12]      ; 11.051 ; 11.051 ; 11.051 ; 11.051 ;
; CONFIG[5]    ; DATA[13]      ; 11.051 ; 11.051 ; 11.051 ; 11.051 ;
; CONFIG[5]    ; DATA[14]      ; 10.968 ; 10.968 ; 10.968 ; 10.968 ;
; CONFIG[5]    ; DATA[15]      ; 11.137 ; 11.137 ; 11.137 ; 11.137 ;
; CONFIG[5]    ; DTACKn        ; 9.063  ; 9.063  ; 9.063  ; 9.063  ;
; CONFIG[5]    ; FC[0]         ; 11.103 ; 11.103 ; 11.103 ; 11.103 ;
; CONFIG[5]    ; FC[1]         ; 10.911 ; 10.911 ; 10.911 ; 10.911 ;
; CONFIG[5]    ; FC[2]         ; 10.911 ; 10.911 ; 10.911 ; 10.911 ;
; CONFIG[5]    ; FLASH_CEn     ; 9.545  ; 9.545  ; 9.545  ; 9.545  ;
; CONFIG[5]    ; FLASH_OEn     ; 10.043 ; 10.043 ; 10.043 ; 10.043 ;
; CONFIG[5]    ; IDE_CS0n      ; 9.044  ; 9.044  ; 9.044  ; 9.044  ;
; CONFIG[5]    ; IDE_CS1n      ; 8.714  ; 8.714  ; 8.714  ; 8.714  ;
; CONFIG[5]    ; IDE_D_EN_INn  ; 8.851  ; 8.851  ; 8.851  ; 8.851  ;
; CONFIG[5]    ; IDE_D_EN_OUTn ; 8.759  ; 8.759  ; 8.759  ; 8.759  ;
; CONFIG[5]    ; IDE_IORDn     ; 8.460  ; 8.460  ; 8.460  ; 8.460  ;
; CONFIG[5]    ; IDE_IOWRn     ; 9.631  ; 9.631  ; 9.631  ; 9.631  ;
; CONFIG[5]    ; JOY_RHn       ; 8.838  ; 8.975  ; 8.975  ; 8.838  ;
; CONFIG[5]    ; JOY_RLn       ; 9.745  ; 9.882  ; 9.882  ; 9.745  ;
; CONFIG[5]    ; JOY_WEn       ; 9.854  ; 9.717  ; 9.717  ; 9.854  ;
; CONFIG[5]    ; JOY_WL        ; 8.696  ; 8.559  ; 8.559  ; 8.696  ;
; CONFIG[5]    ; LDSn          ; 11.289 ; 11.289 ; 11.289 ; 11.289 ;
; CONFIG[5]    ; RAM_BA[1]     ; 8.326  ; 8.630  ; 8.630  ; 8.326  ;
; CONFIG[5]    ; RAM_CAS0n     ; 8.188  ; 8.188  ; 8.188  ; 8.188  ;
; CONFIG[5]    ; RAM_CAS1n     ; 7.776  ; 7.776  ; 7.776  ; 7.776  ;
; CONFIG[5]    ; RAM_DATA[0]   ; 9.807  ; 9.807  ; 9.807  ; 9.807  ;
; CONFIG[5]    ; RAM_DATA[1]   ; 10.846 ; 10.938 ; 10.938 ; 10.846 ;
; CONFIG[5]    ; RAM_DATA[2]   ; 10.220 ; 10.220 ; 10.220 ; 10.220 ;
; CONFIG[5]    ; RAM_DATA[3]   ; 10.275 ; 10.275 ; 10.275 ; 10.275 ;
; CONFIG[5]    ; RAM_DATA[4]   ; 11.211 ; 11.211 ; 11.211 ; 11.211 ;
; CONFIG[5]    ; RAM_DATA[5]   ; 10.849 ; 10.849 ; 10.849 ; 10.849 ;
; CONFIG[5]    ; RAM_DATA[6]   ; 10.758 ; 10.758 ; 10.758 ; 10.758 ;
; CONFIG[5]    ; RAM_DATA[7]   ; 10.869 ; 10.869 ; 10.869 ; 10.869 ;
; CONFIG[5]    ; RAM_DATA[8]   ; 10.537 ; 10.537 ; 10.537 ; 10.537 ;
; CONFIG[5]    ; RAM_DATA[9]   ; 10.561 ; 10.561 ; 10.561 ; 10.561 ;
; CONFIG[5]    ; RAM_DATA[10]  ; 11.000 ; 11.000 ; 11.000 ; 11.000 ;
; CONFIG[5]    ; RAM_DATA[11]  ; 10.773 ; 10.773 ; 10.773 ; 10.773 ;
; CONFIG[5]    ; RAM_DATA[12]  ; 11.149 ; 11.149 ; 11.149 ; 11.149 ;
; CONFIG[5]    ; RAM_DATA[13]  ; 10.601 ; 10.601 ; 10.601 ; 10.601 ;
; CONFIG[5]    ; RAM_DATA[14]  ; 10.084 ; 10.084 ; 10.084 ; 10.084 ;
; CONFIG[5]    ; RAM_DATA[15]  ; 10.095 ; 10.095 ; 10.095 ; 10.095 ;
; CONFIG[5]    ; RAM_RAS0n     ; 8.996  ; 8.996  ; 8.996  ; 8.996  ;
; CONFIG[5]    ; RAM_RAS1n     ; 8.838  ; 8.838  ; 8.838  ; 8.838  ;
; CONFIG[5]    ; ROM0n         ; 8.344  ; 8.417  ; 8.417  ; 8.344  ;
; CONFIG[5]    ; ROM1n         ; 9.171  ; 9.244  ; 9.244  ; 9.171  ;
; CONFIG[5]    ; ROM2n         ; 8.719  ; 8.719  ; 8.719  ; 8.719  ;
; CONFIG[5]    ; ROM3n         ; 8.896  ; 8.896  ; 8.896  ; 8.896  ;
; CONFIG[5]    ; ROM4n         ; 8.704  ; 8.704  ; 8.704  ; 8.704  ;
; CONFIG[5]    ; ROM5n         ; 9.328  ; 9.328  ; 9.328  ; 9.328  ;
; CONFIG[5]    ; ROM6n         ; 9.131  ; 9.131  ; 9.131  ; 9.131  ;
; CONFIG[5]    ; RWn           ; 11.385 ; 11.385 ; 11.385 ; 11.385 ;
; CONFIG[5]    ; UDSn          ; 11.289 ; 11.289 ; 11.289 ; 11.289 ;
; DATA[0]      ; DATA[0]       ; 9.208  ;        ;        ; 9.208  ;
; DATA[0]      ; RAM_DATA[0]   ; 7.387  ;        ;        ; 7.387  ;
; DATA[1]      ; DATA[1]       ; 9.014  ;        ;        ; 9.014  ;
; DATA[1]      ; RAM_DATA[1]   ; 8.099  ;        ;        ; 8.099  ;
; DATA[2]      ; DATA[2]       ; 8.729  ;        ;        ; 8.729  ;
; DATA[2]      ; RAM_DATA[2]   ; 7.886  ;        ;        ; 7.886  ;
; DATA[3]      ; DATA[3]       ; 8.764  ;        ;        ; 8.764  ;
; DATA[3]      ; RAM_DATA[3]   ; 7.861  ;        ;        ; 7.861  ;
; DATA[4]      ; DATA[4]       ; 8.020  ; 8.020  ; 8.020  ; 8.020  ;
; DATA[4]      ; RAM_DATA[4]   ; 8.149  ; 8.149  ; 8.149  ; 8.149  ;
; DATA[5]      ; DATA[5]       ; 9.476  ;        ;        ; 9.476  ;
; DATA[5]      ; RAM_DATA[5]   ; 8.135  ;        ;        ; 8.135  ;
; DATA[6]      ; DATA[6]       ; 8.593  ; 8.593  ; 8.593  ; 8.593  ;
; DATA[6]      ; RAM_DATA[6]   ; 8.424  ; 8.424  ; 8.424  ; 8.424  ;
; DATA[7]      ; DATA[7]       ; 8.852  ;        ;        ; 8.852  ;
; DATA[7]      ; RAM_DATA[7]   ; 8.534  ;        ;        ; 8.534  ;
; DATA[8]      ; DATA[8]       ; 8.794  ;        ;        ; 8.794  ;
; DATA[8]      ; RAM_DATA[8]   ; 8.405  ;        ;        ; 8.405  ;
; DATA[9]      ; DATA[9]       ; 8.342  ;        ;        ; 8.342  ;
; DATA[9]      ; RAM_DATA[9]   ; 7.713  ;        ;        ; 7.713  ;
; DATA[10]     ; DATA[10]      ; 8.800  ;        ;        ; 8.800  ;
; DATA[10]     ; RAM_DATA[10]  ; 8.937  ;        ;        ; 8.937  ;
; DATA[11]     ; DATA[11]      ; 9.665  ;        ;        ; 9.665  ;
; DATA[11]     ; RAM_DATA[11]  ; 8.030  ;        ;        ; 8.030  ;
; DATA[12]     ; DATA[12]      ; 7.724  ;        ;        ; 7.724  ;
; DATA[12]     ; RAM_DATA[12]  ; 7.788  ;        ;        ; 7.788  ;
; DATA[13]     ; DATA[13]      ; 9.072  ;        ;        ; 9.072  ;
; DATA[13]     ; RAM_DATA[13]  ; 7.923  ;        ;        ; 7.923  ;
; DATA[14]     ; DATA[14]      ; 7.943  ;        ;        ; 7.943  ;
; DATA[14]     ; RAM_DATA[14]  ; 7.059  ;        ;        ; 7.059  ;
; DATA[15]     ; DATA[15]      ; 8.165  ;        ;        ; 8.165  ;
; DATA[15]     ; RAM_DATA[15]  ; 7.123  ;        ;        ; 7.123  ;
; FC[0]        ; ACSI_RDn      ; 8.808  ; 8.808  ; 8.808  ; 8.808  ;
; FC[0]        ; ACSI_WRn      ; 8.798  ; 8.798  ; 8.798  ; 8.798  ;
; FC[0]        ; ASn           ; 9.300  ; 9.300  ; 9.300  ; 9.300  ;
; FC[0]        ; BUTTONn       ; 8.544  ; 8.544  ; 8.544  ; 8.544  ;
; FC[0]        ; CA1_OUT       ; 7.843  ; 7.843  ; 7.843  ; 7.843  ;
; FC[0]        ; CD[0]         ; 8.889  ; 8.889  ; 8.889  ; 8.889  ;
; FC[0]        ; CD[1]         ; 8.881  ; 8.881  ; 8.881  ; 8.881  ;
; FC[0]        ; CD[2]         ; 8.723  ; 8.723  ; 8.723  ; 8.723  ;
; FC[0]        ; CD[3]         ; 8.881  ; 8.881  ; 8.881  ; 8.881  ;
; FC[0]        ; CD[4]         ; 8.730  ; 8.730  ; 8.730  ; 8.730  ;
; FC[0]        ; CD[5]         ; 8.730  ; 8.730  ; 8.730  ; 8.730  ;
; FC[0]        ; CD[6]         ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; FC[0]        ; CD[7]         ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; FC[0]        ; DATA[0]       ; 10.784 ; 10.706 ; 10.706 ; 10.784 ;
; FC[0]        ; DATA[1]       ; 10.684 ; 10.374 ; 10.374 ; 10.684 ;
; FC[0]        ; DATA[2]       ; 10.317 ; 10.317 ; 10.317 ; 10.317 ;
; FC[0]        ; DATA[3]       ; 10.715 ; 10.715 ; 10.715 ; 10.715 ;
; FC[0]        ; DATA[4]       ; 10.503 ; 10.503 ; 10.503 ; 10.503 ;
; FC[0]        ; DATA[5]       ; 10.678 ; 10.678 ; 10.678 ; 10.678 ;
; FC[0]        ; DATA[6]       ; 10.265 ; 10.265 ; 10.265 ; 10.265 ;
; FC[0]        ; DATA[7]       ; 10.578 ; 10.578 ; 10.578 ; 10.578 ;
; FC[0]        ; DATA[8]       ; 10.131 ; 10.131 ; 10.131 ; 10.131 ;
; FC[0]        ; DATA[9]       ; 10.263 ; 10.263 ; 10.263 ; 10.263 ;
; FC[0]        ; DATA[10]      ; 10.437 ; 10.437 ; 10.437 ; 10.437 ;
; FC[0]        ; DATA[11]      ; 10.622 ; 10.622 ; 10.622 ; 10.622 ;
; FC[0]        ; DATA[12]      ; 10.584 ; 10.584 ; 10.584 ; 10.584 ;
; FC[0]        ; DATA[13]      ; 10.627 ; 10.627 ; 10.627 ; 10.627 ;
; FC[0]        ; DATA[14]      ; 10.376 ; 10.376 ; 10.376 ; 10.376 ;
; FC[0]        ; DATA[15]      ; 10.545 ; 10.545 ; 10.545 ; 10.545 ;
; FC[0]        ; DTACKn        ; 7.363  ; 7.363  ; 7.363  ; 7.363  ;
; FC[0]        ; FC[0]         ; 9.581  ; 9.581  ; 9.581  ; 9.581  ;
; FC[0]        ; FC[1]         ; 9.389  ; 9.389  ; 9.389  ; 9.389  ;
; FC[0]        ; FC[2]         ; 9.389  ; 9.389  ; 9.389  ; 9.389  ;
; FC[0]        ; FLASH_CEn     ; 10.027 ; 10.027 ; 10.027 ; 10.027 ;
; FC[0]        ; FLASH_OEn     ; 10.525 ; 10.525 ; 10.525 ; 10.525 ;
; FC[0]        ; IDE_CS0n      ; 8.131  ;        ;        ; 8.131  ;
; FC[0]        ; IDE_CS1n      ; 8.024  ;        ;        ; 8.024  ;
; FC[0]        ; IDE_D_EN_INn  ; 8.259  ;        ;        ; 8.259  ;
; FC[0]        ; IDE_D_EN_OUTn ; 8.039  ;        ;        ; 8.039  ;
; FC[0]        ; IDE_IORDn     ; 8.083  ;        ;        ; 8.083  ;
; FC[0]        ; IDE_IOWRn     ; 8.088  ;        ;        ; 8.088  ;
; FC[0]        ; JOY_RHn       ; 8.031  ; 8.396  ; 8.396  ; 8.031  ;
; FC[0]        ; JOY_RLn       ; 8.938  ; 9.313  ; 9.313  ; 8.938  ;
; FC[0]        ; JOY_WEn       ; 9.285  ; 8.910  ; 8.910  ; 9.285  ;
; FC[0]        ; JOY_WL        ; 8.062  ; 7.752  ; 7.752  ; 8.062  ;
; FC[0]        ; LDSn          ; 9.767  ; 9.767  ; 9.767  ; 9.767  ;
; FC[0]        ; RAM_DATA[0]   ; 9.069  ; 8.885  ; 8.885  ; 9.069  ;
; FC[0]        ; RAM_DATA[1]   ; 9.769  ; 9.459  ; 9.459  ; 9.769  ;
; FC[0]        ; RAM_DATA[2]   ; 9.474  ; 9.474  ; 9.474  ; 9.474  ;
; FC[0]        ; RAM_DATA[3]   ; 9.812  ; 9.812  ; 9.812  ; 9.812  ;
; FC[0]        ; RAM_DATA[4]   ; 10.632 ; 10.632 ; 10.632 ; 10.632 ;
; FC[0]        ; RAM_DATA[5]   ; 10.101 ; 10.101 ; 10.101 ; 10.101 ;
; FC[0]        ; RAM_DATA[6]   ; 10.096 ; 10.096 ; 10.096 ; 10.096 ;
; FC[0]        ; RAM_DATA[7]   ; 10.332 ; 10.332 ; 10.332 ; 10.332 ;
; FC[0]        ; RAM_DATA[8]   ; 9.742  ; 9.742  ; 9.742  ; 9.742  ;
; FC[0]        ; RAM_DATA[9]   ; 9.634  ; 9.634  ; 9.634  ; 9.634  ;
; FC[0]        ; RAM_DATA[10]  ; 10.574 ; 10.574 ; 10.574 ; 10.574 ;
; FC[0]        ; RAM_DATA[11]  ; 9.704  ; 9.704  ; 9.704  ; 9.704  ;
; FC[0]        ; RAM_DATA[12]  ; 10.648 ; 10.648 ; 10.648 ; 10.648 ;
; FC[0]        ; RAM_DATA[13]  ; 9.552  ; 9.552  ; 9.552  ; 9.552  ;
; FC[0]        ; RAM_DATA[14]  ; 9.492  ; 9.492  ; 9.492  ; 9.492  ;
; FC[0]        ; RAM_DATA[15]  ; 9.503  ; 9.503  ; 9.503  ; 9.503  ;
; FC[0]        ; ROM0n         ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[0]        ; ROM1n         ; 9.758  ; 9.758  ; 9.758  ; 9.758  ;
; FC[0]        ; ROM2n         ; 9.201  ; 9.201  ; 9.201  ; 9.201  ;
; FC[0]        ; ROM3n         ; 8.711  ; 8.711  ; 8.711  ; 8.711  ;
; FC[0]        ; ROM4n         ; 8.523  ; 8.523  ; 8.523  ; 8.523  ;
; FC[0]        ; ROM5n         ; 9.607  ; 9.607  ; 9.607  ; 9.607  ;
; FC[0]        ; ROM6n         ; 8.946  ; 8.946  ; 8.946  ; 8.946  ;
; FC[0]        ; RWn           ; 9.863  ; 9.863  ; 9.863  ; 9.863  ;
; FC[0]        ; UDSn          ; 9.767  ; 9.767  ; 9.767  ; 9.767  ;
; FC[1]        ; ACSI_RDn      ; 8.937  ; 8.937  ; 8.937  ; 8.937  ;
; FC[1]        ; ACSI_WRn      ; 8.927  ; 8.927  ; 8.927  ; 8.927  ;
; FC[1]        ; ASn           ; 9.429  ; 9.429  ; 9.429  ; 9.429  ;
; FC[1]        ; BUTTONn       ; 7.774  ; 7.774  ; 7.774  ; 7.774  ;
; FC[1]        ; CA1_OUT       ; 7.972  ; 7.972  ; 7.972  ; 7.972  ;
; FC[1]        ; CD[0]         ; 9.018  ; 9.018  ; 9.018  ; 9.018  ;
; FC[1]        ; CD[1]         ; 9.010  ; 9.010  ; 9.010  ; 9.010  ;
; FC[1]        ; CD[2]         ; 8.852  ; 8.852  ; 8.852  ; 8.852  ;
; FC[1]        ; CD[3]         ; 9.010  ; 9.010  ; 9.010  ; 9.010  ;
; FC[1]        ; CD[4]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; FC[1]        ; CD[5]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; FC[1]        ; CD[6]         ; 8.828  ; 8.828  ; 8.828  ; 8.828  ;
; FC[1]        ; CD[7]         ; 8.828  ; 8.828  ; 8.828  ; 8.828  ;
; FC[1]        ; DATA[0]       ; 10.582 ; 10.582 ; 10.582 ; 10.582 ;
; FC[1]        ; DATA[1]       ; 10.582 ; 10.496 ; 10.496 ; 10.582 ;
; FC[1]        ; DATA[2]       ; 10.446 ; 10.446 ; 10.446 ; 10.446 ;
; FC[1]        ; DATA[3]       ; 10.562 ; 10.562 ; 10.562 ; 10.562 ;
; FC[1]        ; DATA[4]       ; 10.394 ; 10.394 ; 10.394 ; 10.394 ;
; FC[1]        ; DATA[5]       ; 10.476 ; 10.476 ; 10.476 ; 10.476 ;
; FC[1]        ; DATA[6]       ; 10.070 ; 10.070 ; 10.070 ; 10.070 ;
; FC[1]        ; DATA[7]       ; 10.376 ; 10.376 ; 10.376 ; 10.376 ;
; FC[1]        ; DATA[8]       ; 10.260 ; 10.260 ; 10.260 ; 10.260 ;
; FC[1]        ; DATA[9]       ; 10.392 ; 10.392 ; 10.392 ; 10.392 ;
; FC[1]        ; DATA[10]      ; 10.401 ; 10.401 ; 10.401 ; 10.401 ;
; FC[1]        ; DATA[11]      ; 10.420 ; 10.420 ; 10.420 ; 10.420 ;
; FC[1]        ; DATA[12]      ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; FC[1]        ; DATA[13]      ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; FC[1]        ; DATA[14]      ; 10.181 ; 10.181 ; 10.181 ; 10.181 ;
; FC[1]        ; DATA[15]      ; 10.350 ; 10.350 ; 10.350 ; 10.350 ;
; FC[1]        ; DTACKn        ; 7.413  ; 7.413  ; 7.413  ; 7.413  ;
; FC[1]        ; FC[0]         ; 9.710  ; 9.710  ; 9.710  ; 9.710  ;
; FC[1]        ; FC[1]         ; 9.518  ; 9.518  ; 9.518  ; 9.518  ;
; FC[1]        ; FC[2]         ; 9.518  ; 9.518  ; 9.518  ; 9.518  ;
; FC[1]        ; FLASH_CEn     ; 9.257  ; 9.257  ; 9.257  ; 9.257  ;
; FC[1]        ; FLASH_OEn     ; 9.755  ; 9.755  ; 9.755  ; 9.755  ;
; FC[1]        ; IDE_CS0n      ; 7.936  ;        ;        ; 7.936  ;
; FC[1]        ; IDE_CS1n      ; 7.829  ;        ;        ; 7.829  ;
; FC[1]        ; IDE_D_EN_INn  ; 8.064  ;        ;        ; 8.064  ;
; FC[1]        ; IDE_D_EN_OUTn ; 7.844  ;        ;        ; 7.844  ;
; FC[1]        ; IDE_IORDn     ; 7.888  ;        ;        ; 7.888  ;
; FC[1]        ; IDE_IOWRn     ; 7.893  ;        ;        ; 7.893  ;
; FC[1]        ; JOY_RHn       ; 7.626  ; 7.626  ; 7.626  ; 7.626  ;
; FC[1]        ; JOY_RLn       ; 8.543  ; 8.543  ; 8.543  ; 8.543  ;
; FC[1]        ; JOY_WEn       ; 8.515  ; 8.515  ; 8.515  ; 8.515  ;
; FC[1]        ; JOY_WL        ; 7.292  ; 7.292  ; 7.292  ; 7.292  ;
; FC[1]        ; LDSn          ; 9.896  ; 9.896  ; 9.896  ; 9.896  ;
; FC[1]        ; RAM_DATA[0]   ; 9.191  ; 9.007  ; 9.007  ; 9.191  ;
; FC[1]        ; RAM_DATA[1]   ; 9.778  ; 9.581  ; 9.581  ; 9.778  ;
; FC[1]        ; RAM_DATA[2]   ; 9.603  ; 9.603  ; 9.603  ; 9.603  ;
; FC[1]        ; RAM_DATA[3]   ; 9.934  ; 9.934  ; 9.934  ; 9.934  ;
; FC[1]        ; RAM_DATA[4]   ; 10.523 ; 10.523 ; 10.523 ; 10.523 ;
; FC[1]        ; RAM_DATA[5]   ; 9.906  ; 9.906  ; 9.906  ; 9.906  ;
; FC[1]        ; RAM_DATA[6]   ; 9.901  ; 9.901  ; 9.901  ; 9.901  ;
; FC[1]        ; RAM_DATA[7]   ; 10.365 ; 10.365 ; 10.365 ; 10.365 ;
; FC[1]        ; RAM_DATA[8]   ; 9.871  ; 9.871  ; 9.871  ; 9.871  ;
; FC[1]        ; RAM_DATA[9]   ; 9.763  ; 9.763  ; 9.763  ; 9.763  ;
; FC[1]        ; RAM_DATA[10]  ; 10.538 ; 10.538 ; 10.538 ; 10.538 ;
; FC[1]        ; RAM_DATA[11]  ; 9.833  ; 9.833  ; 9.833  ; 9.833  ;
; FC[1]        ; RAM_DATA[12]  ; 10.673 ; 10.673 ; 10.673 ; 10.673 ;
; FC[1]        ; RAM_DATA[13]  ; 9.681  ; 9.681  ; 9.681  ; 9.681  ;
; FC[1]        ; RAM_DATA[14]  ; 9.297  ; 9.297  ; 9.297  ; 9.297  ;
; FC[1]        ; RAM_DATA[15]  ; 9.308  ; 9.308  ; 9.308  ; 9.308  ;
; FC[1]        ; ROM0n         ; 8.157  ; 8.157  ; 8.157  ; 8.157  ;
; FC[1]        ; ROM1n         ; 8.988  ; 8.988  ; 8.988  ; 8.988  ;
; FC[1]        ; ROM2n         ; 8.431  ; 8.431  ; 8.431  ; 8.431  ;
; FC[1]        ; ROM3n         ; 7.941  ; 7.941  ; 7.941  ; 7.941  ;
; FC[1]        ; ROM4n         ; 7.753  ; 7.753  ; 7.753  ; 7.753  ;
; FC[1]        ; ROM5n         ; 8.837  ; 8.837  ; 8.837  ; 8.837  ;
; FC[1]        ; ROM6n         ; 8.176  ; 8.176  ; 8.176  ; 8.176  ;
; FC[1]        ; RWn           ; 9.992  ; 9.992  ; 9.992  ; 9.992  ;
; FC[1]        ; UDSn          ; 9.896  ; 9.896  ; 9.896  ; 9.896  ;
; FC[2]        ; ACSI_RDn      ; 8.894  ; 8.894  ; 8.894  ; 8.894  ;
; FC[2]        ; ACSI_WRn      ; 8.884  ; 8.884  ; 8.884  ; 8.884  ;
; FC[2]        ; ASn           ; 9.386  ; 9.386  ; 9.386  ; 9.386  ;
; FC[2]        ; BUTTONn       ; 8.607  ;        ;        ; 8.607  ;
; FC[2]        ; CA1_OUT       ; 9.048  ; 7.929  ; 7.929  ; 9.048  ;
; FC[2]        ; CD[0]         ; 8.975  ; 8.975  ; 8.975  ; 8.975  ;
; FC[2]        ; CD[1]         ; 8.967  ; 8.967  ; 8.967  ; 8.967  ;
; FC[2]        ; CD[2]         ; 8.809  ; 8.809  ; 8.809  ; 8.809  ;
; FC[2]        ; CD[3]         ; 8.967  ; 8.967  ; 8.967  ; 8.967  ;
; FC[2]        ; CD[4]         ; 8.816  ; 8.816  ; 8.816  ; 8.816  ;
; FC[2]        ; CD[5]         ; 8.816  ; 8.816  ; 8.816  ; 8.816  ;
; FC[2]        ; CD[6]         ; 8.785  ; 8.785  ; 8.785  ; 8.785  ;
; FC[2]        ; CD[7]         ; 8.785  ; 8.785  ; 8.785  ; 8.785  ;
; FC[2]        ; DATA[0]       ; 10.544 ; 10.544 ; 10.544 ; 10.544 ;
; FC[2]        ; DATA[1]       ; 10.544 ; 10.449 ; 10.449 ; 10.544 ;
; FC[2]        ; DATA[2]       ; 10.403 ; 10.509 ; 10.509 ; 10.403 ;
; FC[2]        ; DATA[3]       ; 10.524 ; 10.524 ; 10.524 ; 10.524 ;
; FC[2]        ; DATA[4]       ; 10.349 ; 10.349 ; 10.349 ; 10.349 ;
; FC[2]        ; DATA[5]       ; 10.438 ; 10.438 ; 10.438 ; 10.438 ;
; FC[2]        ; DATA[6]       ; 10.025 ; 10.025 ; 10.025 ; 10.025 ;
; FC[2]        ; DATA[7]       ; 10.338 ; 10.338 ; 10.338 ; 10.338 ;
; FC[2]        ; DATA[8]       ; 10.272 ; 10.217 ; 10.217 ; 10.272 ;
; FC[2]        ; DATA[9]       ; 10.349 ; 10.357 ; 10.357 ; 10.349 ;
; FC[2]        ; DATA[10]      ; 10.382 ; 10.382 ; 10.382 ; 10.382 ;
; FC[2]        ; DATA[11]      ; 10.382 ; 10.382 ; 10.382 ; 10.382 ;
; FC[2]        ; DATA[12]      ; 10.387 ; 10.387 ; 10.387 ; 10.387 ;
; FC[2]        ; DATA[13]      ; 10.387 ; 10.387 ; 10.387 ; 10.387 ;
; FC[2]        ; DATA[14]      ; 10.154 ; 10.154 ; 10.154 ; 10.154 ;
; FC[2]        ; DATA[15]      ; 10.323 ; 10.323 ; 10.323 ; 10.323 ;
; FC[2]        ; DTACKn        ; 7.249  ; 7.249  ; 7.249  ; 7.249  ;
; FC[2]        ; FC[0]         ; 9.667  ; 9.667  ; 9.667  ; 9.667  ;
; FC[2]        ; FC[1]         ; 9.475  ; 9.475  ; 9.475  ; 9.475  ;
; FC[2]        ; FC[2]         ; 9.475  ; 9.475  ; 9.475  ; 9.475  ;
; FC[2]        ; FLASH_CEn     ; 9.906  ;        ;        ; 9.906  ;
; FC[2]        ; FLASH_OEn     ; 10.404 ;        ;        ; 10.404 ;
; FC[2]        ; IDE_CS0n      ; 7.909  ;        ;        ; 7.909  ;
; FC[2]        ; IDE_CS1n      ; 7.802  ;        ;        ; 7.802  ;
; FC[2]        ; IDE_D_EN_INn  ; 8.037  ;        ;        ; 8.037  ;
; FC[2]        ; IDE_D_EN_OUTn ; 7.817  ;        ;        ; 7.817  ;
; FC[2]        ; IDE_IORDn     ; 7.861  ;        ;        ; 7.861  ;
; FC[2]        ; IDE_IOWRn     ; 7.866  ;        ;        ; 7.866  ;
; FC[2]        ; JOY_RHn       ; 7.809  ; 8.190  ; 8.190  ; 7.809  ;
; FC[2]        ; JOY_RLn       ; 8.716  ; 9.107  ; 9.107  ; 8.716  ;
; FC[2]        ; JOY_WEn       ; 9.079  ; 8.688  ; 8.688  ; 9.079  ;
; FC[2]        ; JOY_WL        ; 7.856  ; 7.530  ; 7.530  ; 7.856  ;
; FC[2]        ; LDSn          ; 9.853  ; 9.853  ; 9.853  ; 9.853  ;
; FC[2]        ; RAM_DATA[0]   ; 9.144  ; 8.960  ; 8.960  ; 9.144  ;
; FC[2]        ; RAM_DATA[1]   ; 9.957  ; 9.534  ; 9.534  ; 9.957  ;
; FC[2]        ; RAM_DATA[2]   ; 9.560  ; 9.666  ; 9.666  ; 9.560  ;
; FC[2]        ; RAM_DATA[3]   ; 9.887  ; 9.887  ; 9.887  ; 9.887  ;
; FC[2]        ; RAM_DATA[4]   ; 10.478 ; 10.478 ; 10.478 ; 10.478 ;
; FC[2]        ; RAM_DATA[5]   ; 9.861  ; 9.861  ; 9.861  ; 9.861  ;
; FC[2]        ; RAM_DATA[6]   ; 9.856  ; 9.856  ; 9.856  ; 9.856  ;
; FC[2]        ; RAM_DATA[7]   ; 10.338 ; 10.338 ; 10.338 ; 10.338 ;
; FC[2]        ; RAM_DATA[8]   ; 9.883  ; 9.828  ; 9.828  ; 9.883  ;
; FC[2]        ; RAM_DATA[9]   ; 9.720  ; 9.748  ; 9.748  ; 9.720  ;
; FC[2]        ; RAM_DATA[10]  ; 10.753 ; 10.660 ; 10.660 ; 10.753 ;
; FC[2]        ; RAM_DATA[11]  ; 10.112 ; 9.790  ; 9.790  ; 10.112 ;
; FC[2]        ; RAM_DATA[12]  ; 10.646 ; 10.646 ; 10.646 ; 10.646 ;
; FC[2]        ; RAM_DATA[13]  ; 10.004 ; 9.638  ; 9.638  ; 10.004 ;
; FC[2]        ; RAM_DATA[14]  ; 9.270  ; 9.270  ; 9.270  ; 9.270  ;
; FC[2]        ; RAM_DATA[15]  ; 9.281  ; 9.281  ; 9.281  ; 9.281  ;
; FC[2]        ; ROM0n         ; 8.931  ;        ;        ; 8.931  ;
; FC[2]        ; ROM1n         ; 9.762  ;        ;        ; 9.762  ;
; FC[2]        ; ROM2n         ; 9.080  ;        ;        ; 9.080  ;
; FC[2]        ; ROM3n         ; 8.590  ;        ;        ; 8.590  ;
; FC[2]        ; ROM4n         ; 8.402  ;        ;        ; 8.402  ;
; FC[2]        ; ROM5n         ; 9.611  ;        ;        ; 9.611  ;
; FC[2]        ; ROM6n         ; 8.825  ;        ;        ; 8.825  ;
; FC[2]        ; RWn           ; 9.949  ; 9.949  ; 9.949  ; 9.949  ;
; FC[2]        ; UDSn          ; 9.853  ; 9.853  ; 9.853  ; 9.853  ;
; HDINTn       ; DATA[5]       ; 12.021 ; 12.021 ; 12.021 ; 12.021 ;
; HDINTn       ; DATA[13]      ; 11.915 ;        ;        ; 11.915 ;
; HDINTn       ; RAM_DATA[5]   ; 10.680 ; 10.680 ; 10.680 ; 10.680 ;
; HDINTn       ; RAM_DATA[13]  ; 10.766 ;        ;        ; 10.766 ;
; IDE_INTRQ    ; DATA[5]       ; 12.138 ; 12.138 ; 12.138 ; 12.138 ;
; IDE_INTRQ    ; DATA[13]      ;        ; 12.032 ; 12.032 ;        ;
; IDE_INTRQ    ; RAM_DATA[5]   ; 10.797 ; 10.797 ; 10.797 ; 10.797 ;
; IDE_INTRQ    ; RAM_DATA[13]  ;        ; 10.883 ; 10.883 ;        ;
; LDSn         ; ACSI_RDn      ; 7.770  ; 7.770  ; 7.770  ; 7.770  ;
; LDSn         ; ACSI_WRn      ; 7.760  ; 7.760  ; 7.760  ; 7.760  ;
; LDSn         ; ASn           ; 9.507  ; 9.507  ; 9.507  ; 9.507  ;
; LDSn         ; BUTTONn       ; 8.267  ;        ;        ; 8.267  ;
; LDSn         ; CA1_OUT       ; 6.805  ;        ;        ; 6.805  ;
; LDSn         ; CD[0]         ; 7.851  ; 7.851  ; 7.851  ; 7.851  ;
; LDSn         ; CD[1]         ; 7.843  ; 7.843  ; 7.843  ; 7.843  ;
; LDSn         ; CD[2]         ; 7.685  ; 7.685  ; 7.685  ; 7.685  ;
; LDSn         ; CD[3]         ; 7.843  ; 7.843  ; 7.843  ; 7.843  ;
; LDSn         ; CD[4]         ; 7.692  ; 7.692  ; 7.692  ; 7.692  ;
; LDSn         ; CD[5]         ; 7.692  ; 7.692  ; 7.692  ; 7.692  ;
; LDSn         ; CD[6]         ; 7.661  ; 7.661  ; 7.661  ; 7.661  ;
; LDSn         ; CD[7]         ; 7.661  ; 7.661  ; 7.661  ; 7.661  ;
; LDSn         ; DATA[0]       ; 10.470 ; 10.286 ; 10.286 ; 10.470 ;
; LDSn         ; DATA[1]       ; 10.451 ; 9.954  ; 9.954  ; 10.451 ;
; LDSn         ; DATA[2]       ; 10.014 ; 10.014 ; 10.014 ; 10.014 ;
; LDSn         ; DATA[3]       ; 10.295 ; 10.295 ; 10.295 ; 10.295 ;
; LDSn         ; DATA[4]       ; 10.168 ; 10.168 ; 10.168 ; 10.168 ;
; LDSn         ; DATA[5]       ; 10.440 ; 10.440 ; 10.440 ; 10.440 ;
; LDSn         ; DATA[6]       ; 10.027 ; 10.027 ; 10.027 ; 10.027 ;
; LDSn         ; DATA[7]       ; 10.287 ; 10.287 ; 10.287 ; 10.287 ;
; LDSn         ; DATA[8]       ; 10.008 ; 10.008 ; 10.008 ; 10.008 ;
; LDSn         ; DATA[9]       ; 10.286 ; 10.286 ; 10.286 ; 10.286 ;
; LDSn         ; DATA[10]      ; 10.138 ; 10.138 ; 10.138 ; 10.138 ;
; LDSn         ; DATA[11]      ; 10.384 ; 10.384 ; 10.384 ; 10.384 ;
; LDSn         ; DATA[12]      ; 10.030 ; 10.030 ; 10.030 ; 10.030 ;
; LDSn         ; DATA[13]      ; 10.389 ; 10.389 ; 10.389 ; 10.389 ;
; LDSn         ; DATA[14]      ; 9.506  ; 9.506  ; 9.506  ; 9.506  ;
; LDSn         ; DATA[15]      ; 9.675  ; 9.675  ; 9.675  ; 9.675  ;
; LDSn         ; DTACKn        ; 7.886  ; 7.886  ; 7.886  ; 7.886  ;
; LDSn         ; FC[0]         ; 9.788  ; 9.788  ; 9.788  ; 9.788  ;
; LDSn         ; FC[1]         ; 9.596  ; 9.596  ; 9.596  ; 9.596  ;
; LDSn         ; FC[2]         ; 9.596  ; 9.596  ; 9.596  ; 9.596  ;
; LDSn         ; IDE_IORDn     ; 7.299  ;        ;        ; 7.299  ;
; LDSn         ; IDE_IOWRn     ; 7.309  ;        ;        ; 7.309  ;
; LDSn         ; JOY_RLn       ; 8.031  ;        ;        ; 8.031  ;
; LDSn         ; JOY_WEn       ;        ; 8.003  ; 8.003  ;        ;
; LDSn         ; JOY_WL        ;        ; 6.784  ; 6.784  ;        ;
; LDSn         ; LDSn          ; 9.974  ; 9.974  ; 9.974  ; 9.974  ;
; LDSn         ; RAM_CAS0n     ; 9.685  ;        ;        ; 9.685  ;
; LDSn         ; RAM_CAS1n     ; 9.271  ;        ;        ; 9.271  ;
; LDSn         ; RAM_DATA[0]   ; 8.649  ; 8.465  ; 8.465  ; 8.649  ;
; LDSn         ; RAM_DATA[1]   ; 9.536  ; 9.039  ; 9.039  ; 9.536  ;
; LDSn         ; RAM_DATA[2]   ; 9.171  ; 9.171  ; 9.171  ; 9.171  ;
; LDSn         ; RAM_DATA[3]   ; 9.392  ; 9.392  ; 9.392  ; 9.392  ;
; LDSn         ; RAM_DATA[4]   ; 10.297 ; 10.297 ; 10.297 ; 10.297 ;
; LDSn         ; RAM_DATA[5]   ; 9.907  ; 9.907  ; 9.907  ; 9.907  ;
; LDSn         ; RAM_DATA[6]   ; 9.858  ; 9.858  ; 9.858  ; 9.858  ;
; LDSn         ; RAM_DATA[7]   ; 9.969  ; 9.969  ; 9.969  ; 9.969  ;
; LDSn         ; RAM_DATA[8]   ; 9.619  ; 9.619  ; 9.619  ; 9.619  ;
; LDSn         ; RAM_DATA[9]   ; 9.657  ; 9.657  ; 9.657  ; 9.657  ;
; LDSn         ; RAM_DATA[10]  ; 10.275 ; 10.275 ; 10.275 ; 10.275 ;
; LDSn         ; RAM_DATA[11]  ; 9.724  ; 9.724  ; 9.724  ; 9.724  ;
; LDSn         ; RAM_DATA[12]  ; 10.094 ; 10.094 ; 10.094 ; 10.094 ;
; LDSn         ; RAM_DATA[13]  ; 9.678  ; 9.678  ; 9.678  ; 9.678  ;
; LDSn         ; RAM_DATA[14]  ; 8.622  ; 8.622  ; 8.622  ; 8.622  ;
; LDSn         ; RAM_DATA[15]  ; 8.633  ; 8.633  ; 8.633  ; 8.633  ;
; LDSn         ; RAM_DQM0H     ; 9.110  ; 9.027  ; 9.027  ; 9.110  ;
; LDSn         ; RAM_DQM0L     ; 8.600  ; 10.701 ; 10.701 ; 8.600  ;
; LDSn         ; RAM_DQM1H     ; 9.266  ; 9.183  ; 9.183  ; 9.266  ;
; LDSn         ; RAM_DQM1L     ; 8.590  ; 10.691 ; 10.691 ; 8.590  ;
; LDSn         ; RWn           ; 10.070 ; 10.070 ; 10.070 ; 10.070 ;
; LDSn         ; UDSn          ; 9.974  ; 9.974  ; 9.974  ; 9.974  ;
; LPT_BSY      ; DATA[0]       ; 10.508 ;        ;        ; 10.508 ;
; LPT_BSY      ; DATA[8]       ; 9.705  ;        ;        ; 9.705  ;
; LPT_BSY      ; RAM_DATA[0]   ; 8.687  ;        ;        ; 8.687  ;
; LPT_BSY      ; RAM_DATA[8]   ; 9.316  ;        ;        ; 9.316  ;
; LPT_D[0]     ; DATA[0]       ; 10.269 ;        ;        ; 10.269 ;
; LPT_D[0]     ; DATA[8]       ; 9.466  ;        ;        ; 9.466  ;
; LPT_D[0]     ; RAM_DATA[0]   ; 8.448  ;        ;        ; 8.448  ;
; LPT_D[0]     ; RAM_DATA[8]   ; 9.077  ;        ;        ; 9.077  ;
; LPT_D[1]     ; DATA[1]       ; 10.091 ;        ;        ; 10.091 ;
; LPT_D[1]     ; DATA[9]       ; 9.693  ;        ;        ; 9.693  ;
; LPT_D[1]     ; RAM_DATA[1]   ; 9.176  ;        ;        ; 9.176  ;
; LPT_D[1]     ; RAM_DATA[9]   ; 9.064  ;        ;        ; 9.064  ;
; LPT_D[2]     ; DATA[2]       ; 9.895  ;        ;        ; 9.895  ;
; LPT_D[2]     ; DATA[10]      ; 9.394  ;        ;        ; 9.394  ;
; LPT_D[2]     ; RAM_DATA[2]   ; 9.052  ;        ;        ; 9.052  ;
; LPT_D[2]     ; RAM_DATA[10]  ; 9.531  ;        ;        ; 9.531  ;
; LPT_D[3]     ; DATA[3]       ; 10.501 ;        ;        ; 10.501 ;
; LPT_D[3]     ; DATA[11]      ; 11.086 ;        ;        ; 11.086 ;
; LPT_D[3]     ; RAM_DATA[3]   ; 9.598  ;        ;        ; 9.598  ;
; LPT_D[3]     ; RAM_DATA[11]  ; 9.451  ;        ;        ; 9.451  ;
; LPT_D[4]     ; DATA[4]       ; 11.131 ; 11.131 ; 11.131 ; 11.131 ;
; LPT_D[4]     ; DATA[12]      ; 10.859 ;        ;        ; 10.859 ;
; LPT_D[4]     ; RAM_DATA[4]   ; 11.260 ; 11.260 ; 11.260 ; 11.260 ;
; LPT_D[4]     ; RAM_DATA[12]  ; 10.923 ;        ;        ; 10.923 ;
; LPT_D[5]     ; DATA[5]       ; 11.281 ; 11.281 ; 11.281 ; 11.281 ;
; LPT_D[5]     ; DATA[13]      ; 10.479 ;        ;        ; 10.479 ;
; LPT_D[5]     ; RAM_DATA[5]   ; 9.940  ; 9.940  ; 9.940  ; 9.940  ;
; LPT_D[5]     ; RAM_DATA[13]  ; 9.330  ;        ;        ; 9.330  ;
; LPT_D[6]     ; DATA[6]       ; 11.221 ; 11.221 ; 11.221 ; 11.221 ;
; LPT_D[6]     ; DATA[14]      ; 10.609 ; 10.609 ; 10.609 ; 10.609 ;
; LPT_D[6]     ; RAM_DATA[6]   ; 11.052 ; 11.052 ; 11.052 ; 11.052 ;
; LPT_D[6]     ; RAM_DATA[14]  ; 9.725  ; 9.725  ; 9.725  ; 9.725  ;
; LPT_D[7]     ; DATA[7]       ; 10.478 ; 10.478 ; 10.478 ; 10.478 ;
; LPT_D[7]     ; DATA[15]      ; 10.663 ; 10.663 ; 10.663 ; 10.663 ;
; LPT_D[7]     ; RAM_DATA[7]   ; 10.160 ; 10.160 ; 10.160 ; 10.160 ;
; LPT_D[7]     ; RAM_DATA[15]  ; 9.621  ; 9.621  ; 9.621  ; 9.621  ;
; MIDI_IN      ; MIDI_TLR      ; 4.723  ;        ;        ; 4.723  ;
; RAM_DATA[0]  ; DATA[0]       ; 11.727 ;        ;        ; 11.727 ;
; RAM_DATA[0]  ; RAM_DATA[0]   ; 9.906  ;        ;        ; 9.906  ;
; RAM_DATA[1]  ; DATA[1]       ; 11.087 ;        ;        ; 11.087 ;
; RAM_DATA[1]  ; RAM_DATA[1]   ; 10.172 ;        ;        ; 10.172 ;
; RAM_DATA[2]  ; DATA[2]       ; 10.602 ;        ;        ; 10.602 ;
; RAM_DATA[2]  ; RAM_DATA[2]   ; 9.759  ;        ;        ; 9.759  ;
; RAM_DATA[3]  ; DATA[3]       ; 11.042 ;        ;        ; 11.042 ;
; RAM_DATA[3]  ; RAM_DATA[3]   ; 10.139 ;        ;        ; 10.139 ;
; RAM_DATA[4]  ; DATA[4]       ; 9.830  ; 9.830  ; 9.830  ; 9.830  ;
; RAM_DATA[4]  ; RAM_DATA[4]   ; 9.959  ; 9.959  ; 9.959  ; 9.959  ;
; RAM_DATA[5]  ; DATA[5]       ; 11.415 ; 11.415 ; 11.415 ; 11.415 ;
; RAM_DATA[5]  ; RAM_DATA[5]   ; 10.074 ; 10.074 ; 10.074 ; 10.074 ;
; RAM_DATA[6]  ; DATA[6]       ; 11.568 ; 11.568 ; 11.568 ; 11.568 ;
; RAM_DATA[6]  ; RAM_DATA[6]   ; 11.399 ; 11.399 ; 11.399 ; 11.399 ;
; RAM_DATA[7]  ; DATA[7]       ; 10.234 ; 10.234 ; 10.234 ; 10.234 ;
; RAM_DATA[7]  ; RAM_DATA[7]   ; 9.916  ; 9.916  ; 9.916  ; 9.916  ;
; RAM_DATA[8]  ; DATA[8]       ; 10.292 ;        ;        ; 10.292 ;
; RAM_DATA[8]  ; RAM_DATA[8]   ; 9.903  ;        ;        ; 9.903  ;
; RAM_DATA[9]  ; DATA[9]       ; 10.476 ;        ;        ; 10.476 ;
; RAM_DATA[9]  ; RAM_DATA[9]   ; 9.847  ;        ;        ; 9.847  ;
; RAM_DATA[10] ; DATA[10]      ; 10.205 ;        ;        ; 10.205 ;
; RAM_DATA[10] ; RAM_DATA[10]  ; 10.342 ;        ;        ; 10.342 ;
; RAM_DATA[11] ; DATA[11]      ; 11.770 ;        ;        ; 11.770 ;
; RAM_DATA[11] ; RAM_DATA[11]  ; 10.135 ;        ;        ; 10.135 ;
; RAM_DATA[12] ; DATA[12]      ; 11.247 ;        ;        ; 11.247 ;
; RAM_DATA[12] ; RAM_DATA[12]  ; 11.311 ;        ;        ; 11.311 ;
; RAM_DATA[13] ; DATA[13]      ; 11.221 ;        ;        ; 11.221 ;
; RAM_DATA[13] ; RAM_DATA[13]  ; 10.072 ;        ;        ; 10.072 ;
; RAM_DATA[14] ; DATA[14]      ; 11.089 ; 11.089 ; 11.089 ; 11.089 ;
; RAM_DATA[14] ; RAM_DATA[14]  ; 10.205 ; 10.205 ; 10.205 ; 10.205 ;
; RAM_DATA[15] ; DATA[15]      ; 11.462 ; 11.462 ; 11.462 ; 11.462 ;
; RAM_DATA[15] ; RAM_DATA[15]  ; 10.420 ; 10.420 ; 10.420 ; 10.420 ;
; RWn          ; ACSI_RDn      ; 8.200  ; 7.895  ; 7.895  ; 8.200  ;
; RWn          ; ACSI_WRn      ; 7.885  ; 8.190  ; 8.190  ; 7.885  ;
; RWn          ; ASn           ; 9.515  ; 9.515  ; 9.515  ; 9.515  ;
; RWn          ; BUTTONn       ;        ; 9.805  ; 9.805  ;        ;
; RWn          ; CA1_OUT       ;        ; 7.235  ; 7.235  ;        ;
; RWn          ; CD[0]         ; 7.746  ; 7.746  ; 7.746  ; 7.746  ;
; RWn          ; CD[1]         ; 7.629  ; 7.629  ; 7.629  ; 7.629  ;
; RWn          ; CD[2]         ; 7.580  ; 7.580  ; 7.580  ; 7.580  ;
; RWn          ; CD[3]         ; 7.738  ; 7.738  ; 7.738  ; 7.738  ;
; RWn          ; CD[4]         ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; RWn          ; CD[5]         ; 7.587  ; 7.587  ; 7.587  ; 7.587  ;
; RWn          ; CD[6]         ; 7.556  ; 7.556  ; 7.556  ; 7.556  ;
; RWn          ; CD[7]         ; 7.556  ; 7.556  ; 7.556  ; 7.556  ;
; RWn          ; DATA[0]       ; 10.534 ; 10.712 ; 10.712 ; 10.534 ;
; RWn          ; DATA[1]       ; 10.217 ; 9.859  ; 9.859  ; 10.217 ;
; RWn          ; DATA[2]       ; 10.355 ; 10.244 ; 10.244 ; 10.355 ;
; RWn          ; DATA[3]       ; 10.683 ; 10.554 ; 10.554 ; 10.683 ;
; RWn          ; DATA[4]       ; 10.085 ; 10.085 ; 10.085 ; 10.085 ;
; RWn          ; DATA[5]       ; 11.031 ; 11.031 ; 11.031 ; 11.031 ;
; RWn          ; DATA[6]       ; 9.859  ; 9.859  ; 9.859  ; 9.859  ;
; RWn          ; DATA[7]       ; 10.571 ; 10.571 ; 10.571 ; 10.571 ;
; RWn          ; DATA[8]       ; 10.272 ; 10.171 ; 10.171 ; 10.272 ;
; RWn          ; DATA[9]       ; 10.470 ; 10.290 ; 10.290 ; 10.470 ;
; RWn          ; DATA[10]      ; 10.507 ; 10.239 ; 10.239 ; 10.507 ;
; RWn          ; DATA[11]      ; 11.403 ; 11.109 ; 11.109 ; 11.403 ;
; RWn          ; DATA[12]      ; 10.502 ; 10.502 ; 10.502 ; 10.502 ;
; RWn          ; DATA[13]      ; 11.058 ; 10.925 ; 10.925 ; 11.058 ;
; RWn          ; DATA[14]      ; 10.007 ; 10.007 ; 10.007 ; 10.007 ;
; RWn          ; DATA[15]      ; 10.079 ; 10.079 ; 10.079 ; 10.079 ;
; RWn          ; DTACKn        ; 7.769  ; 7.769  ; 7.769  ; 7.769  ;
; RWn          ; FC[0]         ; 9.796  ; 9.796  ; 9.796  ; 9.796  ;
; RWn          ; FC[1]         ; 9.604  ; 9.604  ; 9.604  ; 9.604  ;
; RWn          ; FC[2]         ; 9.604  ; 9.604  ; 9.604  ; 9.604  ;
; RWn          ; FLASH_CEn     ;        ; 11.017 ; 11.017 ;        ;
; RWn          ; FLASH_OEn     ;        ; 11.515 ; 11.515 ;        ;
; RWn          ; IDE_D_EN_INn  ;        ; 9.038  ; 9.038  ;        ;
; RWn          ; IDE_D_EN_OUTn ; 8.858  ;        ;        ; 8.858  ;
; RWn          ; IDE_IORDn     ;        ; 8.940  ; 8.940  ;        ;
; RWn          ; IDE_IOWRn     ; 8.967  ;        ;        ; 8.967  ;
; RWn          ; JOY_RHn       ; 9.495  ; 8.661  ; 8.661  ; 9.495  ;
; RWn          ; JOY_RLn       ; 10.412 ; 9.571  ; 9.571  ; 10.412 ;
; RWn          ; JOY_WEn       ; 9.543  ; 10.384 ; 10.384 ; 9.543  ;
; RWn          ; JOY_WL        ; 9.161  ; 8.268  ; 8.268  ; 9.161  ;
; RWn          ; LDSn          ; 9.982  ; 9.982  ; 9.982  ; 9.982  ;
; RWn          ; RAM_DATA[0]   ; 8.474  ; 8.474  ; 8.474  ; 8.474  ;
; RWn          ; RAM_DATA[1]   ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; RWn          ; RAM_DATA[2]   ; 8.699  ; 8.699  ; 8.699  ; 8.699  ;
; RWn          ; RAM_DATA[3]   ; 9.053  ; 9.053  ; 9.053  ; 9.053  ;
; RWn          ; RAM_DATA[4]   ; 9.053  ; 9.053  ; 9.053  ; 9.053  ;
; RWn          ; RAM_DATA[5]   ; 9.467  ; 9.467  ; 9.467  ; 9.467  ;
; RWn          ; RAM_DATA[6]   ; 9.267  ; 9.267  ; 9.267  ; 9.267  ;
; RWn          ; RAM_DATA[7]   ; 9.467  ; 9.467  ; 9.467  ; 9.467  ;
; RWn          ; RAM_DATA[8]   ; 8.947  ; 8.947  ; 8.947  ; 8.947  ;
; RWn          ; RAM_DATA[9]   ; 8.947  ; 8.947  ; 8.947  ; 8.947  ;
; RWn          ; RAM_DATA[10]  ; 8.947  ; 8.947  ; 8.947  ; 8.947  ;
; RWn          ; RAM_DATA[11]  ; 8.937  ; 8.937  ; 8.937  ; 8.937  ;
; RWn          ; RAM_DATA[12]  ; 8.800  ; 8.800  ; 8.800  ; 8.800  ;
; RWn          ; RAM_DATA[13]  ; 8.800  ; 8.800  ; 8.800  ; 8.800  ;
; RWn          ; RAM_DATA[14]  ; 8.591  ; 8.591  ; 8.591  ; 8.591  ;
; RWn          ; RAM_DATA[15]  ; 8.591  ; 8.591  ; 8.591  ; 8.591  ;
; RWn          ; RAM_DQM0H     ;        ; 8.839  ; 8.839  ;        ;
; RWn          ; RAM_DQM0L     ;        ; 8.251  ; 8.251  ;        ;
; RWn          ; RAM_DQM1H     ;        ; 8.995  ; 8.995  ;        ;
; RWn          ; RAM_DQM1L     ;        ; 8.241  ; 8.241  ;        ;
; RWn          ; RAM_WEn       ; 9.417  ;        ;        ; 9.417  ;
; RWn          ; ROM0n         ;        ; 9.796  ; 9.796  ;        ;
; RWn          ; ROM1n         ;        ; 10.627 ; 10.627 ;        ;
; RWn          ; ROM2n         ;        ; 10.191 ; 10.191 ;        ;
; RWn          ; ROM3n         ;        ; 9.701  ; 9.701  ;        ;
; RWn          ; ROM4n         ;        ; 9.513  ; 9.513  ;        ;
; RWn          ; ROM5n         ;        ; 10.476 ; 10.476 ;        ;
; RWn          ; ROM6n         ;        ; 9.936  ; 9.936  ;        ;
; RWn          ; RWn           ; 10.078 ; 10.078 ; 10.078 ; 10.078 ;
; RWn          ; UDSn          ; 9.982  ; 9.982  ; 9.982  ; 9.982  ;
; SCSI_ACKn    ; CD[0]         ; 7.951  ; 7.951  ; 7.951  ; 7.951  ;
; SCSI_ATNn    ; CD[1]         ; 8.745  ; 8.745  ; 8.745  ; 8.745  ;
; SCSI_BSYn    ; CD[6]         ;        ; 7.019  ; 7.019  ;        ;
; SCSI_D[0]    ; CD[0]         ; 8.485  ; 8.485  ; 8.485  ; 8.485  ;
; SCSI_D[1]    ; CD[1]         ; 8.138  ; 8.138  ; 8.138  ; 8.138  ;
; SCSI_D[2]    ; CD[2]         ;        ; 7.702  ; 7.702  ;        ;
; SCSI_D[3]    ; CD[3]         ; 8.804  ; 8.804  ; 8.804  ; 8.804  ;
; SCSI_D[4]    ; CD[4]         ; 6.442  ; 6.442  ; 6.442  ; 6.442  ;
; SCSI_D[5]    ; CD[5]         ; 6.256  ; 6.256  ; 6.256  ; 6.256  ;
; SCSI_D[6]    ; CD[6]         ; 7.643  ; 7.643  ; 7.643  ; 7.643  ;
; SCSI_D[7]    ; CD[7]         ;        ; 7.825  ; 7.825  ;        ;
; SCSI_DCn     ; CD[3]         ; 7.961  ; 7.961  ; 7.961  ; 7.961  ;
; SCSI_DCn     ; SCSI_CTRL_ENn ; 7.254  ; 7.254  ; 7.254  ; 7.254  ;
; SCSI_DCn     ; SCSI_D[0]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_DCn     ; SCSI_D[1]     ; 7.850  ; 7.850  ; 7.850  ; 7.850  ;
; SCSI_DCn     ; SCSI_D[2]     ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_DCn     ; SCSI_D[3]     ; 7.955  ; 7.955  ; 7.955  ; 7.955  ;
; SCSI_DCn     ; SCSI_D[4]     ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; SCSI_DCn     ; SCSI_D[5]     ; 7.974  ; 7.974  ; 7.974  ; 7.974  ;
; SCSI_DCn     ; SCSI_D[6]     ; 7.983  ; 7.983  ; 7.983  ; 7.983  ;
; SCSI_DCn     ; SCSI_D[7]     ; 7.983  ; 7.983  ; 7.983  ; 7.983  ;
; SCSI_DCn     ; SCSI_DP       ; 7.860  ; 7.860  ; 7.860  ; 7.860  ;
; SCSI_DP      ; CD[0]         ; 8.140  ; 8.140  ; 8.140  ; 8.140  ;
; SCSI_IOn     ; CD[2]         ;        ; 7.638  ; 7.638  ;        ;
; SCSI_IOn     ; CD[3]         ; 9.153  ; 9.153  ; 9.153  ; 9.153  ;
; SCSI_IOn     ; SCSI_CTRL_ENn ; 6.662  ; 7.442  ; 7.442  ; 6.662  ;
; SCSI_IOn     ; SCSI_D[0]     ; 7.258  ; 7.258  ; 7.258  ; 7.258  ;
; SCSI_IOn     ; SCSI_D[1]     ; 7.258  ; 7.258  ; 7.258  ; 7.258  ;
; SCSI_IOn     ; SCSI_D[2]     ; 7.363  ; 7.363  ; 7.363  ; 7.363  ;
; SCSI_IOn     ; SCSI_D[3]     ; 7.363  ; 7.363  ; 7.363  ; 7.363  ;
; SCSI_IOn     ; SCSI_D[4]     ; 7.382  ; 7.382  ; 7.382  ; 7.382  ;
; SCSI_IOn     ; SCSI_D[5]     ; 7.382  ; 7.382  ; 7.382  ; 7.382  ;
; SCSI_IOn     ; SCSI_D[6]     ; 7.391  ; 7.391  ; 7.391  ; 7.391  ;
; SCSI_IOn     ; SCSI_D[7]     ; 7.391  ; 7.391  ; 7.391  ; 7.391  ;
; SCSI_IOn     ; SCSI_DP       ; 7.268  ; 7.268  ; 7.268  ; 7.268  ;
; SCSI_IOn     ; SCSI_RDn      ; 6.116  ;        ;        ; 6.116  ;
; SCSI_IOn     ; SCSI_WRn      ;        ; 6.098  ; 6.098  ;        ;
; SCSI_MSGn    ; CD[3]         ; 8.794  ; 8.794  ; 8.794  ; 8.794  ;
; SCSI_MSGn    ; CD[4]         ;        ; 6.001  ; 6.001  ;        ;
; SCSI_MSGn    ; SCSI_CTRL_ENn ; 7.083  ; 7.083  ; 7.083  ; 7.083  ;
; SCSI_MSGn    ; SCSI_D[0]     ; 7.679  ; 7.679  ; 7.679  ; 7.679  ;
; SCSI_MSGn    ; SCSI_D[1]     ; 7.679  ; 7.679  ; 7.679  ; 7.679  ;
; SCSI_MSGn    ; SCSI_D[2]     ; 7.784  ; 7.784  ; 7.784  ; 7.784  ;
; SCSI_MSGn    ; SCSI_D[3]     ; 7.784  ; 7.784  ; 7.784  ; 7.784  ;
; SCSI_MSGn    ; SCSI_D[4]     ; 7.803  ; 7.803  ; 7.803  ; 7.803  ;
; SCSI_MSGn    ; SCSI_D[5]     ; 7.803  ; 7.803  ; 7.803  ; 7.803  ;
; SCSI_MSGn    ; SCSI_D[6]     ; 7.812  ; 7.812  ; 7.812  ; 7.812  ;
; SCSI_MSGn    ; SCSI_D[7]     ; 7.812  ; 7.812  ; 7.812  ; 7.812  ;
; SCSI_MSGn    ; SCSI_DP       ; 7.689  ; 7.689  ; 7.689  ; 7.689  ;
; SCSI_REQn    ; CD[3]         ; 8.859  ; 8.859  ; 8.859  ; 8.859  ;
; SCSI_REQn    ; CD[5]         ;        ; 5.946  ; 5.946  ;        ;
; SCSI_REQn    ; SCSI_CTRL_ENn ; 7.148  ;        ;        ; 7.148  ;
; SCSI_REQn    ; SCSI_D[0]     ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; SCSI_REQn    ; SCSI_D[1]     ; 7.744  ; 7.744  ; 7.744  ; 7.744  ;
; SCSI_REQn    ; SCSI_D[2]     ; 7.849  ; 7.849  ; 7.849  ; 7.849  ;
; SCSI_REQn    ; SCSI_D[3]     ; 7.849  ; 7.849  ; 7.849  ; 7.849  ;
; SCSI_REQn    ; SCSI_D[4]     ; 7.868  ; 7.868  ; 7.868  ; 7.868  ;
; SCSI_REQn    ; SCSI_D[5]     ; 7.868  ; 7.868  ; 7.868  ; 7.868  ;
; SCSI_REQn    ; SCSI_D[6]     ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SCSI_REQn    ; SCSI_D[7]     ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SCSI_REQn    ; SCSI_DP       ; 7.754  ; 7.754  ; 7.754  ; 7.754  ;
; SCSI_RSTn    ; CD[7]         ;        ; 7.478  ; 7.478  ;        ;
; SCSI_SELn    ; CD[1]         ; 7.877  ; 7.877  ; 7.877  ; 7.877  ;
; SD_AVR_ENn   ; RESETn        ;        ; 7.067  ; 7.067  ;        ;
; SD_AVR_ENn   ; SD_BOOT_REQ   ;        ; 7.169  ; 7.169  ;        ;
; SD_AVR_ENn   ; SD_SPI_MISO   ;        ; 7.212  ; 7.212  ;        ;
; SD_AVR_ENn   ; SYS_BOOT_REQ  ; 6.074  ;        ;        ; 6.074  ;
; SD_AVR_ENn   ; SYS_SPI_MISO  ; 6.273  ;        ;        ; 6.273  ;
; SD_RESETn    ; COM_TxD       ; 8.327  ; 8.327  ; 8.327  ; 8.327  ;
; UDSn         ; ACSI_RDn      ; 9.213  ; 9.213  ; 9.213  ; 9.213  ;
; UDSn         ; ACSI_WRn      ; 9.203  ; 9.203  ; 9.203  ; 9.203  ;
; UDSn         ; ASn           ; 9.958  ; 9.958  ; 9.958  ; 9.958  ;
; UDSn         ; CA1_OUT       ; 8.248  ;        ;        ; 8.248  ;
; UDSn         ; CD[0]         ; 9.294  ; 9.294  ; 9.294  ; 9.294  ;
; UDSn         ; CD[1]         ; 9.286  ; 9.286  ; 9.286  ; 9.286  ;
; UDSn         ; CD[2]         ; 9.128  ; 9.128  ; 9.128  ; 9.128  ;
; UDSn         ; CD[3]         ; 9.286  ; 9.286  ; 9.286  ; 9.286  ;
; UDSn         ; CD[4]         ; 9.135  ; 9.135  ; 9.135  ; 9.135  ;
; UDSn         ; CD[5]         ; 9.135  ; 9.135  ; 9.135  ; 9.135  ;
; UDSn         ; CD[6]         ; 9.104  ; 9.104  ; 9.104  ; 9.104  ;
; UDSn         ; CD[7]         ; 9.104  ; 9.104  ; 9.104  ; 9.104  ;
; UDSn         ; DATA[0]       ; 11.203 ; 11.203 ; 11.203 ; 11.203 ;
; UDSn         ; DATA[1]       ; 11.203 ; 11.203 ; 11.203 ; 11.203 ;
; UDSn         ; DATA[2]       ; 11.183 ; 10.975 ; 10.975 ; 11.183 ;
; UDSn         ; DATA[3]       ; 11.183 ; 11.183 ; 11.183 ; 11.183 ;
; UDSn         ; DATA[4]       ; 10.721 ; 10.721 ; 10.721 ; 10.721 ;
; UDSn         ; DATA[5]       ; 11.097 ; 11.097 ; 11.097 ; 11.097 ;
; UDSn         ; DATA[6]       ; 10.566 ; 10.566 ; 10.566 ; 10.566 ;
; UDSn         ; DATA[7]       ; 10.826 ; 10.826 ; 10.826 ; 10.826 ;
; UDSn         ; DATA[8]       ; 10.170 ; 10.170 ; 10.170 ; 10.170 ;
; UDSn         ; DATA[9]       ; 10.374 ; 10.374 ; 10.374 ; 10.374 ;
; UDSn         ; DATA[10]      ; 10.390 ; 10.390 ; 10.390 ; 10.390 ;
; UDSn         ; DATA[11]      ; 11.041 ; 11.041 ; 11.041 ; 11.041 ;
; UDSn         ; DATA[12]      ; 10.395 ; 10.395 ; 10.395 ; 10.395 ;
; UDSn         ; DATA[13]      ; 10.892 ; 10.892 ; 10.892 ; 10.892 ;
; UDSn         ; DATA[14]      ; 10.048 ; 10.048 ; 10.048 ; 10.048 ;
; UDSn         ; DATA[15]      ; 10.217 ; 10.217 ; 10.217 ; 10.217 ;
; UDSn         ; DTACKn        ; 8.022  ; 8.022  ; 8.022  ; 8.022  ;
; UDSn         ; FC[0]         ; 10.239 ; 10.239 ; 10.239 ; 10.239 ;
; UDSn         ; FC[1]         ; 10.047 ; 10.047 ; 10.047 ; 10.047 ;
; UDSn         ; FC[2]         ; 10.047 ; 10.047 ; 10.047 ; 10.047 ;
; UDSn         ; JOY_RHn       ; 7.689  ;        ;        ; 7.689  ;
; UDSn         ; LDSn          ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
; UDSn         ; RAM_CAS0n     ; 9.515  ;        ;        ; 9.515  ;
; UDSn         ; RAM_CAS1n     ; 9.101  ;        ;        ; 9.101  ;
; UDSn         ; RAM_DATA[0]   ; 9.849  ; 9.882  ; 9.882  ; 9.849  ;
; UDSn         ; RAM_DATA[1]   ; 10.427 ; 10.437 ; 10.437 ; 10.427 ;
; UDSn         ; RAM_DATA[2]   ; 10.580 ; 10.132 ; 10.132 ; 10.580 ;
; UDSn         ; RAM_DATA[3]   ; 10.314 ; 10.314 ; 10.314 ; 10.314 ;
; UDSn         ; RAM_DATA[4]   ; 10.850 ; 10.850 ; 10.850 ; 10.850 ;
; UDSn         ; RAM_DATA[5]   ; 10.539 ; 10.539 ; 10.539 ; 10.539 ;
; UDSn         ; RAM_DATA[6]   ; 10.397 ; 10.397 ; 10.397 ; 10.397 ;
; UDSn         ; RAM_DATA[7]   ; 10.508 ; 10.508 ; 10.508 ; 10.508 ;
; UDSn         ; RAM_DATA[8]   ; 9.781  ; 9.781  ; 9.781  ; 9.781  ;
; UDSn         ; RAM_DATA[9]   ; 9.745  ; 9.745  ; 9.745  ; 9.745  ;
; UDSn         ; RAM_DATA[10]  ; 10.527 ; 10.527 ; 10.527 ; 10.527 ;
; UDSn         ; RAM_DATA[11]  ; 10.106 ; 10.106 ; 10.106 ; 10.106 ;
; UDSn         ; RAM_DATA[12]  ; 10.459 ; 10.459 ; 10.459 ; 10.459 ;
; UDSn         ; RAM_DATA[13]  ; 9.743  ; 9.743  ; 9.743  ; 9.743  ;
; UDSn         ; RAM_DATA[14]  ; 9.164  ; 9.164  ; 9.164  ; 9.164  ;
; UDSn         ; RAM_DATA[15]  ; 9.175  ; 9.175  ; 9.175  ; 9.175  ;
; UDSn         ; RAM_DQM0H     ; 8.718  ; 11.116 ; 11.116 ; 8.718  ;
; UDSn         ; RAM_DQM0L     ; 8.181  ; 8.117  ; 8.117  ; 8.181  ;
; UDSn         ; RAM_DQM1H     ; 8.874  ; 11.272 ; 11.272 ; 8.874  ;
; UDSn         ; RAM_DQM1L     ; 8.171  ; 8.107  ; 8.107  ; 8.171  ;
; UDSn         ; RWn           ; 10.521 ; 10.521 ; 10.521 ; 10.521 ;
; UDSn         ; UDSn          ; 10.425 ; 10.425 ; 10.425 ; 10.425 ;
+--------------+---------------+--------+--------+--------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                               ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+-----------+--------------+-----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths  ; RF Paths     ; FF Paths  ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+-----------+--------------+-----------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0         ; 0            ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0         ; false path   ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 59615        ; 3542      ; 324          ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 2            ; 0         ; 0            ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0         ; false path   ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 59615        ; 3542      ; 324          ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 2            ; 0         ; 0            ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60945        ; 3545      ; 24           ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60945        ; 3545      ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 57565        ; 3542      ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 57565        ; 3542      ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 149510       ; 3542      ; 1            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 149510       ; 3542      ; 1            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 57703        ; 3542      ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 102          ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 102          ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 612          ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 612          ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 102          ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 5180         ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 6            ; 0         ; 0            ; 0         ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+-----------+--------------+-----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+-----------+--------------+-----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths     ; FR Paths  ; RF Paths     ; FF Paths  ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+-----------+--------------+-----------+
; CLK_PLL1                                                   ; CLK_PLL1                                                   ; 51           ; 0         ; 0            ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path   ; 0         ; false path   ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 59615        ; 3542      ; 324          ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 1            ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 2            ; 0         ; 0            ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path   ; 0         ; false path   ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; > 2147483647 ; 618367359 ; > 2147483647 ; 101872311 ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 379547948    ; 3617      ; 62563536     ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 59615        ; 3542      ; 324          ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 1            ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 2            ; 0         ; 0            ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; false path   ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 60945        ; 3545      ; 24           ; 0         ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; false path   ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; > 2147483647 ; 442308946 ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 270829890    ; 3772      ; 46           ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 60945        ; 3545      ; 24           ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 57565        ; 3542      ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 57565        ; 3542      ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 149510       ; 3542      ; 1            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 149510       ; 3542      ; 1            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; 57703        ; 3542      ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 102          ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 102          ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 612          ; 0         ; 0            ; 0         ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 612          ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 102          ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1   ; 5180         ; 0         ; 0            ; 0         ;
; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2   ; 6            ; 0         ; 0            ; 0         ;
+------------------------------------------------------------+------------------------------------------------------------+--------------+-----------+--------------+-----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                      ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 11620      ; 0        ; 40         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 11620      ; 0        ; 40         ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 11620      ; 0        ; 40         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 11620      ; 0        ; 40         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13         ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13         ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13         ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13         ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                       ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; From Clock                                                 ; To Clock                                                   ; RR Paths   ; FR Paths ; RF Paths   ; FF Paths ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 11620      ; 0        ; 40         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; 11620      ; 0        ; 40         ; 0        ;
; CLK_PLL1                                                   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; false path ; 0        ; false path ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 10539      ; 5        ; 36         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 11620      ; 0        ; 40         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; 11620      ; 0        ; 40         ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13         ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1   ; 13         ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0   ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13         ; 0        ; 0          ; 0        ;
; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 ; cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 ; 13         ; 0        ; 0          ; 0        ;
+------------------------------------------------------------+------------------------------------------------------------+------------+----------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+-------------------------------------------------+
; Unconstrained Paths                             ;
+---------------------------------+-------+-------+
; Property                        ; Setup ; Hold  ;
+---------------------------------+-------+-------+
; Illegal Clocks                  ; 0     ; 0     ;
; Unconstrained Clocks            ; 0     ; 0     ;
; Unconstrained Input Ports       ; 122   ; 122   ;
; Unconstrained Input Port Paths  ; 50104 ; 50104 ;
; Unconstrained Output Ports      ; 226   ; 226   ;
; Unconstrained Output Port Paths ; 42440 ; 42440 ;
+---------------------------------+-------+-------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Dec 09 18:29:50 2021
Info: Command: quartus_sta SUSKA-III-C -c SUSKA-III-C
Info: qsta_default_script.tcl version: #1
Warning: Parallel compilation is not licensed and has been disabled
Info: Evaluating HDL-embedded SDC commands
    Info: Entity sld_hub
        Info: create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}]
        Info: set_clock_groups -asynchronous -group {altera_reserved_tck}
Info: Reading SDC File: '../../../rtl/vhdl/Suska-III-C/suska_cycloneII_core_falcon.sdc'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0} {I_AUXCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -divide_by 13 -multiply_by 32 -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1} {I_AUXCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_AUXCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2} {I_AUXCLOCKS|altpll_component|pll|clk[2]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0} {I_SYSCLOCKS|altpll_component|pll|clk[0]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[1]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
    Info: create_generated_clock -source {I_SYSCLOCKS|altpll_component|pll|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1} {I_SYSCLOCKS|altpll_component|pll|clk[1]}
Info: Analyzing Slow Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -12.133
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:   -12.133     -8599.655 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:   -12.133     -8599.655 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:   -11.466    -12013.941 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:   -11.466    -12013.941 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    -3.911      -369.126 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    -1.381      -500.405 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    59.898         0.000 CLK_PLL1 
    Info:    61.245         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is -3.460
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -3.460      -746.183 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    -3.460      -746.183 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    -3.079      -514.643 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    -2.006      -112.700 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    -2.006      -112.700 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.445         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.912         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 21.924
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    21.924         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    21.924         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    28.501         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    28.501         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
Info: Worst-case removal slack is 2.146
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     2.146         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     2.146         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     2.912         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     2.912         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 10.131
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    10.131         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.061         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.420         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    28.943         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    28.943         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.139         0.000 CLK_PLL1 
    Info:    30.139         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    97.531         0.000 altera_reserved_tck 
Info: The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Info: Started post-fitting delay annotation
Warning: Found 234 output pins without output pin load capacitance assignment
    Info: Pin "VMAn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_WGn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_WDn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_STEPn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_DIRCn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_MOn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "MIDI_OLR" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "MIDI_TLR" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "COM_TxD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RESETn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FC[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FC[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FC[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "BERRn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HALTn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "BGACKn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DTACKn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UDSn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LDSn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ASn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RWn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DATA[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ADR[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DATA[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HSYNC" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "VSYNC" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CD[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_D[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_DP" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_BSYn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_MSGn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_REQn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_DCn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_IOn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_ATNn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_RSTn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_ACKn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_SELn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_D[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DS1392_D" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CLK_AUX" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "BGOn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "E" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM6n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM5n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM4n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM3n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM2n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM1n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ROM0n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_RAS0n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_CAS0n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_WEn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_RAS1n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_CAS1n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DQM0H" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DQM0L" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DQM1H" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_DQM1L" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_ADR[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_BA[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "RAM_BA[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UDATA[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UDATA[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UDATA[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UDATA[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LDATA[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LDATA[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LDATA[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LDATA[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LFS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "VDCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LLCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_R[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_R[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_R[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_R[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_G[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_G[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_G[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_G[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_B[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_B[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_B[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_B[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CRT_MONO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "GPO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_D1SELn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_D0SELn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FDD_SDSEL" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CA1_OUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HDCSn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "HDACKn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ACSI_RDn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "ACSI_WRn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_RDn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_WRn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SCSI_CTRL_ENn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IDE_CS0n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IDE_CS1n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IDE_IORDn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IDE_IOWRn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IDE_D_EN_INn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "IDE_D_EN_OUTn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "KEYB_TxD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "UART_MIDI_RTSn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "COM_RTS" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "COM_DTR" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "LPT_STRB" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "JOY_RHn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "JOY_RLn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "JOY_WL" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "JOY_WEn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "BUTTONn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "PADRSTn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DS1392_SCL" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DS1392_CE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FLASH_ADR_19" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FLASH_ADR_18" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FLASH_WEn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FLASH_OEn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FLASH_CEn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "xFF827E_D[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "xFF827E_D[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "xFF827E_D[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "xFF827E_D[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "xFF827E_D[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "xFF827E_D[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "FCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "MWK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "MWD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "MWEn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DAC_SCLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DAC_SYNCn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DAC_SDATA" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "DAC_LDACn" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "YM_OUT_A" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "YM_OUT_B" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "YM_OUT_C" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CODEC_SDOUT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "CODEC_SSYNC" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "PLL_FAULT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "BOOT_LED" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_AVR_CLK" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_SPI_MISO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SD_BOOT_REQ" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SYS_SPI_MISO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SYS_BOOT_REQ" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -0.590
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -0.590       -50.514 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    -0.040        -0.040 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    -0.040        -0.040 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     0.269         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     0.269         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     4.302         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    61.372         0.000 CLK_PLL1 
    Info:    62.012         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
Info: Worst-case hold slack is -1.600
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    -1.600      -450.465 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    -1.600      -450.465 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    -1.460      -348.941 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    -1.084      -141.124 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    -1.084      -141.124 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.215         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:     0.358         0.000 CLK_PLL1 
Info: Worst-case recovery slack is 27.164
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    27.164         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    27.164         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    29.992         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    29.992         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
Info: Worst-case removal slack is 0.983
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.983         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:     0.983         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:     1.252         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:     1.252         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
Info: Worst-case minimum pulse width slack is 10.568
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    10.568         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1 
    Info:    13.498         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk1~1 
    Info:    18.531         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk0 
    Info:    29.231         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0 
    Info:    29.231         0.000 cyclone2_pll_1:I_SYSCLOCKS|altpll:altpll_component|_clk0~1 
    Info:    30.250         0.000 CLK_PLL1 
    Info:    30.250         0.000 cyclone2_pll_2:I_AUXCLOCKS|altpll:altpll_component|_clk2 
    Info:    31.250         0.000 CLK_PLL2 
    Info:    31.250         0.000 CRT_PIN4_CLK1 
    Info:    97.778         0.000 altera_reserved_tck 
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 646 megabytes
    Info: Processing ended: Thu Dec 09 18:30:37 2021
    Info: Elapsed time: 00:00:47
    Info: Total CPU time (on all processors): 00:00:47


